JPH01123439A - Wiring structure for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive accomplishment of high integration of a circuit device by a method wherein the wirings adjoining each other are formed in such a manner that a first region and a second region are adjacently positioned, the width of the second region is formed narrower than that of the first region, and the arrangement pitch of a metal wiring is made small. CONSTITUTION:First regions 1a and 2a of wirings 1 and 2 are positioned adjacent to second regions 1b and 2b, which are adjacently located, of the wiring 2. The regions 1a and 1b are extended toward the regions 1b and 2b in the length corresponding to the difference 'e' between the width of the regions 1a and 2a and the width of the regions 1b and 2b. The interval 'd' between the wirings 1 and 2 is determined by photolithographic technique, and said interval 'd' is set at the minimum wiring interval or more of the distance between the wirings 1 and 2 in which the wirings 1 and 2 are nor short-circuited. The interval between the extended wires of the edge of contact holes 3 and 4 is small definitely. As a result, the arrangement pitch of the wirings 1 and 2 can be made small, and the high integration of the circuit device can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring structure for a semiconductor integrated circuit device, and more particularly to a wiring structure for a semiconductor integrated circuit device suitable for ultra-miniaturization of semiconductor integrated circuit devices.

[Prior Art] FIG. 6 is a schematic plan view showing a wiring structure of a conventional semiconductor integrated circuit device. The metal wiring 15 and the metal wiring 16 are formed so as to extend in parallel with a distance d between them,
A contact hole 3 or a contact hole 4 is provided in the center thereof, respectively. The width a of the metal wiring 16 is determined by the width of the contact hole 4 and the margin C between the edge of the contact hole 4 and the edge of the wiring 16. The metal wiring 15 also has a similar structure to the metal wiring 16.

The distance d between the metal wirings 15 and 16 is determined by considering the processing accuracy of lithography technology and etching technology.
5 and the metal wiring 16 is determined by the lower limit interval (minimum wiring interval) at which no short circuit occurs.

Therefore, in such a wiring structure, if the minimum wiring spacing is do, then the spacing f between the contact holes 3 and 4 must satisfy the following equation (1).

f≧2c+d□ +++++ (1) Also,
Width g of the formation area of the metal wiring 15.16, that is, the metal wiring 1
The distance g between the outer edges of 5.16 is (f+2c+2b
)Yo')44rahru.

Figure 7 shows the wiring structure of a conventional semiconductor integrated circuit device.
FIG. 3 is a schematic plan view showing an example of application to source wiring and drain wiring of an S transistor. A pair of parallel metal wiring lines 15 and 16 are formed on the source 5 and drain 6 regions of the MOS transistor with an insulating film interposed therebetween.
A gate 7 is arranged between the metal wirings 15 and 16. The source 5 and drain 6 and the metal wiring 15 and 16 are formed through three contact holes 3 and 3 in the insulating film, respectively.
After forming the contact holes 3.4, electrical connection is achieved by filling the contact holes 3.4 with metal wiring material.

Note that the gate length is 1.0 to 2.0 μm. In addition, the distance i between the edge of the gate 7 and the edge of the contact hole 3 or 4 takes into account alignment errors in the photolithography process and margins in the etching process for the gate 7 and contact holes 3 and 4. The thickness is approximately 1.0 to 1.5 μm.

In a MOS transistor with such a design rule, the distance f between the contact hole 3 and the contact hole 4 is (h+2 i ), as is clear from FIG. 7, and is about 3.0 to 5. OIJ, m. Therefore,
If the margin C between the edges of the contact holes 3 and 4 and the edges of the metal wiring 15 and 16 is set to 0.8 to 1.5 μm, the distance d between the metal wiring 15° and 16 (=f-2c)
is 1.4 to 2 μm. This is large enough so
With current lithography and etching techniques, it is easy to form the metal lines 15, 16 so that they do not short-circuit each other. Note that the width g between the outer edges of the metal wires 15 and 16, which defines the area necessary for forming the metal wires 15.16, is the same as the width g shown in FIG.

FIG. 8 is a schematic plan view showing a wiring structure of a conventional semiconductor integrated circuit device having a multilayer wiring structure. In FIG. 8, the same parts as in FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted. Two parallel metal wires 15 and 16 are formed in the upper layer, and two parallel metal wires 17 perpendicular to the metal wires 15 and 16 are formed in the lower layer via an insulating film between the eyebrows (not shown).
．． 18 are formed. Metal lines 17 and 18 have a similar structure to metal lines 15 and 16. Upper layer metal wiring 1
5 and the lower metal wiring 18 are through-hole contacts 2
The metal wiring 16 and the metal wiring 17 are connected by a through-hole contact 26. In this example as well, the above-mentioned equation (1) holds true. Then, the width g1 of the area required to form the upper layer metal wiring and the width g of the area required to form the lower layer metal wiring.
2 is the same as the width g between the outer edges of the metal wiring 15°16 in FIG.

[Problems to be solved by the invention] However, recently, semiconductor integrated circuit devices (for example, M
With the miniaturization of OS transistors),
The gate length h (see FIG. 7) has a submicron size of 1.0 μm or less.

In addition, improvements in photolithography technology and etching technology have enabled alignment (
The alignment error is reduced, and the margin in the etching process for gates and contact holes can be reduced.

As a result, the distance i between the gate 7 and the contact hole 3 or 4 is approximately 0.5 to 0.6 μm. Also,
If the contact holes 3 and 4 are formed by self-alignment with respect to the gate 7, the distance i between the gate 7 and the contact holes 3 and 4 will be approximately 0.2 to 0.4μ.
m and becomes even finer.

When attempting to form metal wiring for a MOS transistor with such design rules, the distance f (=h+2i) between contact holes is approximately 1.0 to 1.8μ.
For example, contact hole 3.4
Even if the margin C between the metal wires 15° and 16 is as small as about 0.6 μm, as is clear from equation (1) above, there is not enough room to provide the minimum wiring spacing do between the metal wires.

Therefore, in order to make the spacing d between the metal wirings a minimum wiring spacing of 60 or more without causing a short circuit, the spacing f between the contact holes must exceed the spacing required from the processing accuracy of photolithography technology and etching technology. It needs to be bigger than necessary. Therefore, metal wiring 1
The width g of the region required to form 5.16 becomes larger than necessary, which impedes miniaturization of semiconductor devices.

Furthermore, since the areas of the source region and the drain region become large, the source junction capacitance and the train junction capacitance increase, resulting in a decrease in the operating speed of the MOS transistor.

Furthermore, in order to increase the degree of integration of semiconductor integrated circuit devices, it is necessary to reduce the width of the formation region of the wiring interconnecting such fine MOS transistors. Therefore, even in the multilayer wiring structure connected by through-hole contacts 25 and 26 shown in FIG. 8, the large width g2 of the wiring formation region is a factor that hinders the high integration of semiconductor integrated circuit devices. It has become.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a wiring structure for a semiconductor integrated circuit device that can reduce the spacing between the centers of metal wiring (array pitch) and enable high-speed operation and high integration of the semiconductor integrated circuit device.

[Means for Solving the Problems] A wiring structure for a semiconductor integrated circuit device according to the present invention includes a first region in which a contact portion is provided, and a first region narrower than the first region. and a second region connecting the regions, the first region being arranged adjacent to the second region of the adjacent wire at a predetermined interval. It is characterized by

[Function] In the present invention, the parallel wiring has a wide first region in which a contact portion is provided, and the contact portion allows the first region to connect to other wiring or transistors through an insulating film. Reliably connects to the diffusion layer, etc. In each wiring, the first regions are connected by a second region narrower than the first region. The parallel wirings that are adjacent in a plane are formed at a predetermined interval so that the first region and the second region are adjacent to each other. in this way,
Since the first region and the second region, which is narrower than the first region, are formed adjacent to each other, the arrangement pitch can be maintained while ensuring the spacing between adjacent wirings is equal to or greater than the minimum wiring spacing. It becomes easy to miniaturize the semiconductor integrated circuit device by reducing the size of the semiconductor integrated circuit device.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic plan view showing a wiring structure of a semiconductor integrated circuit device according to a first embodiment of the present invention. metal wiring 1
and metal wiring 2 are formed in parallel, and have first regions 1a and 2a in which contact holes 3 and 4 are provided, respectively, and a second region 1 that connects these first regions la and 2a.
b, 2b. Contact holes 3 and 4 having a width b are formed in the insulating film below the first regions 1a and 2a, respectively, and contact portions are formed by filling the contact holes 3 and 4 with a metal wiring material. has been done.

The edges of the contact holes 3 and 4 and the first region 1a,
A margin C is provided between the edge of 2a. The second regions 1b, 2b have a width a smaller than the width of the first regions 1a, 2a. In other words, the width a is smaller than the sum of the margin C between the metal wiring 1 and the contact hole 3, and has the relationship shown in equation (2) below. This relationship holds true for the metal wiring 2 as well.

a<b+2c (2) The first regions 1a, 2a of the wirings 1, 2 are adjacent to the second regions 2b, lb of the adjacent wirings 2, 1, respectively, The regions 1a and 2a are connected to the adjacent second regions 2b and l.
It extends toward b by a length corresponding to the difference e between the width of the first region and the width of the second region. This first area 1a,
The spread width e of 2a has the relationship shown in the following equation (3).

e=b+2cm −・” (3) The distance d between the metal wirings 1 and 2 is determined by photolithography technology and etching technology, and the distance d between the metal wirings 1 and 2 is determined by photolithography and etching techniques so that the metal wirings 1 and 2 do not short-circuit. The minimum wiring spacing is set to 60 or more.

According to such a wiring structure, the contact hole 3.4
The distance between the extended lines of the edges is clearly smaller than the distance f of the conventional wiring structure shown in equation (1). Therefore, the width g of the region required for forming the metal wirings 1 and 2 can be made smaller than the width g required for the conventional wiring structure.

FIG. 2 is a schematic plan view showing a wiring structure of a semiconductor integrated circuit device according to a second embodiment of the present invention. This embodiment is an example in which this wiring structure is applied to lead wiring of a contact portion of an ultra-fine MOS transistor. In FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted.

A pair of parallel metal wiring lines 1.2 are placed on the source 5 and drain 6 of the MOS transistor via an insulating film (not shown).
is formed. A gate 7 is arranged between the metal wirings 1 and 2, and the gate length is 0.6 to 1.2 mm.
It is 0 μm. By filling the inside of the contact hole 3 formed in the insulating film with a metal wiring material, the source 5 and the metal wiring 1 are connected, and the inside of the contact hole 4 formed in the insulating film is filled with the metal wiring material. The drain 6 and the metal wiring 2 are connected by filling the drain 6 with the metal wiring 2. Distance i between the edges of contact holes 3 and 4 and the edge of gate 7
is 0.2 to 0.4 μm.

For a MOS transistor having such a design rule, metal wirings 1 and 2 are patterned in the same shape as in the first embodiment. In other words, the first region 1a of the metal interconnect 1 in which the contact hole 3 is provided extends toward the second region 2b of the metal interconnect 2, and the first region 1a of the metal interconnect 2 in which the contact hole 4 is provided extends toward the second region 2b of the metal interconnect 2. 2 a is formed so as to extend toward the second region 1 b of the metal interconnect 1 . Therefore, the first regions 1a, 2a and the second regions 2b, lb are adjacent to each other.

The distance f between the extended lines of the edges of the contact holes 3 and 4 is
As shown in Figure 2, it is determined as f=h+2i, and by substituting the values of h and i mentioned above, f is 1.0 to 1.8.
It becomes an extremely small value of μm. However, the margin C between the edges of the metal interconnects 1 and 2 and the edges of the contact holes 3 and 4 is 0.6 to 0.8 μm, and the distance d between the metal interconnects is 0.7 to 1.0 μm. It can be made large enough. Considering that the minimum interconnect spacing do between metal interconnects that can be realized using the latest photolithography and etching technology is 0.6 μm, the value of this spacing d is much larger than the minimum interconnect spacing d. Since it is large, wirings 1 and 2 can be easily formed.

As a result of being able to make the value of f smaller than before,
Width g of the area required to form metal wirings 1 and 2
The width j of the MOS transistor according to this embodiment is reduced to about 75 to 85% as compared to the width of a conventional MOS transistor.

Therefore, the area occupied by the MOS transistor in the semiconductor integrated circuit device can be reduced, and higher integration is possible. Also, the diffusion layer capacity is about 15 to 25%.
Therefore, a MOS transistor capable of high-speed operation can be obtained.

FIG. 3 is a schematic plan view showing a wiring structure of a semiconductor integrated circuit device according to a third embodiment of the present invention. This embodiment is an example in which the present invention is applied to wiring of two MOS transistors connected in parallel. In FIG. 3, the same parts as in FIG. 1 are denoted by the same reference numerals, and their explanation will be omitted. Metal interconnections 1, 8.2 are formed in parallel on the drain or source diffusion layers 13, 10, 14 of the MOS transistor with an insulating film interposed therebetween. A gate 11.
12 are arranged. Contact holes 3, 9.4 are formed in the insulating film, respectively, and metal wirings 1, 8.
2 and diffusion layers 13, 10.14 are connected to each other by filling the contact holes 3.9.4 with metal wiring material.

Also in this example, the gate length and gate 11.12
The distance i between the contact hole 3.4.9 and the contact hole 3.4.9 is determined in the same way as in the second embodiment. The shapes of the metal wirings 1 and 2 are the same as in the first embodiment, but the metal wirings 1 and 2 are
A first region 1a and a first region 2a having a width of (a+e)
The metal wiring lines 1 and 2 are arranged so that the line connecting them and the longitudinal direction of the metal wiring lines 1 and 2 are perpendicular to each other. The metal wiring 8 is arranged between the metal wirings 1 and 2, and has a first region 8a in which a contact hole 9 is provided and a second region 8b connecting the first region 8a. . This first region 8a is formed at a position facing the second region 1b (or 2b) in the center between the contact holes 3 (or 4). The second region 8b is adjacent to the first region 1a (or 2a).

The width of the first region 8a is (2c+b). Further, the width of the second region 8b of the metal interconnect 8 adjacent to the first regions 1a, 2a of the metal interconnects 1, 2 is smaller than the width a of the second region of the metal interconnect 1.2. The spacing between the metal wiring 8 and the metal wiring 1 and the spacing between the metal wiring 8 and the metal wiring 2 are both equal, and the spacing d is larger than the minimum wiring spacing do.
By wiring in this way, the distance between the extended lines of the edge of the contact holes 3 and 9.4 is the same as the distance f between the extended lines of the edge of the contact holes 3 and 4 in the second embodiment. Therefore, in this embodiment as well, the second
The same effects as in the embodiment can be obtained.

4 and 5 are schematic plan views showing a wiring structure of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

This embodiment is an example in which the present invention is applied to a multilayer wiring structure having an upper layer metal wiring, a lower layer metal wiring, and an insulating film between the eyebrows formed between both wiring layers.

In the example shown in FIG. 4, the metal wiring 2 formed in the upper layer
1.22 is formed to have the same structure and arrangement as the metal wiring 1.2 shown in the first embodiment.

The metal wirings 23 and 24 formed in the lower layer have a structure similar to that of conventional metal wirings, and have a constant width over the entire length. The metal wirings 21 and 24 are connected to each other by through-hole contacts 19 formed in the insulating film, and the metal wirings 22
．． 23 are connected to each other by through-hole contacts 20 formed in the insulating layer. By wiring in this way, the width g1 of the formation area required for the upper layer metal wiring 21, 22 can be reduced by about 15 to 25% compared to the case of the conventional multilayer wiring structure shown in FIG. This makes it easy to achieve high integration.

FIG. 5 shows the lower two metal wiring lines 23 in FIG. 4.
．． This is an example in which the wiring structure of the present invention is applied to 24, and the width g2 of the formation region of the lower metal wiring 23 and 24 is
It can be reduced by about 15 to 25% compared to the conventional multilayer wiring structure shown in the figure, and similarly, high integration becomes easy.

[Effects of the Invention] As explained above, according to the present invention, adjacent wirings are formed such that the first region and the second region are adjacent to each other, and the width of the second region is equal to the width of the first region. Since the width is narrower than the width of the area, even if there is a spacing greater than the minimum spacing between wires,
Since the arrangement pitch of the metal wiring can be reduced and the width of the area required to form the wiring structure can be reduced, it becomes easy to increase the degree of integration of the semiconductor integrated circuit device.

Furthermore, if the present invention is applied to the source and drain lead wiring of a MOS transistor, the area of the source and train diffusion layers can be reduced, MOS parasitic capacitance is reduced, and a MOS transistor capable of high-speed operation can be obtained. Can be done.

[Brief explanation of the drawing]

1 to 3 are schematic plan views showing wiring structures of semiconductor integrated circuit devices according to first to third embodiments of the present invention, and FIGS. 4 and 5 are schematic plan views showing wiring structures of semiconductor integrated circuit devices according to first to third embodiments of the present invention. Sixth schematic plan view showing the wiring structure of the semiconductor integrated circuit device according to the embodiment
8 are electrical plan views showing the wiring structure of a conventional semiconductor integrated circuit device. 1. 2,8.15-18.21-24; Metal wiring, l
a, 2a, 8a; first region, lb, 2b.

Claims (1)

[Claims] A parallel wiring having a first region in which a contact portion is disposed and a second region narrower than the first region and connecting the first regions, and 1. A wiring structure for a semiconductor integrated circuit device, wherein the region is arranged adjacent to a second region of an adjacent wiring at a predetermined interval.