JPH01120852A - Plastic chip carrier - Google Patents
Plastic chip carrierInfo
- Publication number
- JPH01120852A JPH01120852A JP62278877A JP27887787A JPH01120852A JP H01120852 A JPH01120852 A JP H01120852A JP 62278877 A JP62278877 A JP 62278877A JP 27887787 A JP27887787 A JP 27887787A JP H01120852 A JPH01120852 A JP H01120852A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- plating
- package
- substrate
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004033 plastic Substances 0.000 title claims abstract description 11
- 229920003023 plastic Polymers 0.000 title claims abstract description 11
- 229910000679 solder Inorganic materials 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 abstract description 19
- 238000007747 plating Methods 0.000 abstract description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052802 copper Inorganic materials 0.000 abstract description 8
- 239000010949 copper Substances 0.000 abstract description 8
- 230000008569 process Effects 0.000 abstract description 8
- 238000005476 soldering Methods 0.000 abstract description 7
- 238000007639 printing Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005219 brazing Methods 0.000 abstract 1
- 229920000954 Polyglycolide Polymers 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 235000010409 propane-1,2-diol alginate Nutrition 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3468—Applying molten solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、入出力端子数が多いプラスチックチップキャ
リアに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a plastic chip carrier having a large number of input/output terminals.
−（従来の技術） 近年ＬＳＩの集積度の向上と、カスタム。- (Conventional technology) In recent years, the degree of integration of LSI has improved and customization has increased.
およびセミカスタムＬＳＩの普及に伴う、入出力ピンの
増加は著しい。この様な人出ピンの増加に対して、セラ
ミンクのＰＧＡやチップ・キャリヤが急速に採用され始
めた。しかし、セラミック・パッケージでは、チップ・
コストよりもパッケージ・コストの方が高価になること
がある。With the spread of semi-custom LSIs, the number of input/output pins has increased significantly. In response to this increase in demand, ceramic PGAs and chip carriers began to be rapidly adopted. However, in ceramic packages, the chip
Package costs can be more expensive than costs.
これに対して、プリント配線基板をベースにしたプラス
チックＰＧＡ （第２図）とＬＣＣ（第３図）のコトス
は、セラミックと同じピン密度であっても、ＰＧＡで１
７２〜１／３゜ＬＣＣでは１／３〜１１５で作ることが
できる。On the other hand, plastic PGA (Fig. 2) and LCC (Fig. 3), which are based on printed wiring boards, have the same pin density as ceramics, but the PGA is
72-1/3° LCC can produce 1/3-115°.
ところが、実際後述する様な理由で、量産性が上がらず
、前記の様な低価格品が市場に出まわるには、至ってい
ない。However, for reasons that will be described later, mass production has not improved, and low-priced products such as those mentioned above have not yet appeared on the market.
すなわち、ＰＧＡにおいては、ｉ）ピンとスルーホール
は、はめ合わせの高い精度が必要。That is, in PGA, i) pins and through holes require high precision fitting;
ｉｉ）ピン価格が生産コストの１７２〜１／３を占める
＊ １ｉｉ）ピン立て工程の量産化技術がない。ii) The pin price accounts for 172 to 1/3 of the production cost.* 1ii) There is no mass production technology for the pin setting process.
ＬＣＣにおいては、ｉ）側面電極部分のスルーホールを
金型で縦に切断するため、めっきの厚さが切断の成否に
大きく影響する。ｉｉ）品種の変動が多い実装ラインで
は、チップの搭載からりフローはんだ付けまでの表面実
装技術が確立されていない。In LCC, i) through-holes in side electrode portions are vertically cut using a mold, so the thickness of the plating greatly influences the success or failure of cutting. ii) Surface mounting technology from chip mounting to flow soldering has not been established in mounting lines where product types often change.
１ｔｉ）基板端面のみに入出力端子を設けるため、端子
数を多くするためには、５０ミルから。1ti) Since input/output terminals are provided only on the end face of the board, in order to increase the number of terminals, start from 50 mil.
２０ミルピンチにしなければならない。Must be in a 20 mil pinch.
等の問題点がある。しかし、上記問題点等が解決出来れ
ば、プラスチックパッケージの利用である。１）加工性
、２）電気的特性、３）１ａ械的衝撃性にすぐれ、しか
もセラミックに比べ格段の４）量産性が得られることに
なる。There are other problems. However, if the above problems can be solved, plastic packages can be used. It has excellent 1) workability, 2) electrical properties, 3) 1a mechanical impact resistance, and 4) mass productivity, which is much better than ceramics.
（発明が解決しようとする問題点）
ＬＳＩパッケージを占有面積のわりに、多端子化するた
めに、現在量も有利な、パッケージ形態はＰＧＡとＬＣ
Ｃである。この両形態のパンケージ材質をセラミックか
ら、ガラス−エポキシ等に変えることにより、パッケー
ジコストの大巾な低減が予想された。しかるに、このプ
リント配線基板をベースにしたパフケージコストは、現
在の所予想に反して。(Problem to be solved by the invention) In order to reduce the area occupied by LSI packages and increase the number of terminals, the current package formats, which are advantageous in quantity, are PGA and LC.
It is C. By changing the material of the pan cage for both types from ceramic to glass-epoxy or the like, it was expected that the packaging cost would be significantly reduced. However, the puff cage cost based on this printed wiring board is currently contrary to expectations.
そればどのコスト低減効果をもたらしてはいない。その
理由の一つに、プリント基板にはない、製造工程の複雑
さがある。すなわち。It does not bring any cost reduction effect. One of the reasons for this is the complexity of the manufacturing process, which printed circuit boards do not have. Namely.
ＰＧＡにおいては、 １）ピンとスルーホールは。In PGA, 1) Pins and through holes.
はめ合わせの高い精度が必要なため、めっき厚の管理が
むずかしいこと＊ｉｉ）ピン価格が生産コストの１ノ２
〜１／３を占めて、けっして安価ではないこと。１ｉｉ
）小さなピンを整列させて、プリント基板に立てる量産
技術がないこと、などである、それでは、ＬＣＣ形態の
パフケージにすればと考えられるが、ＬＣＣにおいても
、ｉ）側面電極部分を、スルーホールを金型で縦に切断
するため、めっきの厚さが切断の成否に大きく影響する
ため、めっき厚の管理がむずかしいこと。ｉｉ）プリン
ト板へのチップ搭載からりフローはんだ付けまでの表面
実装技術が確立されていないこと、１ｉｉ）基板端面に
のみ入出力端子を設けるため。Controlling plating thickness is difficult as high precision fitting is required. *ii) Pin price is the number one factor in production cost.
It occupies ~1/3 and is not cheap at all. 1ii
) There is no mass production technology to align small pins and mount them on a printed circuit board.In that case, it would be possible to make an LCC-type puff cage, but in LCC as well, i) side electrode parts and through holes are not available. Since cutting is performed vertically using a mold, the thickness of the plating has a large effect on the success or failure of the cut, making it difficult to control the thickness of the plating. ii) The surface mounting technology from mounting the chip on the printed board to flow soldering has not been established; 1ii) Input/output terminals are provided only on the end face of the board.
端子数を多くするためには、５０ミルから、２０ミルピ
ンチと端子ピッチを落す必要があり。In order to increase the number of terminals, it is necessary to reduce the terminal pitch from 50 mil to 20 mil pinch.
微細回路形成技術と直径０．２５ａ＋ｍ以下の小径穴あ
け技術等の確立が必要となる。It is necessary to establish fine circuit forming technology and small diameter hole drilling technology of 0.25a+m or less in diameter.
本発明は、前記問題点を１回避し、かつ。The present invention avoids one of the above problems, and.
ＰＧＡ、ＬＣＣの両方の１１点のみをそなえ持つ、プラ
スチックチップキャリアを安価に製造する方法を堤供す
るものである。The present invention provides a method for manufacturing a plastic chip carrier at low cost, which has only 11 components for both PGA and LCC.
（問題点を解決するための手段） 第１図により説明する。(Means for solving problems) This will be explained with reference to FIG.
ガラス・エポキシ、ポリイミド等のパネル状プリント配
線板材料に、複数行列の格子状（例えば１００〜５０ミ
ルピツチ）に、ドリル加工等で０．３１〜０．６１望ま
しくは、０．５ｍｍのスルーホールを形成する（第１図
（ａ））。この基板を、無電解銅めっき、電気銅めっき
システムにより、１５〜３５μｍ厚のスルーホール銅め
っきを形成する（第１図りｈ））。プリント板の回路形
成に使用される。サブトラクト法を用い８回路形成を行
う（第１図（ｃ） 、 （ｄ））。ソルダーレジストを
印刷法あるいは、焼付法等により、基板両面に形成する
。その後必要箇所に、ワイヤーボンディング用の、高純
度Ｎｉ−Ａｕめっきを行う。（第１図（ｅ））。次にス
ルーホールに対して、デイツプ法、ウェーブ法、リフロ
ー法等の方法により、はんだ上げを行う。このはんだ上
げにより、パッケージとしての気密封止が出来ると共に
、基板裏面に対し、入出力端子が形成されたことになる
（第１図（ｆ））。この杖態では、バッドバンプとして
は、きわめて、バンプ高さが低いものであるため、さら
に、ペーストはんだの、メタルマスク印刷法等の方法に
より、パッドハンプ上に、３０〜５０μｍ程度のはんだ
厚付けを行う（第１図（ｇ））。この後製品外形加工を
行ない、、ＬＳＩチップを搭載しく第１図（ｈ））。Drill through holes of 0.31 to 0.61 mm, preferably 0.5 mm, in a panel-shaped printed wiring board material such as glass, epoxy, or polyimide in a grid pattern of multiple rows and columns (for example, 100 to 50 mil pitch). (Fig. 1(a)). Through-hole copper plating with a thickness of 15 to 35 μm is formed on this substrate by electroless copper plating or electrolytic copper plating system (first drawing h)). Used to form circuits on printed boards. Eight circuits are formed using the subtract method (FIGS. 1(c) and (d)). Solder resists are formed on both sides of the substrate by a printing method, a baking method, or the like. Thereafter, high-purity Ni-Au plating for wire bonding is applied to the necessary locations. (Figure 1(e)). Next, solder is applied to the through holes using a dip method, a wave method, a reflow method, or the like. By this soldering, the package can be hermetically sealed, and input/output terminals are formed on the back surface of the board (FIG. 1(f)). In this case, the height of the bump is extremely low for a bad bump, so a solder thickness of about 30 to 50 μm is applied to the pad hump using a method such as paste solder or metal mask printing. (Figure 1 (g)). After this, the external shape of the product is processed and the LSI chip is mounted (Figure 1 (h)).
ワイヤーボンティング（第１図（ｉ）） 、 １０）パ
ッケージ封止をして（第１図（ｊ））、ＬＳＩパッケー
ジを完成する。Wire bonding (FIG. 1(i)) and 10) package sealing (FIG. 1(j)) are performed to complete the LSI package.
（作用） 本発明によるプラスチックパッケージは。(effect) A plastic package according to the invention.
パッケージ底面より、接続端子を格子状に取れるため、
同一パフケージ面積のＬＣＣに比べ端子数が多く取れる
。（ＬＣＣ１２０〜２０８ピンに対し、２０８〜３００
ビン程度）またマザ−ボードに表面実装回路を形成する
必要がなく、ＤＩＰ、ＰＧＡと同様に、マザーボードの
スルーホールパッド上に直接搭載可能であり、その後の
はんだ上げで、セルフアライメントの良い接続が出来る
。さらに、マザーボードと同一材質のため、熱応力によ
る。はんだ接合部の破壊も、きわめて少ないものとなる
。Since the connection terminals can be removed in a grid pattern from the bottom of the package,
The number of terminals can be increased compared to LCC with the same puff cage area. (For LCC120-208 pins, 208-300
In addition, there is no need to form a surface mount circuit on the motherboard, and it can be mounted directly on the through-hole pad of the motherboard, similar to DIP and PGA, and the subsequent soldering allows for connections with good self-alignment. I can do it. Furthermore, since it is made of the same material as the motherboard, it is caused by thermal stress. Breakage of solder joints is also extremely reduced.
実施例
１）プリント配線板材料であるＭＣＬ−Ｅ−６７（日立
化成工業Ｈ製品名）両面銅張り積層板に、格子状（例え
ば１００ミルピンチ）に。Example 1) A printed wiring board material MCL-E-67 (Hitachi Chemical H product name) double-sided copper-clad laminate was coated in a lattice shape (for example, 100 mil pinch).
ＮＣドリルマシーンで穴あけを行う、２）この穴あけを
行なった基板に、無電解銅めっき。Drill a hole using an NC drill machine. 2) Electroless copper plating is applied to the board on which this hole has been drilled.
電気銅めっきを行ない、スルーホール銅めっきを形成す
る。３）シかる後、感光性レジストを露光１現像させ、
所望の回路像を形成する。Perform electrolytic copper plating to form through-hole copper plating. 3) After printing, the photosensitive resist is exposed and developed,
Form a desired circuit image.
この回路には、大きくわけて、ランド部ボンディングリ
ード部、ランド部とリード部を結ぶ配線部からなってい
る。４）このレジスト像のままに、塩化第二銅等のエツ
チング液で。This circuit mainly consists of a land portion, a bonding lead portion, and a wiring portion connecting the land portion and the lead portion. 4) Leave this resist image as is and use an etching solution such as cupric chloride.
スプレーエツチングを行ない２回路形成する。Perform spray etching to form two circuits.
５）次に、ソルダーレジストＣＣＲ−５０６Ｇ（アサヒ
化学研究所製品名）や、ＰＳＲ−１０００（太陽インキ
製品名）等を、スクリーン印刷法、焼付法等の方法にら
り、永久レジスト膜として形成する。5) Next, solder resist CCR-506G (Asahi Chemical Research Institute product name), PSR-1000 (Taiyo Ink product name), etc. is formed as a permanent resist film using methods such as screen printing and baking. do.
尚、前記レジストを選択した理由は、はんだ耐熱性の良
さ、絶縁特性（８５℃、８５％ＲＨ１００Ｖ、 １００
０Ｈｒ）の良さからなどである。６）さらに、ワイヤー
ボンディングに必要な、ニッケル、金めつき（テンペレ
ジストマＴ）（日本高純度化学■製品名）を、ボンディ
ングリード部に行なう、この後、ＰＧＡの製造工程にお
いては、ビン立てを行なうのであるが９本発明によれば
、６）スルーホールに対して、はんだ上げを行なう、具
体的には、アルファメタルＲ５００３（田中貴金属側製
品名）等のフラックスを添布し、ウェーブ法により２３
０℃３０秒程度ではんだ（Ｓｎ ： Ｐｂ＝６ ： ４
）上げを行なう。本工程で、金スルーホールにはんだ上
げを行ない、気密針止が出来ると共に。The above resist was selected because of its good soldering heat resistance and insulation properties (85°C, 85%RH 100V, 100%
This is because of its good performance (0Hr). 6) Furthermore, nickel and gold plating (Tempelestomer T) (product name of Nippon Kojundo Chemical Co., Ltd.) necessary for wire bonding is applied to the bonding lead part. However, according to the present invention, 6) Soldering is performed on the through hole. Specifically, a flux such as Alphametal R5003 (product name of Tanaka Kikinzoku side) is applied and a wave method is applied. by 23
Solder at 0°C for about 30 seconds (Sn:Pb=6:4
). In this process, the gold through-holes are soldered to create an airtight needle stop.
基板裏面に１人出力端子が形成される。７）さらに、こ
のままでは、はんだバンプの高さが低いため、ペースト
はんだを、メタルマスク印刷法により、 ３０〜５０μ
ｍ程度の厚さで、はんだ上げを行なったランド上に印刷
する。その後、金型による打ち抜きにより、パネル状で
あった製品を１個別に分離し、洗浄を行ない、パフケー
ジを完成する。A single output terminal is formed on the back side of the board. 7) Furthermore, since the height of the solder bump is low as it is, the paste solder is coated with a thickness of 30 to 50μ using the metal mask printing method.
It is printed on the soldered land to a thickness of approximately 1.5 m. Thereafter, the panel-shaped product is separated into individual pieces by punching with a die, and the puff cage is completed by cleaning.
（発明の効果）
本発明によれば、セラミックパッケージに比べ、１）加
工性＋２）？ｉｌ気的特性、３）機械的衝撃性にすぐれ
、かつ、４）熱応力による接点の破断の少ない、多端子
プラスチックパッケージを得ることが出来ると同時に、
ＰＣ；Ａ、 ＬＣＣの両方の利点をかねそなえた
。５１産性の高い多端子プラスチックパッケージとなる
。(Effects of the Invention) According to the present invention, compared to a ceramic package, 1) workability +2)? At the same time, it is possible to obtain a multi-terminal plastic package that has excellent electrical properties, 3) mechanical impact resistance, and 4) less rupture of contacts due to thermal stress.
It has the advantages of both PC; A and LCC. This results in a multi-terminal plastic package with high productivity.
第１図（ａ）〜（ｊ）は本発明のプラスチックチップキ
ャリアを製造する工程を説明する断面図、第２図、第３
図は従来例の斜視図である。
符号の説明
１ 銅 箔
２基材
３ エツチングレジスト
４ ソルダーレジスト
５ ニッケルめっき
６ 金めっき
７ はんだ
８ はんだバンプ
ＬＳｌ
１０ ワイヤー
（ａ）
８ （ｃ）
↓ （ｄ）
：、 （ｅ）
第゛
第２図
” （ｆ）
Ａ （＋）
（ｊ）
１図
第３図FIGS. 1(a) to (j) are cross-sectional views explaining the process of manufacturing the plastic chip carrier of the present invention, FIGS. 2 and 3.
The figure is a perspective view of a conventional example. Explanation of symbols 1 Copper Foil 2 Base material 3 Etching resist 4 Solder resist 5 Nickel plating 6 Gold plating 7 Solder 8 Solder bump LSL 10 Wire (a) 8 (c) ↓ (d) :, (e) Fig. 2 ” (f) A (+) (j) Figure 1 Figure 3
Claims (1)
を行ない、はんだバンプを形成し、このはんだバンプを
接点とするプラスチックチップキャリア。[Claims] 1. A plastic chip carrier in which a plurality of rows and rows of through holes formed from the front surface to the back surface of a package base are soldered to form solder bumps, and the solder bumps are used as contacts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62278877A JPH01120852A (en) | 1987-11-04 | 1987-11-04 | Plastic chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62278877A JPH01120852A (en) | 1987-11-04 | 1987-11-04 | Plastic chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01120852A true JPH01120852A (en) | 1989-05-12 |
Family
ID=17603361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62278877A Pending JPH01120852A (en) | 1987-11-04 | 1987-11-04 | Plastic chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01120852A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994025984A1 (en) * | 1993-04-23 | 1994-11-10 | Nihon Micron Kabushiki Kaisha | Ic package and method of its manufacture |
| EP0941021A1 (en) * | 1998-03-06 | 1999-09-08 | Easy Hole International, Ltd. | Manufacturing process for printed-circuit boards with electrical connection between faces |
| CN103153001A (en) * | 2013-02-05 | 2013-06-12 | 浙江宇视科技有限公司 | Printed circuit board (PCB) and processing method |
-
1987
- 1987-11-04 JP JP62278877A patent/JPH01120852A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994025984A1 (en) * | 1993-04-23 | 1994-11-10 | Nihon Micron Kabushiki Kaisha | Ic package and method of its manufacture |
| EP0941021A1 (en) * | 1998-03-06 | 1999-09-08 | Easy Hole International, Ltd. | Manufacturing process for printed-circuit boards with electrical connection between faces |
| CN103153001A (en) * | 2013-02-05 | 2013-06-12 | 浙江宇视科技有限公司 | Printed circuit board (PCB) and processing method |
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