JPH01120848A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01120848A JPH01120848A JP62279653A JP27965387A JPH01120848A JP H01120848 A JPH01120848 A JP H01120848A JP 62279653 A JP62279653 A JP 62279653A JP 27965387 A JP27965387 A JP 27965387A JP H01120848 A JPH01120848 A JP H01120848A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- metal film
- metallic film
- etching
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000005530 etching Methods 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims description 56
- 239000002184 metal Substances 0.000 claims description 56
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 13
- 229910052737 gold Inorganic materials 0.000 description 13
- 239000010931 gold Substances 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 208000025174 PANDAS Diseases 0.000 description 2
- 208000021155 Paediatric autoimmune neuropsychiatric disorders associated with streptococcal infection Diseases 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 240000004718 Panda Species 0.000 description 2
- 235000016496 Panda oleosa Nutrition 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に於ゆるバンプ電極構造と、その
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bump electrode structure in a semiconductor device and a manufacturing method thereof.
従来の半導体装置に於ける一般的なバンプ電極の製造方
法は、バンプ電極形成後バンプ電極下金属層を連続して
゛ウェットエツチング、すなわち前述の第３の金属膜を
ウェットエツチング後、第２の金属膜をウェットエツチ
ングし、更に第１の金属膜をウェットエツチングしてい
た。A common method for manufacturing bump electrodes in conventional semiconductor devices is to continuously wet-etch the metal layer under the bump electrode after forming the bump electrode. The film was wet-etched, and the first metal film was further wet-etched.
〔発明が解決しようとする問題点〕 。[Problem that the invention seeks to solve].
この様に従来の技術に於ては複層膜を連続してウェット
エツチングしている為、本エツチング工程に於けるサイ
ドエッチにより、第３及び第２の金属膜周辺部が下部金
属膜に接しない浮いた部分ができ、これが後工程に於【
針状に欠落して電極間ショートをもたらすといった内容
の問題があった。In this way, in the conventional technology, the multilayer film is continuously wet-etched, so the side etching in the main etching process causes the peripheral parts of the third and second metal films to come into contact with the lower metal film. There will be floating parts that will not be removed.
There was a problem in that the electrodes were missing in the form of needles, causing short circuits between the electrodes.
本発明はこの様な問題点を解決するもので、その目的と
するところは前述の第３．第２．第１の金８４膜層を連
続エツチングした後、感光性樹脂を第３の金に謹上に残
した状態で、第２の金属膜を再エツチングし、更に第３
の金ＩＭＭを再エツチングすることで問題となっている
第３．第２の金属膜周辺部の浮いた部分を無くし、大幅
な品質向上を提供することにある。The present invention is intended to solve these problems, and its purpose is to solve the above-mentioned third problem. Second. After continuously etching the first gold 84 film layer, the second metal film is re-etched with the photosensitive resin carefully left on the third gold film, and then the third gold film is etched.
The third problem caused by re-etching the gold IMM. The object of the present invention is to eliminate floating parts around the second metal film and to provide a significant improvement in quality.
本発明の半導体装置及びその製造方法は、（１） 半
導体基板上の第１の絶縁膜と該第１０絶縁膜上のアルミ
ニウム電極と、該第１の絶縁膜上より該アルミニウム電
極の上面周辺部上に延在して設けられた第２の絶縁膜と
、該アルミニウム電極上面中央部より該第２の絶縁膜上
に延在して設けられた第１の金属膜と、該第１の金ａ４
膜上且つ該°第１の金＃４膜領域の内側上面に設けられ
た第２の金属膜と該第２の金属膜上且つ該第２の金属膜
領域の内側上面に設けられた第３の金ｌｊ！膜と該第３
の金属膜上に設けられたバンプ電極層とを有することを
特徴とする。The semiconductor device and the manufacturing method thereof of the present invention include (1) a first insulating film on a semiconductor substrate, an aluminum electrode on the tenth insulating film, and a peripheral portion of the upper surface of the aluminum electrode from above the first insulating film. a second insulating film extending above the aluminum electrode; a first metal film extending from the center of the upper surface of the aluminum electrode onto the second insulating film; a4
A second metal film provided on the film and on the inner upper surface of the first gold #4 film region; and a third metal film provided on the second metal film and on the inner upper surface of the second metal film region. Money lj! membrane and the third
A bump electrode layer is provided on the metal film.
（２） 半導体電極上に第１．第２．第３の金属膜を
順に形成させ、該第３の金属膜上にバンプを極を形成後
、該バンク電極上より、該第３の金属膜上に延在し、島
状に感光性樹脂を付着させる工程と、該第３の金属をエ
ツチングする工程と、該第２の金属をエツチングする工
程と該第１の金属をエツチングする工程と、該第２の金
属を再エツチングする工程と、該第１の金属を再エツチ
ングする工程と、該感光性樹脂を除去する工程とを含む
ことを特徴とする。(2) First layer on the semiconductor electrode. Second. After forming a third metal film in order and forming bumps on the third metal film, a photosensitive resin is formed in an island shape extending from above the bank electrode onto the third metal film. a step of depositing, a step of etching the third metal, a step of etching the second metal, a step of etching the first metal, a step of re-etching the second metal; The method is characterized by including a step of re-etching the first metal and a step of removing the photosensitive resin.
以下１０本発明について実施例に基づき詳細に説明する
。Hereinafter, ten of the present invention will be explained in detail based on examples.
第１図は、本発明の半導体装置であるバンプ電極構造の
一実施例を示す。図に示す様に本発明はバンプ［種下の
金属展層の構造に於て、第３の金属膜３を第２の金属膜
領域の内側上部に設け、更に第２の金Ｆｊ４Ｍ２を第１
の金属膜領域の内側上部に設けることを特徴とする。FIG. 1 shows an embodiment of a bump electrode structure which is a semiconductor device of the present invention. As shown in the figure, in the structure of the metal spreading layer under the bump [seed], the third metal film 3 is provided on the inner upper part of the second metal film region, and the second gold Fj4M2 is further placed on the first metal layer.
It is characterized by being provided on the inner upper part of the metal film region.
第２図は、本発明の半導体装置の製造工程に於げる、バ
ンプ下金属膜層な連続エツチングした後の断面構造を示
す。FIG. 2 shows a cross-sectional structure after continuous etching of the metal film layer under the bump in the manufacturing process of the semiconductor device of the present invention.
第３図は、第２図に於て金属膜層をエツチング後、第２
の金属膜２を再エツチングした後の断面構造を示す。FIG. 3 shows the second etching after etching the metal film layer in FIG.
The cross-sectional structure of the metal film 2 after being re-etched is shown.
第４図は、第５図に於て第２の金属膜のエツチング後、
第３の金属膜をエツチングした後の断面構造を示す。FIG. 4 shows the steps in FIG. 5 after etching the second metal film.
The cross-sectional structure after etching the third metal film is shown.
第５図は、第３の金属膜エツチング後、金ｍｍ層の選択
エツチングの為に設けた感光性樹脂を除去した後の最終
バンプ電極の断面構造を示す。FIG. 5 shows the cross-sectional structure of the final bump electrode after the third metal film etching and the removal of the photosensitive resin provided for selective etching of the gold mm layer.
第６図は、従来のバンプ電極の構造を示゛す。本構造は
、本発明の製造工程である第２図に示す工巴後、感光性
樹脂を除去した場合の構造と一致する。FIG. 6 shows the structure of a conventional bump electrode. This structure corresponds to the structure when the photosensitive resin is removed after the manufacturing process shown in FIG. 2, which is the manufacturing process of the present invention.
上述の如く、本発８１１によればバンプ下金ｔ１層に於
て、第２及び第３の金属膜を各々下部金ｒＡ膜領域の上
部、且つ内側に後退して設けることにより、従来の構造
に於る、第２及び第５の金属膜が下部金属膜領域の外ｆ
ｌＩｌｌ？：出た構造をとることによる問題点、すなわ
ち第２及び第３の金属膜周辺部の下部金属膜に接しない
浮いた部分が後工程で針状に欠落して電極間シ茸−トを
もたらすといった内容の問題を完全く解消することがで
き、パンダ電極品質の大幅な向上をもたらすものである
。As described above, according to the present invention 811, in the bump lower gold t1 layer, the second and third metal films are provided above the lower gold rA film region and retreated inside, thereby improving the conventional structure. The second and fifth metal films are located outside the lower metal film region.
Illll? : Problems caused by adopting the exposed structure, namely, the floating parts around the second and third metal films that do not contact the lower metal film are broken off in the form of needles in the subsequent process, resulting in a seat between the electrodes. These problems can be completely resolved, and the quality of panda electrodes can be greatly improved.
第１図は本発明の半導体装置であるバンプ１極断面図。
第２図は、本発明の半導体装置の製造工＆に於【、バン
プ電極金属膜層のエツチング後の状態を示すバンプ′Ｉ
ｔ極断面図。
第３図は、本発明の半導体装置の製造工１ｆｆｌＫ於て
、第２の金ｇ４Ｆ！４のエツチング後の状態を示すバン
プ電極断面図。
第４図は、本発明の半導体装置の製造工程に於て、第３
°の金ｍｗＩのエツチング後の状態を示すバンプ電極断
面図。
第５図は、本発明の半導体装置の最終パンダ電極断面図
。
第６図は、従来のバンプ電極断面図。
１・・・・・・チタン、り四ム、アルミニウム等の第１
の金Ｈ４膜
２・・・・・・銅、パラジウム、ニッケル等の第２の金
属膜
３・・・・・・金、白金等の第３の金属膜４・・・・・
・バンプ電極層
５・・・・・・アルミニウム＃ｌＬ極
６．７・・・・・・Ｓｉｎ、、ＳｉＮ 系絶縁膜８
・・・・・・感光性樹脂
以上
出願人 セイコーエプソン株式会社
代理人 弁理士最上筋（他１名）
〆−
（１１・１．ニー、・
′、〜己−・FIG. 1 is a sectional view of one pole of a bump which is a semiconductor device of the present invention. FIG. 2 shows the state of the bump 'I' after etching the bump electrode metal film layer during the manufacturing process of the semiconductor device of the present invention.
t-pole cross-sectional view. FIG. 3 shows a second gold g4F! 4 is a cross-sectional view of the bump electrode showing the state after etching. FIG. 4 shows the third step in the manufacturing process of the semiconductor device of the present invention.
FIG. 3 is a cross-sectional view of the bump electrode showing the state after etching of gold mwI. FIG. 5 is a sectional view of the final panda electrode of the semiconductor device of the present invention. FIG. 6 is a sectional view of a conventional bump electrode. 1...First of titanium, aluminum, aluminum, etc.
Gold H4 film 2... Second metal film 3 of copper, palladium, nickel, etc. Third metal film 4 of gold, platinum, etc.
- Bump electrode layer 5...Aluminum #lL pole 6.7...Sin, SiN-based insulating film 8
...Applicant for photosensitive resins and above Seiko Epson Co., Ltd. Representative Patent attorney Mogamisuji (1 other person) 〆- (11.1. Knee,・', ~Self-・
Claims (2)
のアルミニウム電極と、該第１の絶縁膜上より該アルミ
ニウム電極の上面周辺部上に延在して設けられた第２の
絶縁膜と、該アルミニウム電極上面中央部より該第２の
絶縁膜上に延在して設けられた第１の金属膜と、該第１
の金属膜上且つ該第１の金属膜領域の内側上面に設けら
れた第２の金属膜と該第２の金属膜上且つ該第２の金属
膜領域の内側上面に設けられた第３の金属膜と該第３の
金属膜上に設けられたバンプ電極層とを有することを特
徴とする半導体装置。(1) a first insulating film on a semiconductor substrate; an aluminum electrode on the first insulating film; a second insulating film, a first metal film extending from the center of the upper surface of the aluminum electrode onto the second insulating film;
a second metal film provided on the metal film and on the upper inner surface of the first metal film region; and a third metal film provided on the second metal film and on the inner upper surface of the second metal film region. A semiconductor device comprising a metal film and a bump electrode layer provided on the third metal film.
に形成させ、該第３の金属膜上にハング電極を形成後、
該バンプ電極上より、該第３の金属膜上に延在し島状に
感光性樹脂を付着させる工程と、該第３の金属をエッチ
ングする工程と、該第２の金属をエッチングする工程と
該第１の金属をエッチングする工程と、該第２の金属を
再エッチングする工程と、該第１の金属を再エッチング
する工程と、該感光性樹脂を除去する工程とを含むこと
を特徴とする半導体装置の製造方法。(2) After sequentially forming first, second, and fifth metal films on the semiconductor electrode and forming a hang electrode on the third metal film,
a step of attaching a photosensitive resin in an island shape extending from the bump electrode onto the third metal film; a step of etching the third metal; and a step of etching the second metal. The method includes the steps of etching the first metal, re-etching the second metal, re-etching the first metal, and removing the photosensitive resin. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62279653A JPH01120848A (en) | 1987-11-05 | 1987-11-05 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62279653A JPH01120848A (en) | 1987-11-05 | 1987-11-05 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01120848A true JPH01120848A (en) | 1989-05-12 |
Family
ID=17613979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62279653A Pending JPH01120848A (en) | 1987-11-05 | 1987-11-05 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01120848A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5242861A (en) * | 1991-06-06 | 1993-09-07 | Nec Corporation | Method for manufacturing semiconductor device having a multilayer wiring structure |
| US5376584A (en) * | 1992-12-31 | 1994-12-27 | International Business Machines Corporation | Process of making pad structure for solder ball limiting metallurgy having reduced edge stress |
| JP2011249564A (en) * | 2010-05-27 | 2011-12-08 | Renesas Electronics Corp | Semiconductor device manufacturing method and mounting structure |
-
1987
- 1987-11-05 JP JP62279653A patent/JPH01120848A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5242861A (en) * | 1991-06-06 | 1993-09-07 | Nec Corporation | Method for manufacturing semiconductor device having a multilayer wiring structure |
| US5376584A (en) * | 1992-12-31 | 1994-12-27 | International Business Machines Corporation | Process of making pad structure for solder ball limiting metallurgy having reduced edge stress |
| JP2011249564A (en) * | 2010-05-27 | 2011-12-08 | Renesas Electronics Corp | Semiconductor device manufacturing method and mounting structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0778826A (en) | Preparation of chip bump | |
| TW546841B (en) | Semiconductor device and fabrication process thereof | |
| JPH0513418A (en) | Semiconductor device and manufacture thereof | |
| JPH01120848A (en) | Semiconductor device and manufacture thereof | |
| TW444253B (en) | Semiconductor device and method of producing the same | |
| JPS60136338A (en) | Semiconductor device | |
| JP3116469B2 (en) | Method of forming bump type electrode and method of manufacturing semiconductor device | |
| JP3573894B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH03198342A (en) | Manufacture of semiconductor device | |
| JPS6336548A (en) | Semiconductor device and manufacture thereof | |
| JP3119352B2 (en) | Method for forming plated structure of semiconductor device | |
| JPH05299420A (en) | Semiconductor device | |
| JPH065609A (en) | Bump forming method | |
| JPH01187949A (en) | Manufacture of semiconductor device | |
| JPS63220549A (en) | Integrated circuit device | |
| JP3038361B2 (en) | Manufacturing method of electrical connection member | |
| JPH0231844B2 (en) | HANDOTAISOCHORIIDOFUREEMUNOSEIZOHOHO | |
| JPH0350734A (en) | Manufacture of integrated circuit | |
| JPH0510365Y2 (en) | ||
| JP3032643B2 (en) | Semiconductor device mounting method | |
| TW306050B (en) | ||
| JP2600669B2 (en) | Metal bump for transfer bump | |
| JPS60113446A (en) | Bump electrode structure and formation thereof | |
| JPS62206856A (en) | Semiconductor device and manufacture thereof | |
| JPH04199631A (en) | Manufacture of integrated circuit |