JPH01119772A - Ic tester - Google Patents

Abstract

PURPOSE:To enable the simultaneous and parallel execution of a DC characteristic test of a plurality of ICs (DUTs) to be tested and thereby to shorten a time for the test, by providing a group of pins, DC characteristic measuring circuits (PMUs), a DC measuring relays, etc. CONSTITUTION:A control signal is delivered from CPU 11 to each of power supply connecting relays 9a-9d through an interface (IF) 12 and a control signal line 13, and thereby the pins out of test pins 2, which are connected to power supply pins of DUTs 4a and 4b, are connected to those of inspection power supplies 7a-7d, which correspond to said pins, through the intermediary of the relays 9a-9d. Next, a control signal is delivered from the CPU 11 to each of measuring relays 10a-10d, and thereby one pin Qa1 of a pin group 2a connected to one pin Pa1 of the CUT 4a is connected to a DC characteristic measuring circuit (PMU) 8a. One pin Qb1 of a pin group 2b connected to one pin Pa(n+1) of the DUT 4a is connected, likewise, to PMU 8b. By the PMU 8a and 8b, a DC test of the pins Pa1 and Pa(n+1) of the CUT 4a are executed simultaneously and in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC tester used for testing the characteristics and functions of LSI, and particularly to an improvement in its DC characteristic measuring mechanism.

[Conventional technology]

FIG. 4 is a block diagram showing the general configuration of a conventional IC tester.
This is a connection cable that connects to the pins of C (hereinafter referred to as DU) 4a and 4b.

Further, 5 is a function test circuit that generates a pattern for funcsi contest and performs logic judgment, and 6 is a driver/inverter circuit that converts signals between DUTs 4a and 4b and funcsi contest circuit 5.
7 is when testing 0LIT4a and 4b, these DLIT4a
, 4b is a test power source (hereinafter referred to as VPS), and 8 is a DC characteristic measuring circuit (hereinafter referred to as PMIJ) that measures the DC characteristics of DUTs 4a and 4b. And V
A power supply connection relay 9 is used between PS7 and each test pin 2, and a DC measurement relay 10 is used between PMLJ8 and each test pin 2 to perform connection and FJJ leveling.

11 is a CPU that constitutes the control unit of this IC tester 1;
12 is the above-mentioned funksi contest circuit 5, VPS7
, PMU 8 and other test units and the CPU 11, and the above-mentioned power supply connection relay 9. D
C measurement relay 10 is connected to the interface 12 by a control signal line 13 and also to the VPS 7. PMU 8 is connected to interface 12 by data signal line 14 .

The conventional IC tester 1 is configured as described above, and the DUT
Tests 4a and 4b are conducted as follows according to the procedure shown in the flow diagram of FIG.

First, from the CPU 11 to the interface 12. Control signal line 1
A control signal is sent to the power supply connection relay 9 through 3, and as a result, the power supply connection relay 9 is connected between the test pins 2 connected to the power supply pins of [) UT4a and 4b and PS7.
(step S1). Then CPLll
l to interface 12. D through the control signal line 13
A control signal is sent to the C measurement relay 10, which causes the DU
One of the test pins 2 connected to the pin of T4a
The pin and the PMU 8 are connected via the DC measurement relay 10 (step S2), and the PMU 8 performs a DC characteristic test of the DUT 4a (step S2). In the next step S4, it is checked whether the DC characteristic test performed in step S3 is for the final pin of the DUT 4a, and if it is determined that the test is not for the final pin, the execution returns to step S2, Here, PMU8 is D
It is switched and connected to another pin of UT4a. Thereafter, the execution of step S-84 is repeated until the final pin is reached. As a result, the PMU 8 is sequentially switched and connected to each pin of the DUT 4a one by one, and each time the PMU 8 is switched and connected, a DC characteristic test is performed on that pin.

When the DC characteristic test on all pins of the DUT 4a is completed, the PMU 8 is switched and connected to the 1st pin of the other DUT 4b by the DC measurement relay 10 (step S5). Each execution of pin/non-pin determination is performed on the DUT.
By repeating the same way as for 4a, DUT4b
DC characteristics are also measured over all pins.

When the DC characteristic test is completed using the above procedure, the CPU
11, all DC measurement relays 10 are turned off, PMU 8 is disconnected from test pin 2, while driver/comparator circuit 6 is connected to CPtJl.
It is connected to all test pins 2 by the control signal wJlfi from l. A test pattern signal for all test pins 2 is output from the function test circuit 5 by this desk, and after this signal is converted into an analog signal by a driver/comparator circuit 6, it is sent to each pin of the corresponding DUT 4a, 4b. In addition, the signals output from the DLITs 4a and 4b are converted into digital pattern signals by the driver/comparator circuit 6 and then input to the function test circuit 5, where the frequency contest results of the DUTs 4a and 4b are simultaneously determined. Ru. The determination data is input to the CPU 11 through the interface 12 (step S8).

Figure 6 shows the PMU in IC tester 1 shown in Figure 4.
8 is a block diagram showing a schematic configuration of another conventional example in which a plurality of PMUs 8 are provided corresponding to the number of DUTs 4a and 4b (two in this case), and connection/disconnection between one PMU 8a and each test pin 2 is The DC measurement relay 108 also allows another one
Connections and disconnections between the two PMUs 8b and each test pin 2 are configured to be performed by separate DC measurement relays 10b. The other configurations are the same as in the case of FIG. 4.

In this DC characteristic test using IC tester 1, VPS
7 is connected to the power pin of each DIJT 4a, 4b, the relay corresponding to each pin of the DUT 4a is selected from among the DC measurement relays 10a, while the DC measurement relay 10b
A relay corresponding to each pin of DUT 4b is selected from among them. Then, the DC measurement relay 10a is connected to each pin of the DUT 4a one by one, and the DC characteristic test of the DUT 4a is sequentially performed.
The measurement relay 10b is connected to each pin of the DUT 4b by switching one pin at a time, and a DC characteristic test of the DUT 4b is simultaneously performed one after another.

[Problem that the invention seeks to solve]

The conventional tC tester shown in Fig. 4 detects one PM.
Since it is necessary to sequentially connect U8 to all pins of DUT4a and 4b one pin at a time and perform a DC characteristic test,
Even when testing by assigning test pin 2 to multiple DLjTs 4a and 4b, it is necessary to repeat the pin connection procedure for one OUT as many times as there are OUTs, resulting in a problem that the test time becomes longer. .

On the other hand, in another conventional IC tester shown in FIG. 6, PM [J8a, 8b
DC applied to one DUT
Although it is possible to perform DC characteristic tests on multiple DUTs 4a and 4b in parallel during the characteristic test time, reducing the test time, each PMU 8a and 8b and each DUT 4a and 4
DC measurement relays 10a and '10b are arranged in a 7-trix pattern with respect to test pin 2 in order to connect and disconnect between pins b and 2. The problem was that it became more complicated.

This invention was made to solve these problems, and it is possible to perform DC characteristic tests on multiple DUTs at the same time. Easy to configure and less likely to malfunction.
The test program also aims to provide an easy IC tester.

[Means for solving problems]

In the IC tester according to the present invention, a plurality of test pins connected to each pin of a DUT are divided into a plurality of adjacent pin groups to form a plurality of pin groups, and the DC characteristics of the DtJT are A plurality of PMUs are provided for testing, and switching connection means is provided for sequentially switching and connecting these PMUs to pins in each corresponding pin group.

[Effect].

In the IC tester according to the present invention, a plurality of DUTs are connected to a test pin while preventing one pin group of test pins from being connected across a plurality of DUTs. Then, by sequentially switching and connecting one pin to each corresponding pin group of each PMU, DC characteristic tests of a plurality of DLJTs are simultaneously performed in parallel.

〔Example〕

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of an IC tester according to the present invention, and 1 to 6 degrees 11 to 14 are exactly the same as the above-mentioned conventional device. In this IC tester 1, the test pins 2 are divided into several adjacent pins (0 pins) to form multiple pin groups 2a to 2d (Q, 1 to Q).
,. :... bows Qd1 to Qdo), and a plurality of PMIs corresponding to these pin groups 2a to 2d, respectively.
J8a, 8b.

3c and 8d are provided. In addition, each PMU8a~
Separate DC measurement relays 10a, 10b, 10c, and 10d are provided as disconnection IA 1m connection means for connecting and disconnecting pin groups 8d and the corresponding pin groups 2a and 2d, respectively. Furthermore, a plurality of VPSs 7a, 7b, 7c, and 7d are provided corresponding to each of the pin groups 2a to 2d, and connection and disconnection between each VPS 7a to 7d and each of the corresponding pin groups 2a to 2d is separately performed. The power supply connection relays 9a, 9b, 9c, 9cjr are made.

In the IC tester 1 configured as described above, a plurality of Dt
The operation when testing JT4a and 4b is performed as follows according to the procedure shown in the flowchart in FIG. In addition,
DUT4a and 4b each have N pins P...
, P ′P , ..., PbN alo aN
'bl When conducting the test, for one DU pin 4a, N pins including all the pins in the pin group 2a of the test pin 2 and some pins in the adjacent pin group 2b are used. and pin group 2C for the other DLJT4b.
It is assumed that all the pins of the pin group 2d and some pins of the adjacent pin group 2d are combined into the same number of N pins.

First, from the CPU 1.1 to the interface 12. A control signal is sent to each power supply connection relay 9a to 9d through the control signal line 13, and thereby the test pin 2
The pins connected to the power supply pins of 4a and 4b and VPS7a~
7d corresponding to that pin are connected via power connection relays 9a to 9d (step 511).
. Next, from the CPU 11 to the interface 12. A control signal is sent to each DC measurement relay 10a to 10d through the control signal line 13, and this causes the 1st pin Qa1 of the pin group 2a connected to the 1st pin Pa1 of the DUT 4a to connect to the PMU.
8a are connected via the DC measurement relay 10a (
Step S), Similarly, pin group 2b connected to 1 pin P of DUT42a a, (.+1)
between pin 1 Qb1 and PMLI8t), and pin 1 Pbl of DUT4b through DC measurement relay iob.
1 pin QC1 and P of pin group 2C connected to
The MU8c is further connected to the 1st pin P of the DIJT4b via the DC measurement relay 10c (n+1) and the 1st pin Qd1 of the pin group 2d is connected to the PML.
J8d are connected in parallel via DCWI constant relay 10d (step 512b, 512C1S1
2d). Then, DLJT by PMU8a and 8b
Pair a1 a with pin P of 4a and pin P
(n+1) and the DCvI characteristic test for pin Pb1 and pin Pb(.+1) of DtJT4b are simultaneously performed by the PMUs 8c and 8d (step SSS).

13a'13b'13C' 13d In the next step 5sss 14a''14b・14cm 14d, it is checked whether the DC characteristic test performed in steps S13. to 513d is for the final pin corresponding to each PMU 8a to 8d. If it is determined that the test is not for the final pin, the execution returns to step S-8, where P12a 12d MtJ8a to 8d each test the next pin, that is, Q
(P), Q62(P8(.,2)),
Qo2 (Pl, 2) a2 a2 and Qd2 (Pb(n+2)) are respectively switched and connected.

The execution from step S-812d to steps S142a to S is repeated until the final pin is reached.
14d i.e. pin Q for PMtJ8a. (P,.), PM (for J8b, pin Qbk (PaN), P
For MU8c, Q an (P bn), PMt
For J8d, it is repeated until reaching Qdk(PbN).

As a result, PMU8a1. tDUT4a's pin P, 1 to pin Pan, PMU8b is DUT4a's pin Pa
From (n+1) to pin P 几N, P M tJ 8 C
j, t D U From pin Pb1 to pin Pbn of T4b, PMtJ8d is pin Pbc of DtJT4b. +1)
From pin Pb-, each pin is switched and connected to A and Germany in sequence, and each time it is switched and connected, the D for that pin is connected.
A C characteristic test is performed.

When the DC characteristic test on all pins of DUT 4a and 4b is completed, all DC measurement relays 10a to 10d are turned off by the control signal from cpui"+.
While each PMU8a to 8d is disconnected from the test pin 2, the driver/comparator circuit 6 is connected to the CPtJll.
Connected to all test pins 2 by a control signal from. This allows the DU to be
Functional tests of T4a and 4b are performed (step 515).

In the above embodiment, a plurality of VPs are provided corresponding to each pin group 2a to 2d of the test pin 2, similarly to the PMLs 18a to 8d.
Although a configuration in which S7a to 7d are provided is shown, the same functionality can be provided even if one VPS7-Q is provided as shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of PMLIs are provided so as to correspond to each pin group of test pins divided into several pins, and a switching connection means is used to connect each PMtJ and each corresponding pin group. Since the configuration is configured to switch connection to one pin, it is possible to perform DC characteristic tests of multiple DUTs in parallel, reducing test time, and the configuration of the switching connection means for switching connection between the PMU and the test pin. This has the effect of simplifying the process, reducing failures, and simplifying test programs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an IC tester according to the present invention, FIG. 2 is a flow diagram showing its operation, FIG. 3 is a block diagram showing another embodiment of the invention, and FIG. 4 is a conventional IC tester. FIG. 5 is a flow diagram showing its operation, and FIG. 6 is a block diagram showing another example of the conventional IC tester. In the figure, 2 is a test pin, 2a to 2d are pin groups, and 8
a~8d are PMLJ (DC characteristic measurement circuit), 108~
10d is a DC measurement relay (switching connection means). Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 5

Claims (1)

[Claims] (1) A plurality of test pins connected to each pin of the IC under test are divided into several adjacent pins to form multiple pin groups, and the DC of the IC under test is
A plurality of DC characteristic measuring circuits for measuring characteristics are provided, and switching connection means is further provided for sequentially switching and connecting these DC characteristic measuring circuits to corresponding pins in each pin group. IC tester.