JPH01119227U

JPH01119227U -

Info

Publication number: JPH01119227U
Application number: JP16399288U
Authority: JP
Priority date: 1988-12-20
Filing date: 1988-12-20
Publication date: 1989-08-11
Also published as: JPH0432823Y2

Description

[Brief explanation of the drawing]

第１図は２ビツトおよび４ビツトのＮＲＺデー
タを３ビツトおよび６ビツトのコードワードに符
号変換するときの対応を示す図表、第２図は本考
案に基づく符号変換回路の一実施例を示す回路図
、第３図は第２図の符号変換回路の動作説明に用
いる要部の波形を示すタイムチヤート、第４図は
一般的な１／Ｎコードワードを得る符号変換回路
の一例を示すブロツク図である。２０，４０……符号変換回路、２１……シフト
レジスタ、２７……ロード・シフト切換ゲート、
２８……シフトレジスタ、２９……ＡＮＤゲート
、３５……同期引込み回路、３６……カウント回
路、３７……プリセツト回路、３８……符号変換
論理回路、Ｄｉｎ……入力データ、Ｄｏｕｔ……
出力データ。 Fig. 1 is a chart showing the correspondence when code converting 2-bit and 4-bit NRZ data into 3-bit and 6-bit code words, and Fig. 2 is a circuit showing an embodiment of the code conversion circuit based on the present invention. Figure 3 is a time chart showing the waveforms of the main parts used to explain the operation of the code conversion circuit shown in Figure 2, and Figure 4 is a block diagram showing an example of a code conversion circuit that obtains a general 1/N code word. It is. 20, 40... code conversion circuit, 21... shift register, 27... load/shift switching gate,
28...Shift register, 29...AND gate, 35...Synchronization pull-in circuit, 36...Count circuit, 37...Preset circuit, 38...Sign conversion logic circuit, Din...Input data, Dout...
output data.

Claims

[Claims for Utility Model Registration] 1. An input register that sequentially holds input data consisting of a bit string in which a plurality of bit mode units are mixed in units of bit modes of 2 or more bits, and the input data held in the input register. a logic circuit for code conversion that performs code conversion; an output register that sequentially holds the output from the logic circuit for code conversion and sends out the held output data; A bit mode identification logic circuit that identifies a bit mode from the held input data; and an output from the code conversion logic circuit to the output register according to the bit mode identified by the bit mode identification logic circuit. 1. A code conversion circuit comprising a timing control circuit that sets a timing for holding the output data and an output timing for taking out the output data from the output register. 2 Number of bits A ₁ , A ₂ ...An(A ₁ , A ₂ ...A
Input data Din of frequency f consisting of a mixture of multiple units of n (A ₁ < A ₂ ... < An) are all integers of 2 or more) is input serially at the frequency f and then output in parallel. A ₁ →B ₁ ,A ₂ →B ₂ ...An→Bn(B ₁ ,B ₂ ...
Bn (B ₁ < B ₂ ... < Bn) is a natural number and corresponds to A ₁ < B ₁ , A ₂ < B ₂ ... An < Bn), and is composed of units of the number of bits B ₁ , B ₂ ... Bn. the code conversion logic circuit 3 that converts the code of the code word according to a predetermined code conversion rule;
8 and the code conversion output from the logic circuit 38 for code conversion, the frequency f'(f'>
f) a Bn-bit second shift register 28 forming the output register for serially outputting as output data Dout; and a synchronization pull-in circuit 35 that detects a start bit pattern included in the input data Din and pulls in the synchronization; A load/shift switching gate 27 that opens upon completion of synchronization, a count circuit 36 whose output is sent through the load/shift switching gate 27 and performs subtraction counting at a frequency f', and a count circuit 36 that performs subtraction counting at a frequency f'. The input data Din in the first shift register ₂₁ is input to preset _the initial count value for Logic circuits 29 and 37 for identifying the bit mode specifying the initial count value assigned in advance for each bit mode, and the output of the count circuit 36 is provided until the initial count value reaches zero by the subtraction count. Therefore, the second shift register 28 is set to shift mode to serially output the output data Dout, and the count circuit 36 itself is operated as a subtraction counter, and when the initial count value becomes zero by the subtraction count, the count circuit 36 The second shift register 28
is put into parallel-in mode, the code conversion output is loaded in parallel, and the logic circuits 29 and 37 for bit mode identification preset the initial count value corresponding to the newly received input data Din into the count circuit 36. Here, the synchronization pull-in circuit 35 and the count circuit 36 are connected.
A code conversion circuit according to claim 1, wherein the timing control circuit is formed by a load/shift switching gate 27 and a load/shift switching gate 27. 3. The code conversion circuit according to claim 1, wherein the bit mode identification logic circuit is also used as the code conversion logic circuit.