JPS62257243A - Pattern generating circuit - Google Patents

Abstract

PURPOSE:To generate a pattern signal subjected to high speed MB1 C code easily with a comparatively low speed and inexpensive element by applying MB1C coding to a code string in parallel input to N systems and applying serial conversion to the result. CONSTITUTION:A code string inputted synchronously in parallel with N-system A-D is selected in the unit of M+1 bits and a selection pulse is sent from the selection circuits 15-18 receiving the M+1-th bit code from a selection signal generator 20. Then the M+1-th bit code is replaced into A code being the inverson of the M-th bit code by inverters 11-14 to obtain N-system of parallel code strings (M bit 1 complementary code, MB1C code) regulated. The code is converted into a serial code string by a serial conversion circuit 19 to generate a pattern signal subjected to MB1C coding.

Description

[Detailed description of the invention] ・'Field to which the present invention belongs> The present invention relates to a pattern generation circuit.

<Prior Art> (FIGS. 5 and 6) In optical digital transmission lines, binary transmission is effective due to the characteristics of laser diodes. However, for example, if a random data signal is divided into M+1 bits, and the contents of M bits 1 to 1 are inverted, the M+1 bit will not cause any problems with timing reproduction in the transmission relay system. There is a system that replaces the contents of , and uses this as the generated signal. A signal sequence obtained based on such rules is called an M-bit 1 complementary code (abbreviated as MBIC code), and requires a code format used as a binary code for optical digital transmission lines. The present invention relates to a pattern generation circuit used for evaluating an optical digital transmission line using the above-mentioned MB1G code.

FIG. 5 is a diagram showing an example of a pattern generation circuit using such a conventional MBIC code.

In the figure, 1 is a frequency divider that outputs one pulse every time M+1 clock pulses are input. 2 is a 1-bit shift register that temporarily stores the input code each time a clock pulse is input, and outputs the stored code when the next clock pulse is input. 3 is an inverter that inverts the sign of the output from the shift register 2 and outputs the inverted signal. 4 is a switch that is switched from the 4a side to the 4b side according to the divided output from the frequency divider 1.

Next, the operation of the above circuit will be explained using the time chart of FIG. 6, taking the 581C code as an example.

First, in synchronization with the clock pulse (Fig. 6 A), code sequences a, b, c, d, e1... (Fig. 6 C)
is input to the terminal 4a of the switch 4 and the shift register 2, the code sequence 10, 5, and ,d,no,
...... (Figure 2) is output.

On the other hand, the clock pulse is divided into 1/6 by the frequency divider 1, and one frequency-divided pulse synchronized with the 6th clock pulse from time tl is output from the frequency divider 1 at 12 o'clock. ), this frequency-divided pulse connects the switch 4 from the 4a side to the 4b side for one clock pulse time.

Since the switch 4 is connected to the 4a side during the time when the frequency division pulse from the frequency divider 1 is not input (from 1+ to tl), the code sequences a, b, c, d, and e are output as they are. Ru. Then, at 12 o'clock, the switch 4 is connected to the 4b side, so the impark 3 output 100 at this time is output as a continuation, and the code sequence becomes a, b, c, d, e, 'Q. In other words, a 5810-encoded code sequence is output (see E in the figure).

At time t3, one clock pulse time has elapsed since 12:00, the switch 4 returns to the 4a side and returns to the initial 1] state (at time tl), and the same operation is repeated from tl to t3 as one cycle, and 581C encoding is performed. The pattern signal is output continuously.

Problems to be Solved by the Present Invention> The above circuit can achieve speeds of 1Iili faster, for example, 2 GHz.
) To receive the MB1C coded pattern signal output (), divider 1, shift register 2, inverter 3
Each must operate stably at high speed.

However, elements that can stably perform such naa operations are often not available, and even if they are available, they are extremely expensive.

Therefore, with the conventional circuit as described above, it is extremely difficult to obtain a high-speed MBIG-coded pattern signal output.

OBJECT OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a pattern generation circuit that uses relatively low-speed elements to generate a high-speed pattern signal output encoded in MBIC. The purpose is to provide.

An Embodiment of the Present Invention (FIGS. 1 to 3) FIG. 1 is a diagram showing a 1081C coded pattern generation circuit according to an embodiment of the present invention.

In the figure, 10 is a 1-bit shift register synchronized with a clock pulse, and 11 to 14 are inverters.

15 to 18 pass the outputs from the inverters 11 to 14 when they receive a selection pulse from a selection signal generator 20 (described later), and when they do not receive a selection pulse from the selection signal generator 20, they pass the clocks. This is a selection circuit that passes the codes input in parallel to the four input terminals A to D in parallel with the pulse.

One is a serial conversion circuit that sequentially switches the codes input in parallel from the selection circuits 15 to 18 at a constant speed (four times the speed of the clock pulse) and converts them into a serial code string.

20 is one of the selection circuits 15, 16, 17, or 18 at a predetermined timing in synchronization with the clock pulse;
This is a selection signal generator that outputs selection pulses. 10
A specific implementation example of the selection signal generator 20 for generating the 81G code is shown in FIG.

In the figure, numerals 21 to 30 are 1-bit shift registers synchronized with clock pulses, which are connected in series in 10 stages. 31 is a 10-manpower NOR gate having all the outputs of shift registers 21 to 30 as inputs. Further, the outputs of the NOR groups 1 to 31 are input to the shift register 21, and are also connected to the selection circuit 15 as shown in FIG. Similarly, shift register 2
The output of the shift register 25 is connected to the selection circuit 18, the output of the shift register 25 is connected to the selection circuit 17, and the shift register 28 is connected to the selection circuit 16.

<Operation of Embodiment> Next, the operation of the above circuit will be explained using timer 1 in FIG.

First, before explaining the operation of the entire circuit, the operation of the selection signal generator 20 shown in FIG. 2 will be explained in advance.

At time tl as an initial state of operation, each shift register 21
〜30 outputs are all in the “L II state,” then N
The output of the OR gate 31 becomes ``)'', and this ``H'' signal is stored in the shift register 21. 1 from tl
At time tl after the clock time, the "H" signal stored in the shift register 21 is input and stored in the shift register 22, and is also input to the NOR gate 31, so the output of the NOR gate 31 becomes "L". . Thereafter, in the same way, each time a clock pulse (portion in Figure 3) is input, ""
l-1" signal is sequentially shifted to the subsequent shift registers 23 to 30, and when the 12th clock pulse is input from 1.00, the outputs of all shift registers 21 to 30 become "L". The initial state is returned and the above operations are repeated continuously.

Therefore, NOR gate 31, shift register 22 .
The selection pulses obtained from the respective outputs of 25 and 28 are pulses shifted at predetermined intervals with tl as the initial state, as shown in FIGS.

Next, the pattern generation circuit shown in FIG. 1 will be explained.

First, the 4-bit code sequences a l N bl N CI and dl are respectively input in parallel to the four parallel input terminals A to D at 11 o'clock, and one clock time later at tl, the next 4-bit code sequence is similarly input. a2, b2, C2 and d2 are input, and thereafter a 4-bit code sequence is input sequentially in synchronization with the clock pulse (FIG. 3A).

On the other hand, in the selection signal generator 20, at 11 o'clock, NOR
The output of the gate 31 is in the 11 state, and this "1" signal (selection pulse) is sent to the selection circuit 15 (see the same figure).
.

The selection circuit 15 that receives the selection pulse from the NOR gate 31 of the selection signal generator 20 at 11 o'clock inverts the inverter 11
The output of the inverter 11 is passed through one serial conversion circuit, but the output sign of this inverter 11 is 1 [1 m (') from 11 o'clock.
The code do (not shown) inputted to the input terminal of j1 is temporarily stored by the shift register 10, and
output from the shift register 10, and the inverter 11
The code (jG) is inverted and output by

At 11 o'clock, the selection circuits 16 to 18 do not receive the selection pulse from the selection signal generator 20 (to 2 to 2 in the same figure), so the code series input to the input terminals B, C1, and D bl, C1 and dl pass through respective selection circuits 16-18 and are input into one serial conversion circuit.

Therefore, the output signs of each selection circuit 15 to 18 at time C1 are d O% b l , CI, (jl
are inputted in parallel to the serial conversion circuit 19, and the serial conversion circuit 19 outputs the serial 7q Q sequences do, b+, Ct, and dl within one clock time from time C1 (FIG. 3).

At time C2, one clock time after time C1, the 'I-1' signal stored in the jl signal of the shift register 21 of the selection signal generator 20 is input to and stored in the shift register 22, and is also input to the NoR gate. 31, so no selection pulse is generated.

Therefore, the code series a2, bl, C2 and dl (A in the figure) inputted to the input terminals A-D at 12 o'clock pass through the respective selection circuits 15 to 18 and the serial conversion circuit 19
is input into the serial code sequence a2, bl, C2, dl (
(G) in the same figure is output.

Next, at C3, one clock after C2, 3m 1
1. ! The "tobi' signal stored at 11 o'clock in the shift register 22 of the signal generator 20 is input to the shift register 23 as input J3, and is also input to the selection circuit 18 as a selection pulse (see the same figure). Therefore, code sequences a3, b3 input in parallel to input terminals A-D at C3
and C3 pass through each of the selection circuits 15 to 17 and are input to the serial conversion circuit 19, but the selection circuit 18 allows the inverted sign output 3 from the impark 14 to pass through by the selection pulse.

Therefore, the output of the serial conversion circuit 19 at the time of C3 is a serial code sequence a3, b3, C3, and M3.

That is, the code sequence al input in parallel to input terminals A-D
, bl, c (..., the codes of the 10th and 11th bits from bl are output as C3, C3, and as a result, the pattern signal of the 10BIC code becomes 1
be qed.

Between the following (for medicine, the selection signal generator 20
A selection pulse is output from C6, and from code a4 to 11
The bit-th code CG is replaced with 56, and the code d is replaced at C9.
The code b9 of the 6th to 11th bits is replaced with 109, and the serial conversion circuit 19 outputs a 10BIC-encoded continuous serial pattern signal (FIG. 19).

Another Embodiment of the Present Invention (FIG. 4) In the above embodiment, a 1osic coded pattern signal output is generated, but this is not limited to the 10F31C code, but also the selection signal generator 20. By increasing or decreasing the number of stages of the shift registers 21 to 30 and determining the output of the selection pulse, an MB1C coded pattern signal output can be obtained.

Furthermore, in the above embodiment, the input code is a 4-bit parallel signal, and a selection circuit is provided for each.
As long as there are a plurality of codes within M+1 of the required code MB1C, it can be similarly applied by making the selection signal generator correspond to the code.

Furthermore, another embodiment of the present invention is shown in FIG.

In the same figure, 40 is a selection pulse to the selection circuit 15.
/X, and outputs a negative pulse.
is an exclusive OR circuit (EX-OR circuit), which has the output from the frequency divider 40 and the output from the shift register 10 as inputs, and its output is connected to the selector/path 15.

In the above circuit, until the selection pulse is output to the selection circuit 15 X times, the frequency division ill! The output of :40 remains "Tobi'", and the sign output of shift register 10 is inverted by exclusive OR circuit 41, passed through selection circuit 15, and output.

Then, when the selection pulse is output to the selection circuit 15 X times, the output of the frequency divider 40 becomes L II. Therefore, the sign output of the shift register 10 passes through the exclusive OR circuit 41 without being inverted, and the sign output of the shift register 10 passes through the selection circuit 15- as it is and is output.

That is, the code of the M+1-th bit in the MBIC code is replaced with a code that is not inverted in the M-th bit, and an error is inserted into the MB1C code.

In this circuit, M
[Since the error insertion rate of the '31C code can be changed, M
This is effective for checking the BIC code error detection function.

<Effects of the Present Invention> As is clear from the above description, the pattern generation circuit of the present invention converts code strings input in parallel into N systems into M[31C codes, and serially converts the code strings, thereby converting the input code strings into M[31C codes. The pattern signal is generated at a speed N times the code speed.

Therefore, unlike conventional circuits, high-speed elements are not required, and a high-speed MB1C coded pattern signal can be easily generated using commonly used relatively low-speed and inexpensive elements.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the pattern generation circuit of the present invention, FIG. 2 shows a specific example of a part of FIG. 1, and FIG. 3 shows the operation of FIG. 1. This is a time chart. FIG. 4 is a diagram showing another embodiment of the present invention. FIG. 5 is a diagram showing a conventional pattern generation circuit, and FIG. 6 is a diagram showing a conventional pattern generation circuit.
6 is a time chart showing the operation of FIG. 5. FIG. 1: Frequency divider, 2: Shift register, 3: Inverter, 4: Switch, 1o: Shift register, 11-14...
...Inverter, 15-18...Selection circuit, one...Serial conversion circuit, 20...Selection signal F3 generator, 21-30... ...Shift register, 31...NOR gate, 40...
- Frequency divider, 41...exclusive OR circuit. Patent Applicant: Anritsu Corporation Representative of Nippon Telegraph and Telephone Corporation Patent Attorney Makoto Hayakawa 1 Figure 2 Figure 2゜Figure 4

Claims (2)

[Claims] (1) A selection signal generator that outputs selection pulses; N inverters that input code strings that are synchronously input in parallel to N systems and invert the codes; and have two input terminals; The code string is input to one input terminal, the inverted code from the inverter is input to the other input terminal, and the input is input to either input terminal depending on the presence or absence of the selection pulse from the selection signal generator. a serial conversion circuit for converting the N series of parallel output code strings of the selection circuits into a serial code string; parallel synchronization with the N series; The input code string is divided into M+1 bits, and a selection pulse is sent from the selection signal generator to the selection circuit to which the M+1-th code is input, so that the M+1-th code becomes the M-bit code. N parallel code strings (M bit 1 complementary code, MB1
C code) into a serial code string by the serial conversion circuit, and generates an MB1C coded pattern signal. (2) A 1/X frequency divider circuit that receives a signal from one of the N selection signal generation circuits and outputs one pulse every time X pulses are input, and the output of the frequency divider circuit. Claims characterized by having an exclusive OR for inputting an error pulse and controlling the M+1-th bit signal to be replaced with an inverted code or a non-inverted code for the M-th bit depending on the presence or absence of the error pulse. The pattern generation circuit according to item 1.