JPH0432823Y2 - - Google Patents

Description

[Detailed explanation of the idea] (1) Technical field of invention The present invention relates to a code conversion circuit.

(2) Technical background For example, when writing digital data in a magnetic disk device, it is common to write NRZ data as is. However, when writing NRZ data as is, the following two problems arise. The first problem is that NRZ data does not change at all unless there is a change in 1 or 0 of the original data, and the operating frequency band must be considered from the DC component, resulting in an extremely wide band. The second problem is that, as mentioned above, if the NRZ data does not change at all, the so-called clock component cannot be extracted, making decoding difficult. In order to solve these problems, a coding conversion method has been proposed in which 2-bit and 4-bit NRZ data are converted into 3-bit and 6-bit 1/7 codewords, respectively. For example, IEEE Trans on Mag Vol MAG12 No.6
1976 November et al. Here, the 1/7 code word means a code in which at least one bit 0 and a maximum of 7 bits are inserted between one bit 1 and the next bit 1. In this way, since bit 0 always appears within a predetermined period, the above 2.
Two problems are solved at the same time. In addition, in the coding conversion method proposed above, the code conversion is performed from 2 bits to 3 bits and from 4 bits to 6 bits, so the frequency F increases by 1.5 times, but bit 0 is converted from bit 1 to bit 1. Since there is always one in between, the recording frequency is reduced by 0.75 times as a result.
As a result, the so-called recording density becomes even higher than in the conventional case where NRZ data is written as is, and there is also the advantage that the utilization efficiency of the magnetic disk is improved.

(3) Prior Art and Problems By the way, as mentioned above, although the coding conversion method can exhibit excellent functions, there are still few code conversion circuits available on the market to implement this method. One possible attempt is to configure the code conversion circuit with a ROM. That is, by using 2-bit or 4-bit NRZ data as the address input of the ROM, a 3-bit or 6-bit code word is read from the ROM. Although this is a simple idea and is realistic, considering the limited access time of ROM, it cannot support high-speed code conversion. Therefore, there is a strong demand for a code conversion circuit that can be implemented in a discrete configuration without using ROM.

(4) Purpose of the invention In view of the above circumstances, the purpose of the invention is to realize a code conversion circuit that does not use a ROM.

(5) Structure of the invention In order to achieve the above object, the present invention has an input register that sequentially holds multiple bits of input data consisting of an arbitrary bit string, and two input data held in the input register. It is classified into multiple bit modes with bit modes larger than bit as units,
a logic circuit for code conversion that converts the code of the input data based on the classification; an output register that sequentially holds the output from the logic circuit for code conversion and sends out the held output data; a bit mode classification logic circuit that classifies the input data connected and sequentially held in the input register into the plurality of bit modes; and a bit mode classification logic circuit that classifies the input data sequentially held in the input register; The present invention is characterized by comprising a timing control circuit that sets the timing for holding the output from the logic circuit in the output register and the output timing for taking out the output data from the output register.

(6) Embodiment of the invention FIG. 1 is a chart showing the correspondence when converting the codes of 2-bit and 4-bit NRZ data into 3-bit and 6-bit code words, respectively. This invention takes the NRZ data on the left, e.g. (10), as input, and the code word on the right, e.g. (010).
We will discuss the circuit for code conversion to . In the above diagram, there is a code word bit _C6 marked with an x, which represents an undefined bit that becomes 0 or 1 depending on the 1 or 0 of the code bit that immediately precedes it. In any case, it is not so easy to realize a code conversion circuit that can almost instantaneously obtain the correspondence shown in the diagram of FIG.

FIG. 2 is a circuit diagram showing an embodiment of a code conversion circuit based on the present invention. The configuration and operation of this code conversion circuit will be explained below. Incidentally, FIG. 3 is a time chart showing the waveforms of the main parts used to explain the operation of the code conversion circuit of FIG. 2. Referring to Figures 2 and 3, the input data Din input from the left side in Figure 2 (NRZ data in Figure 1)
is code-converted by the code conversion circuit 20 of the present invention, and is output in bit serial form as output data Dout (code word in FIG. 1) from the right side of the figure. This input data Din is illustrated in column (10) of FIG. 3, and the corresponding output data Dout is illustrated in column (11) of the same figure. In this case, the input data Din (NRZ data) is shown in column (1) of Figure 3.
It is synchronized with the 1F (Frequency) clock CLK, and the output data Dout is shown in column (2) of the same figure.
It is synchronized to the clock CLK, which is 1.5 times the frequency, or 1.5F. It becomes 1.5 times as much as 2 in the same time.
This is because code conversion is performed from bit to 3 bits (or from 4 bits to 6 bits).

First, the input NRZ data Din is bit-serially transferred to a shift register (4-bit shift register) 21.
is input. 4 bits in shift register 21
D ₁ , D ₂ , D ₃ and D ₄ correspond to the case where each bit D ₁ to _{D 4} of the NRZ data in FIG. 1 is completely filled.
The first thing to do here is what is called synchronous retraction. For this purpose, a start bit pattern is added immediately before the original NRZ data. The start bit pattern may be any pattern as long as it can be clearly distinguished from a gap pattern. Generally, the structure of each track on a magnetic disk is (gap pattern) (sync bit pattern) (data pattern), so a gap pattern may be (1111...).
, and the sync bit pattern (synchronous
The start bit pattern (1110) should be given as the bit pattern). Hereinafter, the start bit pattern (1110) will be explained as an example. Now write data command (WC:
Write Command) is given (the rise of WC in column (3) of Figure 3). This Directive WC:
A flip flop forming part of the synchronous pull-in circuit 35
An inverted level is applied to the reset input of flip-flop 23, making flip-flop 23 active. On the other hand, the AND gate 22 constituting a part of the synchronization pull-in circuit 35 is supplied with data bits (D ₁ to D ₄ ) from the shift register 21 whose respective inputs are inverted in level. However, among the bits of the shift register 21, D ₄ to _{D 2} are output as inverted outputs (indicated by a small circle).
As for D ₁ , output it as it is and pass it to AND gate 22.
is given. Therefore, when the start bit pattern (1110) is exactly aligned at (D ₄ D ₃ D ₂ D ₁ ) in the shift register 21, the AND gate 22
(0000) is applied to the inputs of , and the AND gate 22 sends out an output of 1 by inverting the level of each input.
This output 1 is shown in column (4) of FIG. This output 1 sets the flip-flop 23, which is now active by WC, and its output P also rises (column (5) in FIG. 3). In response to this output P, the output Q of the flip-flop 24 forming a part of the synchronization pull-in circuit 35 falls (column (6) in FIG. 3). As shown in the figure, this output Q is synchronized with clock 1.5F・CLK, and the load
Functions as shift enable signal LSE. This load shift enable signal LSE is a logic 0
When this happens, the load/shift switching gate (NOR gate) 27 is opened. Loading here means converting the code of the NRZ data in the shift register 21 (according to the correspondence shown in FIG. 1) and inputting the converted data into the 6-bit shift register 28 in parallel. Furthermore, the term "shift" refers to pushing the code-converted data (code word) loaded into the shift register 28 upward in synchronization with the clock 1.5F/CLK. Note that each bit C ₁ -C ₆ of shift register 28 corresponds to each bit C ₁ -C ₆ of the code word of FIG.

In this way, when the synchronous pull-in for the input data Din (NRZ data) is completed and the load/shift switching gate 27 is opened, the original
Start code conversion of NRZ data. However, this code conversion cannot be started immediately. Because the first
This is because, as shown in the figure, a 2-bit mode and a 4-bit mode appear randomly in the input NRZ data. Therefore, it is necessary to identify in advance whether the mode is 2-bit mode or 4-bit mode. Preferably, this identification is also simple and quick. Therefore, in this embodiment, the contents of the shift register 21 are checked to discover a bit pattern specific to one of the modes. 1st again
Referring to the figure, the fourth and third
When we focus on bits (D ₄ D ₃ ), we see a unique bit pattern of (00). That is (D ₄ D ₃ )
When is (00), it is 4-bit mode, not 2-bit mode. A mode identification circuit performs this mode identification, specifically an AND gate 29, and (D ₄ D ₃ ) of the shift register 21.
When the output becomes (00), that is, the inverted output marked with a small circle becomes (11), an output S (see column (9) in Figure 3) indicating that the mode is 4-bit mode and not 2-bit mode is sent out. Ru. Therefore, when the output S is logic 0, it is the 2-bit mode. This output S is further applied to a preset circuit 37. Preset circuit 37 includes an AND gate and an inverter as shown. Presetting means initializing the count value of the count circuit 36, which will be described later. This count value indicates the bit shift amount in the shift register 28 mentioned above. This count value is 2 (=3-
1). Of these, 3 in parentheses is the number of bits of the code word corresponding to the 2-bit mode.
Also, the count value is 5 in 4-bit mode.
(=6-1). The meaning of 6 is the number of bits of the code word corresponding to this 4-bit mode. According to these count values, shift register 2
In the 2-bit mode of NRZ data, push out 3 bits of the code word as 2 → 1 → 0 (serial out of data Dout).
In 4-bit mode of NRZ data, 5→4→
The 6 bits of the code word are serially output in the order 3→2→1→0. This is because a code word consists of 3 or 6 bits. These 2 → 1 → 0, 5 → 4 → 3 → 2 → 1
→0 is explained in column (8) of FIG. 3 (described later).

When the contents of the shift register 28 are shifted word by word using the clock 1.5F.CLK as described above, the contents must already be code-converted according to the correspondence shown in FIG. For this reason,
The NRZ data in shift register 21 must be transcoded almost instantaneously and loaded into shift register 28 in parallel, asynchronously with the aforementioned clock. The code conversion logic circuit 38 performs this. The logic within this circuit 38 is
They are arranged to produce the correspondence shown in the figure. This logic can be constructed relatively simply by paying attention to certain regularities. For example, bits C ₃ and C ₂ of the codeword are always 0. Bit C ₁ is always the same as bit D ₁ of the NRZ data. Bit C ₄ becomes 1 because bit (D ₄ D ₃ ) of NRZ data is
(10). Bit C ₅ becomes 1 because
When the bit (D ₄ D ₃ ) of the NRZ data is (10), or when the bit (D ₄ D ₃ ) is (00) and the bit (D ₂ D ₁ is (11) or (00)) There is.
Regarding _C6 , in the 2-bit mode of NRZ data (D ₄ D ₃ ) is (10) and 0, and in the 4-bit mode (D ₄ D ₃ ) is (00) and (D ₂ D ₁ ) is (11). )
Or it becomes 0 when it is (00). In this case, the output S of the AND gate 29 described above is also used for bit mode determination. Also, since the x bit of bit C ₆ is the inverted code word bit immediately before it, the inverted output X of C ₆ above the shift register 28 is fed back to a predetermined gate in the circuit 38 . In this way, the inside of the shift register 21
After NRZ data is always subjected to a specified code conversion,
It is loaded in parallel as a code word into shift register 28.

The codewords loaded in parallel as described above are 3-bit codewords (C ₆ to _{C 4} in Figure 1).
The amount of shift to be serially output from the shift register 28 differs depending on whether the data is a 6-bit code word (C ₆ to C ₁ in the figure) (as described above). For this,
The count circuit 36 is enabled. The count circuit 36 has a load/shift switching output LS' (Load,
Shift), and now passes through the load shift switching gate 27, which is opened by the load shift enable signal LSE (column (6) in Figure 3), and becomes the load shift switching output LS. ,on the one hand,
Input at counter 25 in counting circuit 36
S ₁ and, on the other hand, to the shift input S ₂ of the shift register 28 . To make the explanation easier to understand, the bit string (1,0) of the NRZ data Din is clocked as shown in column (10) of Figure 3.
It appears in synchronization with 1F・CLK, and as a result, as shown in column (11) in the same figure, the code word bit string (1, 0) is output in synchronization with clock 1.5F・CLK with a slight delay. Let's take this as an example. First of all,
The start bit pattern SBP ₁ (1110) described above is
If it appears within Din, the output of the AND gate 22 rises as shown in column (4) of FIG. 3, and synchronization is entered. In this embodiment, two consecutive start bit patterns SBP ₂ (1110) are added to SBP ₁ to function as a so-called leading flag.
This SBP ₂ is followed by the original NRZ data, for example (0010), (11)... The corresponding code words are (100000), (101), etc. As shown in column (7) of FIG. 3, the load/shift/switch output LS sequentially repeats the load and shift operations. For example, in Shift3, Load3 loaded instantly
The 6-bit code word in the shift register 28 corresponding to the NRZ 4-bit mode data is
As described above, the shift is 5→4→3→2→1→0. Then, in the next Load 4, 3 in the shift register 28 corresponding to the NRZ 2-bit mode data
Shift the bit code word (C ₆ C ₅ C ₄ ) from 2 to 1 to 0. This is done in Shift4. Said
At Load3, it is determined by the output S (logic 1) of the AND gate 29 that the code word corresponding to the 4-bit mode data of the NRZ data is loaded into the shift register 28 (the third Column (9) in the figure). Therefore, when this output S becomes logic 1, a 6-bit shift must be performed in Shift3. For this reason, the counter 25
The (D ₂ D ₁ D ₀ ) input must be preset with a count value of 5 in binary. This count value 5 corresponds to when the input (D ₂ D ₁ D ₀ ) is (101). This (101) is the preset circuit 3.
It is given by the AND gate of 7. In the above case, the preset circuit 37 receives the output S (logic 1) from the AND gate 29 and inputs the 4-bit mode data of the NRZ data.
Logic 1 is applied from one of the output AND gates (upper part of the diagram) and logic 0 is applied from the other (lower part of the diagram) to (D ₂ D ₁ D ₀ ) of the counter 25 as (101). The counter 25 constitutes a subtraction counter, and subtracts one value each time the clock 1.5F.CLK arrives. During the subtraction as 5→4→3→2→..., the NOR gate 26 that receives the (Q ₂ Q ₁ Q ₀ ) output of the counter 25 continues to output logic 0. That is, the load/shift switching output LS' is at logic 0, and the load/shift switching output LS' is at logic 0.
The load/shift switching output LS from 7 becomes logic 1 (Logic 1 Shift3 in column (7) of FIG. 3).
This logic 1 switching output LS is the shift register 2
8's shift input _S2 to place it in shift mode. On the other hand, the switching output LS of logic 1 is
Applied to input S ₁ of counter 25 to place it in subtraction mode of operation. Furthermore, the two-output AND gate is closed through the inverter of the preset circuit 37. Then, when the above subtraction exceeds 5→4...→1 and reaches 0, the output (LS') of the NOR gate 26
changes to logic 1, and the load/shift switching output LS from the switching gate 27 becomes logic 0 (Logic 0 Load4 in column (7) of FIG. 3). This results in
The shift register 28 switches from shift mode to load mode and instantly takes in the next code word. On the other hand, a two-output AND gate is opened through the inverter of the preset circuit 37, and the output S (from the AND gate 29) at the time of this load is passed. In this example, NRZ 2-bit mode data is being input, and the output S is logic 0 (the logic shown in column (9) below Load 4 in column (7) in Figure 3 is 0). ), counter 2
5 (D ₂ D ₁ D ₀ ) becomes (110), and a count value of 2 is given to the counter 25 in binary.
As mentioned above, the counter 25 constitutes a subtraction counter, and subtracts by 1 each time the clock 1.5F.CLK arrives. Here, while subtracting 2→1→…,
NOR that receives the (Q ₂ Q ₁ Q ₀ ) output of counter 25
Gate 26 continues to output a logic 0. That is, the load/shift switching output LS' becomes logic 0, and the load/shift switching output LS from the load/shift switching gate 27 becomes logic 1 (Shift4 of logic 1 in column (7) in FIG. 3). ). This logic 1 switching output LS is applied to the shift input _S2 of shift register 28 to place it in shift mode. On the other hand, its logic 1 switching output LS is applied to the input S ₁ of the counter 25 to place it in the subtraction mode of operation. Furthermore, the two-output AND gate is closed through the inverter of the preset circuit 37. Then, when the above-mentioned subtraction exceeds 2→1 and reaches 0, the output LS' of the NOR gate 26 changes to logic 1, and the load/shift switching output LS from the switching gate 27 becomes logic 0 ( Logic 0 (Load5) in column (7) of Figure 3). This causes the shift register 28 to switch from shift mode to load mode and load the code word corresponding to the next NRZ data input. In the above Shift4, the code word (C ₆ C ₅ C ₄ ) in the shift register 28 is only serially output, and the code word (C ₃ C ₂ C ₁ ) is output as is (C ₆ C ₅ C ₄ ) Stops at position. However, this data has no meaning and is overwritten and disappears when the code word corresponding to the next NRZ data is input in parallel.

The above explanation was about the 1/7 code word generation circuit based on the code conversion table shown in Figure 1.
In general, the same can be applied to a 1/N (N is a natural number) code word generation circuit. That is,
For example, the k-bit, l-bit, and m-bit modes of NRZ data can be transcoded into K-bit, L-bit, and M-bit words of the codeword. The circuit configuration in this case is basically the same as that in FIG. 2. FIG. 4 is a block diagram showing an example of a code conversion circuit for obtaining a general 1/N code word. .
Reference numbers 41, 42, 43, 44, 45, 46, 47 in this figure,
Components marked 48, 50, 57, and 58 are shown in Figure 2.
They are substantially the same as the components marked 21, 22, 23, 24, 25, 26, 27, 28, 30, 37, and 38, respectively.
The difference is in the part that detects the start bit pattern and the count value to be preset in the counter 45. The start bit pattern needs to be reset for the new code conversion circuit 40. Further, the count value ("2" or "5" in the case of FIG. 2) must be reset for each of the k, l, and m bit modes. However, once the operating principle described above is understood, it is obvious how to set it. Like this,
Even given another transcoding technique, NRZ
The basic process for obtaining the code word output D'out from the input data Din' is the same as in the case of FIG.

(7) Effects of the invention As explained in detail above, according to the invention, NRZ in which multiple types of bit modes of 2 or more bits coexist.
Since the code conversion circuit from data to code words is concretely realized and is mostly composed of gate circuits, high-speed operation is expected compared to the case of using ROM, which requires access time.

[Brief explanation of the drawing]

Fig. 1 is a chart showing the correspondence when code converting 2-bit and 4-bit NRZ data into 3-bit and 6-bit code words, and Fig. 2 is a circuit showing an embodiment of the code conversion circuit based on the present invention. Figure 3 is a time chart showing the waveforms of the main parts used to explain the operation of the code conversion circuit shown in Figure 2, and Figure 4 is a block diagram showing an example of a code conversion circuit that obtains a general 1/N code word. It is. 20, 40... code conversion circuit, 21... shift register, 27... load/shift switching gate,
28...Shift register, 29...AND gate,
35...Synchronization pull-in circuit, 36...Count circuit, 37...Preset circuit, 38...Sign conversion logic circuit, Din...Input data, Dout...Output data.

Claims (1)

[Claims for Utility Model Registration] Input data consisting of an arbitrary bit string is
A first conversion mode converts bits to n bits, and a second conversion mode converts m' bits to n' bits, where m>m', n>n', m/n=
A code conversion circuit that converts codes according to a predetermined conversion rule having two conversion modes: an input register 21 that sequentially holds m bits of data to be input, and converts the m bits of data held in the input register 21 into n' bits of data, and converts the m bits of data into n' bits of data in the two conversion modes. A code conversion logic circuit 3 that outputs an identification signal indicating which mode should be used for conversion.
8, and the n' bit output of the code conversion logic circuit 38;
Part of the data held in the input register 21
_D1 and fixed data are supplied, and the output of the n' bits, part of the data _D1 , and fixed data are held together by the load signal, and synchronized with the output clock of frequency n/mF. and an output register 28 that sequentially outputs the held data, and an identification signal that operates in synchronization with the output clock and that is output by the code conversion logic circuit 38.
When indicating the identification of the second conversion mode, the load signal is generated after n output clocks are supplied to the output register 28, and when indicating the recognition of the second conversion mode, the load signal is output to the output register 28. a timing control circuit 36 that generates the load signal after the m output clocks are supplied, and a timing control circuit 36 that generates the load signal after recognizing a bit pattern representing the start of code conversion from the m-bit data held in the input register; A code conversion circuit comprising a start pattern recognition circuit 35 that validates the load signal generated by the circuit 36 and supplies it to the output register 28.