JPH07307726A - Bit buffer circuit - Google Patents

Abstract

PURPOSE:To improve the reliability in the receipt and delivery of data between circuits by realizing a bit buffer circuit which is capable of overlaying data without any omission of data when the data are overlaid on internal frame pulses and clocks. CONSTITUTION:In a bit buffer circuit, a single D-FF (hereinafter referred to as D-FF [0]) is provided in addition to a D-type flip flop group (D-FF group) composed of n D-type flip flops (D-FF). Input data are supplied to the data terminal and a priority processing circuit is provided. The priority processing circuit where a reading frame pulse is preferentially outputted, the pulse that a decoder having the same phase as the reading frame pulse outputs is suppressed and the pulse of the decode signal which is not the same in phase as the reading frame pulse is outputted is provided. The output of the priority processing circuit is defined as the select signal of a selector and the outputs of the single D-FF [0] and D-FF are selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit buffer circuit for transferring input data synchronized with a frame pulse and a clock outside a circuit such as an LSI to a frame pulse and a clock inside a circuit such as an LSI, and more particularly, The present invention relates to a bit buffer circuit that can prevent the loss of the first bit of a first frame after reset release.

Generally, in an information communication device, it is usual that data is processed under different frame pulses or clocks between the outside and inside of a circuit section. When data is passed between circuits, the internal frame is processed. Rereading of the data is done with pulses and clocks. Therefore, it is important that no data error such as data loss occurs during the rereading.

[0003]

2. Description of the Related Art FIG. 5 shows a conventional bit buffer circuit. In FIG. 5, 1a is a first OR circuit, 1b is a second OR circuit, 2a is a first counter, 2b is a second counter, 3a is a first decoder, 3b is a second decoder, Reference numeral 4 is a D-type flip-flop group (D-FF group) including n D-type flip-flops (D-FF), and 5 is a selector.

The first and second counters are m-bit n-ary counters. Also, the first and second decoders are m
Decodes binary number of bits and outputs decoded signal from 1 to 2
It outputs to the output line corresponding to ^m . When n is smaller than 2 ^m , n output lines are connected to the circuit in the subsequent stage,
(2 ^m −n) output lines are open. The outputs of the first decoders are supplied to the enable terminals of the D-FFs forming the D-FF group, respectively, whereby the input data is latched in the D-FF group. A signal obtained by decoding 0 latches D-FF [1], a signal obtained by decoding 1 latches D-FF [2], and the maximum count number (n-1)
It is assumed that the signal obtained by decoding is to latch D-FF [n]. And the selector is D-FF
One of the outputs of n D-FFs from [1] to D-FF [n] is used as n outputs of the second decoder, select [1], select [2], ... It is selected by the select [n]. The signal obtained by decoding the count value 0 of the second counter is the select [1], and the signal obtained by decoding the maximum count value (n-1) is the select [n]. As shown in FIG. 7, the structure of the selector is such that AND circuits are arranged at the cross points and the outputs of all the AND circuits are ORed and output.

In the following description, m = 4 and n = 12 will be described. The first counter is loaded by a write frame pulse, counts from an initial value 0, and outputs a carry when counting "11". This carry loads the first counter via the first OR circuit and restarts counting from "0". For example, when the count value is 0, the first decoder outputs a decode signal for the count value 0 to the output line [1], and this signal enables the D-FF [1]. Then D-FF
The data input to the data terminal [1] is latched,
It is output from D-FF [1] and guided to the selector. When the count value becomes 1, a circuit for decoding 1 outputs a decode signal to the output line [2] to enable D-FF [2]. The same operation is performed thereafter, and when the count value is 11, the D-FF 12 is enabled. Now, since m = 4, the decoder has the ability to convert a 4-bit binary number from 1 to 16, but since it deals with a binary number here,
Of the output lines of the decoder, 13 to 16 are open.

On the other hand, the second OR circuit, the counter, and the decoder also operate in the same manner, outputting a signal obtained by decoding a 4-bit binary number to the output lines [1] to [12] of the second decoder, The selection [1] to the selection [12] are supplied to the selection terminal of the selector. D-FF [1] to D-FF [1 supplied to the input terminal of the selector by this signal
The data latched in 2] is selected and output.

FIG. 6 is a time chart of the configuration of FIG. Reset release signal is reset when "H",
When it is “L”, it has the meaning of releasing and controls the first and second counters and the D-FF group. When the reset is released,
The first and second counters and the D-FF group become operable.
After that, when a write frame pulse is input, the first counter is loaded and counts the initial values 0 to 11. When 11 is counted, a carry is output and the counter is loaded again.

Now, in the case of the timing when the write frame pulse is inputted, the count value of the first counter is 2 in the example of FIG. Therefore, the decoder receives this count value of 2, the circuit for decoding 2 outputs a decode signal to the output line [3], and enables the D-FF [3]. At this time, since the input data is input in synchronization with the write frame pulse, the first bit a of the input data is a.
Is a signal D-FF for enabling D-FF [3]
[3] It is latched by EN and appears at the output of D-FF [5].

On the other hand, when the read frame pulse is applied with the phase shown in the figure, the second counter is loaded with the read frame pulse. Therefore, the select [1] is input to the select terminal of the selector to which the output line [1] of the second decoder is connected. Since the select [1] selects the signal of the D-FF [1] connected to the input terminal of the selector, the second bit b of the input data is selected by the select [1] and the read data b Become the displayed bit. Then, c and d are sequentially read out.

By the way, the first bit "a" is latched by the D-FF [3] as described above. Then, the D-FF [3] is selected by the select [3]. That is, the first bit a is read at the illustrated phase of the read data.

That is, there is a problem that the input data becomes different data after being transferred to the internal frame pulse.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bit buffer circuit in which input data is saved even when switching to an internal frame pulse and a clock in order to cope with such a problem.

[0013]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1a is a first logical sum circuit, 1b
Is a second OR circuit, 2a is a first counter, 2b is a second counter, 3a is a first decoder, 3b is a second decoder, 4 is n D-type flip-flops (D-FF).
The D-type flip-flop group (D-FF group), 5 is a selector, 6 is a single D-FF, and 7 is a priority processing circuit. The first and second counters and the first and second decoders operate exactly the same as the counters and decoders in the configuration of FIG.

The structure of FIG. 1 is characterized by a single D-FF (hereinafter referred to as D-FF).

[0]) to supply input data to its data terminal and supply a write frame pulse to its enable terminal, and to provide a priority processing circuit to give a read frame pulse the highest priority. This is to suppress the pulse output and output by the second decoder at the phase of the read frame pulse and supply it to the selector.

[0015]

The operation of the configuration shown in FIG. 1 will be described with reference to FIGS. In FIG. 1, the operations of the first and second counters, the first and second decoders, and the first and second OR circuits are exactly the same as those of the conventional bit buffer circuit, and therefore the description thereof is omitted. Input data is D-FF

The write frame pulse is also supplied to the data terminal of [0] and the write frame pulse is D-FF.

Since it is supplied to the enable terminal of [0], the first bit a of the F write data is D by the write frame pulse.
-FF

Latched by [0], D-FF

[0] Holds like output. The second bit b having the same phase as the count value 0 enables D-FF [1] to enable D-FF [1].
It is latched by D-FF [1] by EN.

On the other hand, when the read frame pulse is applied as shown in the figure, this is preferentially output and selected.

It is supplied to the select terminal of the selector as [0]. Select

[0] pulse is D-FF

Since the signal of [0] selects the latched signal, the first bit a of the input data a
Is output like read data. After that, b, c,
It is read as d.

On the writing side, the input data a
Is latched by a signal obtained by decoding 2 in the D-FF [3], and is read by the select signal corresponding to the count value 2 of the second counter on the read side, and the read data has a phase surrounded by a broken line. a appears. However, since the read side handles the data in synchronization with the read frame pulse, this isolated a is not actually used and is not a problem.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 3 is an example of a priority processing circuit. In FIG. 3, reference numeral 71 is a logical inversion circuit, and 72 to 74 are logical product circuit groups composed of n logical product circuits. The read frame pulse is output as it is, and the logic is inverted by the logic inverting circuit to be guided to one input terminal of all the AND circuits. All the outputs from the decoder are guided to the other input terminals of all the logical product circuits forming the logical product circuit group without duplication. Then, the read frame pulse and the outputs of all the AND circuits are output in parallel.

FIG. 4 is a time chart of the configuration of FIG. When a read frame pulse is input, the counter is loaded and counts repeatedly from 0 to 11,
It has already been described that the second decoder outputs the decode signal after the select [1] in FIG. The decode signal and the read frame pulse are input to the configuration of FIG. Since the frame pulse is logically inverted and supplied to one input terminal of the AND circuit, all the pulses of the decode signal having the same phase as the frame pulse are suppressed. Then, the decode signal whose phase does not match the phase of the frame pulse is output as a select signal without being suppressed by the frame pulse.

[0020]

As described above, according to the present invention, a bit buffer circuit capable of transferring data to the internal frame pulses and clocks without loss of data is realized. It becomes possible to improve reliability.

[Brief description of drawings]

FIG. 1 is an embodiment of the present invention.

FIG. 2 is a time chart of the configuration of FIG.

FIG. 3 is a configuration of a priority processing circuit.

FIG. 4 is a time chart of the configuration of FIG.

FIG. 5 is a conventional bit buffer circuit.

FIG. 6 is a time chart of the configuration of FIG.

FIG. 7 shows a configuration of a selector.

[Explanation of symbols]

 1a 1st OR circuit, 1b 2nd OR circuit 2a 1st counter, 2b 2nd counter 3a 1st decoder 3b 2nd decoder 4 D-type flip-flop group 5 Selector 6 Single D Type flip-flop 7 priority processing circuit

Claims (2)

[Claims] 1. A first m-bit n-ary counter (2a) loaded and counted by a logical sum (1a) of a write frame pulse and a carry signal, and an output of the first m-bit n-ary counter. A first decoder (3a) for decoding and selecting an output line corresponding to the count value from the n output lines and outputting the decode signal; and an input state that is enabled by the output of the first decoder. To the data terminal and the logical sum (1) of the read frame pulse and the carry signal.
a second m-bit n-ary counter (2b) loaded and counted by b) and decoding the output of the second m-bit n-ary counter and outputting from the n output line the corresponding count value A bit buffer circuit comprising a second decoder (3b) for selecting a line and outputting the decode signal, and a selector (5) for selecting the output of the n memory circuit by the output of the second decoder, A single memory circuit (6) is provided, input data is supplied to a data terminal of the single memory circuit, and a write frame pulse is supplied to an enable terminal of the single memory circuit, The output of the circuit is supplied to the selector, the read frame pulse is preferentially output, and among the decode signals output by the decoder, the decode signal of the same phase as the read frame pulse is output. A priority processing circuit (7) for suppressing a pulse and outputting a pulse of a decode signal out of the decode signal output by the second decoder and not in the same phase as the read frame pulse. A bit buffer circuit, wherein the output of the single memory circuit and the output of the n memory circuit are selected as a select signal of a selector. 2. The bit buffer circuit according to claim 1, wherein the priority processing circuit receives a read frame pulse and an n output of the second decoder, and outputs the n output of the second decoder. The output is supplied to one input terminal of the n AND circuit without duplication or omission, and the read frame pulse is logically inverted and supplied to the other input terminal of the n AND circuit without duplication or omission. A bit buffer circuit which is a priority processing circuit which outputs a read frame pulse and an output signal of the n logical product circuit.