JPH0730434A - Decoder for variable length code - Google Patents

Abstract

PURPOSE:To obtain a variable length code decoder simplified at its circuit constitution and control by directly decoding serial data as it is. CONSTITUTION:A bit-serial variable length code to be decoded is inputted to a flip flop(FF) 1 synchronously with a clock CKI and latched. A memory 3 is a ROM storing information and the contents of the memory 3 are outputted by using the contents of the FFs 1, 2 as addresses. The variable length code has tree structure and each leaf part has a code word shown by a double circle. A black dot expresses an initial state, a void circle expresses a halfway state, the halfway state is transitted in the right or left direction in accordance with data '0' or '1' bit-serially inputted from the initial state, and at the time of reaching a double circle state, a decoded value is outputted. In an example shown by a broken line, data '001' are inputted, transitted through a route of S0, S3, S5, and S6 and reached to a double circle and '2' e.g. corresponding to the '001' is outputted as a decoded value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length code decoder.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram of a conventional decoder disclosed in Japanese Patent Laid-Open No. 4-258025. The bit-serial variable-length code is input to the serial / parallel (S / P) converter 11 in synchronization with the clock CLK, converted into parallel data here, and temporarily stored in the buffer memory 12. The contents of the buffer memory 12 are read into a rotating unit 13 composed of a bit shifter, and data shift is performed here so that the head portion of the unprocessed data is head-justified. The contents of the rotating unit 13 are given as an address to the decoding unit 14 composed of a ROM.

When a code exists at the input address, the decoding section 14 outputs the code as a decoded value, and at the same time, supplies the code length (the number of bits) for decoding to the rotating section 13. The rotating unit 13 packs the data accordingly and reads new data from the buffer memory 12.

[0004]

The decoder having such a structure has a complicated circuit structure, and accordingly the control is complicated, and the simplification of the circuit / control has been a problem. It is an object of the present invention to provide a variable-length code decoder that simplifies the circuit structure by making it possible to decode the serial data as it is and also makes the control simple.

[0005]

FIG. 2 is an explanatory diagram of the decoding principle of the present invention. The variable-length code has a tree structure as shown in the drawing, and has a code word as indicated by a double circle in the leaf portion. The black circles show the initial state, and the white circles show the intermediate state.
Data "0" input in bit serial from the initial state
, Transitions to the right or left according to "1". When the state of the double circle is reached, the decoded value is output. The example of the broken line in the figure shows the case where "001" is input, and S0 → S3
, S5, S6, a double circle is reached, and 2 corresponding to "001", for example, 2 is output as a decoded value.

[0006]

According to the present invention, since the serial data can be decoded as it is, the circuit configuration is simple, and accordingly, the control can be easily performed. This can also be detected by adding a unique word detector, so that even if the synchronization is lost, the initial state can be restored and subsequent decoding can be performed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 3 is a block diagram showing an embodiment of the decoder of the present invention. The bit-serial variable-length code to be decoded is input to the flip-flop 1 in synchronization with the clock CK1 and latched there. The memory 3 is a ROM that stores information on the relationship shown in FIG.
The contents of 2 are accessed as an address. The read data (parallel data) from the memory 3 is the data representing the decoded value and the data representing the internal state (both are multiple bits).
In addition, data CK2 (1 bit) to be used as a clock, data representing the decoded value is latched by flip-flop 4 (corresponding to the number of corresponding bits), and internal state table data is flip-flop 2 (corresponding to the number of corresponding bits). Latched on. The data CK2 to be used as a clock is given to the flip-flop 4 as a clock. The clock CK1 is applied to the flip-flop 2.

Table 1 shows an example of code words, code lengths and decoded values corresponding to FIG. In this case, "11010011
It is assumed that 101 "has been input. Table 2 shows the relationship between the input (flip-flop 2 side) and output of the variable-length code memory 3, CK2, and the decoded value in this case. The operation of the decoder of FIG. 3 will be described with reference to.

[0009]

[Table 1]

[0010]

[Table 2]

In the initial state, the flip-flops 1 and 2 are reset, and the state is represented by S0 in FIG. When the first "1" is input, this is latched in flip-flop 1. On the other hand, the flip-flop 2 has a content corresponding to S0. The memory output in this case is S
The content is equivalent to 1. The states of S0 and S1 have a significant output to the flip-flop 2 side, but there is no significant output to the flip-flop 4 side and CK2.

When the next "1" is input, the output of the memory 3 enters the state of S2 (solid line in FIG. 2), the decoded value "0" is output to the flip-flop 4, and CK2 is accordingly output. Is output. In the state where the decoded value such as S2 is obtained, the output to the flip-flop 2 side is equal to the initial state S0. Therefore, depending on the next input of "01", it transits to S3 and S4,
Get the decrypted value 1 and CK2. Similarly, the decoded value 2,
0 and 1 are obtained. When the unique word "000001" is input, there is no decoded value output, and only the output returning to the initial state S0 is given to the flip-flop 2.

FIG. 4 is a block diagram showing another embodiment of the decoder of the present invention. This embodiment differs from the embodiment of FIG. 3 in that the unique word detector 5 is provided. That is, the variable length code to be decoded is clocked to the unique word detector 5.
Input in synchronization with CK1. The unique word detector 5 includes a shift register having the same number of stages as the number of digits of the unique word, a parallel output of the shift register, and a logic circuit for determining whether the unique word “000001” matches.
Is detected, a reset signal is output to the direct reset terminal R of the flip-flop 2. The other structure is similar to that of the embodiment shown in FIG.

[0014]

[Table 3]

Table 3 shows the input variable length code of this decoder when "11100100000010011101" is input, the input of the memory,
The output, CK2, the decoded value and the reset signal output from the unique word detector are shown. After the decoded value "0" is output by the input of "11" and the initial state S0 is returned,
Since "10" is input, the transition from state S1 to the back is not possible (○ a). That is, there is no address accessed by the output of flip-flop 2 and "0" of flip-flop 1 in the state of S1. Therefore, as shown in Table 3, read data from the memory 3 cannot be obtained for the subsequent "010000001". On the other hand, in addition to the function of the memory 3, the unique word detector 5 detects the unique word "000001" and resets the flip-flop 2. Then, it is possible to return to the initial state S0, and the subsequent "001" is decoded as "2" (○ b).

Although the unique word is detected in the state S10, the unique word itself is output from the flip-flop 4 as a decoded value. Then, it is used for a special purpose such as a line feed signal in a circuit in the subsequent stage.

[0017]

According to the present invention as described above, since the serial data can be decoded as it is, the structure is simple as shown in the embodiment and no complicated control is required. Further, when the unique word detector is provided, even if a bit error occurs due to noise or the like, it is possible to surely decode after the unique word.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional decoder.

FIG. 2 is a diagram explaining the principle of decoding according to the present invention.

FIG. 3 is a block diagram of a decoder of the present invention.

FIG. 4 is a block diagram of another embodiment of the present invention.

FIG. 5 is a diagram illustrating the principle of decoding according to the present invention.

[Explanation of symbols]

 1,2,4 Flip-flop 3 Memory 5 Unique word detector

Claims (2)

[Claims] 1. In a bit-serial variable-length code decoder having a finite codeword in a leaf portion of a tree structure, storage means (2) for storing a current state in the tree structure, and the storage means. A memory (3) for storing the relationship between the current state and the next-order bit data and the next-order state is provided, and a tree structure is traced to obtain a decoded value when a predetermined state is reached. A variable-length code decoder characterized by being provided. 2. A detector for a unique word inserted in the variable-length code is provided, and when the detector detects a unique word, the storage means is configured to be in an initial state. Variable length code decoder.