JPH01113746U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an information processing control device according to an embodiment of the invention, and FIG. 2 is a diagram for explaining a conventional information processing control device. 1 is an instruction prefetch queue register, 2 is a next instruction register, 3 is an instruction register, 4 is an arithmetic control unit, 5
1 is an arithmetic processing unit, 6 is an input data register, 7 is a comparator, and 8 is an OR circuit. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

Claims (1)

[Scope of utility model registration request] There is an instruction prefetch queue register that stores instructions to be executed sequentially in a fetch queue in advance, a next instruction register that holds the data output from this instruction prefetch queue register as the next instruction to be executed, and a next instruction register that stores this output in the next instruction cycle. store,
an instruction register that holds the currently executed instruction; an arithmetic control unit that generates an arithmetic control signal from the outputs of the instruction prefetch queue register and the next instruction register;
In an information processing control device comprising an arithmetic processing unit that performs arithmetic processing according to the arithmetic control signal and also performs interrupt processing such as breaks, an input data register that holds data input from the outside;
A comparator that compares the contents of this input data register and the contents of the instruction register, and if the comparison results are equal, outputs that information as a break signal, ORs it with the break signal input from the outside, and sends it to the arithmetic processing unit. An information processing control device characterized by having a configuration consisting of a transmission circuit.