JPH01112819A - Operation compensating system for clock generating circuit - Google Patents

Abstract

PURPOSE:To continue clock generation when the supply of a reference clock signal is interrupted by providing a reset signal generating means and a clock generation circuit and generating a clock in the clock generation circuit based on a reset signal generated by frequency-dividing the input clock signal. CONSTITUTION:If a fault takes place in the supply of the external reference clock signal 215 and the reference clock signal 215 is fixed to a high level, a high level signal is always supplied to a reset terminal R of a counter 211 and the count of counters 211, 212 is stopped. Thus, the generation of the reset signal 217 is stopped. When no reset signal 217 is outputted from a D-FF 216, the reset of counting in the counters 221, 222 is not applied. However, when the input clock signals 213 is fed normally to the counters 221, 222, the counting of the counters 221, 222 is continued. Thus, the generation of the clock signals 223, 224 is continued.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Example ■, Correspondence between the Example and Figure 1 Relationship ■, Structure of the embodiment ■, Operation of the embodiment (i) Reset signal creation operation (ii) Clock signal generation operation during normal conditions (ij) Clock signal generation operation during abnormality ■, Summary of the embodiment ■ 3 Inventions [Summary] Regarding an operation compensation method for a clock generation circuit for creating a clock signal of a desired frequency based on a reference clock signal, the present invention relates to an operation compensation method for a clock generation circuit that performs a clock generation operation when the supply of the reference clock signal is stopped. For the purpose of continuous operation, an input clock signal and a reference clock signal are introduced, a reset signal generating means for dividing the frequency of the input clock signal to create a reset signal having a frequency equal to that of the reference clock signal, and an input clock signal and a reset signal. is introduced and synchronized to the reset signal,
and a clock generation circuit that divides the frequency of an input clock signal to generate a generated clock signal.

[Industrial application field]

The present invention relates to an operation compensation method for a clock generation circuit, and more particularly to an operation compensation method for a clock generation circuit for creating a clock signal of a desired frequency based on a reference clock signal.

[Conventional technology]

There is a clock generation circuit that generates clock signals of various frequencies based on a supplied input clock signal.

FIG. 4(A) shows a clock generation circuit that generates a 16 KHz clock signal synchronized with a 400 Hz reference clock signal input from the outside.

In the figure, a frequency divider 421 is composed of a counter, and divides the input clock signal of 64 KHz by a frequency division ratio of 4. In addition, the frequency divider 421 has a frequency of 400Hz.
A reference clock signal is input as a reset signal (resetting is performed when it is at a high level), and a frequency division operation is performed in synchronization with this reference clock signal.

FIG. 4(b) shows the operation timing of the above-described clock generation circuit. The frequency divider 421 is a 0 frequency divider 4 that starts counting the input clock signal in synchronization with the reference clock signal.
The count in 21 cycles from "0" to "3", and a generated clock signal is output when the count value is "3".

[Problem that the invention seeks to solve]

By the way, in the conventional method described above, if a failure occurs in the nine connection lines for supplying the reference clock signal and the reference clock signal is held at a high level, the operation of the clock generation circuit is interrupted. There was a problem that it would stop.

In particular, when the generated clock signal is created by dividing the input clock signal as described above, it is possible to continue generating the generated clock signal as long as there is no change in the synchronization method. However, a reset was forced.

The present invention was created in view of the above points, and an object of the present invention is to provide an operation compensation method for a clock generation circuit that can continue clock generation operation even when the supply of a reference clock signal is stopped. The purpose is

[Means for solving problems]

FIG. 1 is a principle block diagram of an operation compensation system for a clock generation circuit according to the present invention.

In the figure, the reset signal generating means 111 receives an input clock signal 113 and a reference clock signal 115, divides the frequency of the input clock signal 113, and generates a reset signal 117 having the same frequency as the reference clock signal 115.

The clock generation circuit 121 receives an input clock signal 113 and a reset signal 117, and receives the reset signal 117.
The generated clock signal 123 is generated by frequency-dividing the input clock signal 113 in synchronization with the input clock signal 113 .

Therefore, the overall configuration is such that the input clock signal 113 is frequency-divided based on the reset signal 117 created by frequency-dividing the input clock signal 113.

[For production]

The reset signal generating means 111 receives the input clock signal 11
3 to create a reset signal 117 having the same frequency as the reference clock signal 115,
supply to.

The clock generation circuit 121 includes the reset signal generation means 11
It starts operating in synchronization with the reset signal 117 supplied from 1 and divides the frequency of the input clock signal 113 to create a generated clock signal 123.

In the present invention, by performing clock generation in the clock generation circuit 121 based on the reset signal 117 created by dividing the input clock signal 113,
It becomes possible to continue the clock generation operation even when the supply of the reference clock signal is stopped.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment to which the clock generation circuit operation compensation method of the present invention is applied.

Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The reset signal generating means 111 includes a counter 211, a counter 212 . anime) 214. D-type flip-flop (hereinafter referred to as D-FF) 216, or gate 218
corresponds to

Input clock signal 113 corresponds to input clock signal 213.

Reference clock signal 115 corresponds to reference clock signal 215.

Reset signal 117 corresponds to reset signal 217.

The clock generation circuit 121 includes a counter 221° counter 222 . D-FF227. Corresponds to D-FF229.

The generated clock signal 123 is a generated clock signal 223,
This corresponds to the generated clock signal 224.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

■-Back trip■■ Structure In Figure 2, the clock generation circuit of the embodiment has four counters 211, 212, and 22 for frequency division operation.
1.222 and three D- to latch the output signal.
It includes FFs 216, 227, 229, an AND gate 214, and an OR gate 218.

Counters 211 and 222 are 4-bit counters for performing a frequency division operation with a frequency division ratio of 16. Counter 221 is a 2-bit counter for performing a frequency division operation with a frequency division ratio of 4. The counter 212 is a decimal counter for performing a frequency division operation with a frequency division ratio of 10.

64K) The input clock signal 213 of Iz is the input clock signal 213 of the counter 2.
11,212. D-FF216. counter 221.22
2. It is commonly input to each clock terminal CK of the D-FFs 227 and 229. Here, the input of the manual clock signal 213 to the D-FF 216 is performed using negative logic.

Further, the reference clock signal 215 of 400)(z is input to one input terminal of the OR gate 218.

The other input terminal of the OR gate 218 has a D-FF 216
A reset signal 217 output from the output terminal Q of is input. This reset signal 217 is transmitted to the OR gate 218
is input to the other input terminal of the counter 212,
221, 222. It is commonly input to each reset terminal R of D-FF227.229. The output of the OR gate 218 is input to the reset terminal R of the counter 211.

A signal output from the carry-out terminal CO of the counter 211 is commonly input to the enable terminal EN of the counter 212 and one input terminal of the AND gate 214.

Furthermore, the signal output from the carry-out terminal CO of the counter 212 is input to the other input terminal of the AND gate 214.

The output of the AND gate 214 is input to the input terminal of the D-FF 216.

Furthermore, the signal output from the carry-out terminal CO of the counter 221 is input to the input terminal of the D-FF 227, and the generated clock signal 223 of 16Kl[z is output from the output terminal Q of the D-FF 227.

The signal output from the carry-out terminal CO of the counter 222 is input to the input terminal of the D-FF 229, and the signal is output from the carry-out terminal CO of the counter 222.
A 4 KHz generated clock signal 224 is output from the output terminal Q of the FF 229.

l-Uradate ■Natsudori Tatsu Next, the operation of the operation compensation system of the clock generation circuit according to the embodiment of the present invention described above will be explained.

FIG. 3 shows the operation timing of the embodiment. In the figure, the "count value of the 4-bit counter" is the count value of the counter 211, and the "output of the 4-bit counter" is the count value of the counter 211.
The signal r output from the carry-out terminal CO of No. 11, r
The count value of the LO counter is the count value of the counter 212, rl.

The output of the decimal counter is a signal output from the carry-out terminal CO of the counter 212, and the input of rFF is D-F.
This is a signal input to the input terminal of F216.

Reference will now be made to FIGS. 2 and 3.

i i set t″″′ φ First, the operation of dividing the input clock signal 213 to create the reset signal 217 having the same frequency as the reference clock signal 215 will be described.

When the reference clock signal 215 is input to the reset terminal R of the counter 211 via the OR gate 218, the counting operation of the counter 211 is reset in response to the high level of the reference clock signal 215.

When the counting operation is reset, the counter 211 starts counting from a count value of "0".

The counting operation in the counter 211 is performed in synchronization with a 64 KHz input clock signal 213 that is input to the clock terminal CK of the counter 211.

Since the counter 211 is a 4-bit counter,
” to “F” (=15), and “F′
Next, return to "O" and count. Also, counter 2
In the counting operation No. 11, the output from the carry-out terminal co becomes high level in accordance with the count value "F".

Therefore, the input clock signal 213 (frequency 64K Hz
) is frequency-divided by the counter 211 (dividing ratio 16) to obtain a 4 KHz output signal from the carry-out terminal CO of the counter 211.

The output signal output from the carry-out terminal CO of the counter 211 is input to the enable terminal EN of the counter 212. The output signal input to the enable terminal EN is a permission signal for counting operation in the counter 212, and counting is performed in the counter 212 in synchronization with the rise of the input clock signal 213 next to the enable signal.

Since the counter 212 is a decimal counter,
'' to "9", and in accordance with the count value "9", the output from the carry-out terminal CO becomes high level.

The output signal of the counter 211 and the output signal of the counter 212 are input to an AND gate 214.
14 is the carryout of the counter 211 and the counter 2
When all 12 carry-outs are at high level, the output is set at high level.

Therefore, 4007 output signals are obtained from the output terminal of the AND gate 214.

This output signal is then supplied to the input terminal of the D-FF 216.

The D-FF 216 latches the signal supplied from the AND gate 214 in synchronization with the input clock signal 213 (negative logic) and outputs it from the output terminal Q as a reset signal 217.

Therefore, by the frequency dividing operation by the counters 211 and 212, a reset signal 217 having the same frequency as the reference clock signal 215 can be obtained.

ii' The operation of creating the generated clock signal 223 and the generated clock signal 224 when the reference clock signal 215 is normally supplied to Chienari will be explained.

The reset terminal R of the counter 221 has a D-FF 216
Since the reset signal 217 output from
In response to the high level of the reset signal 217, the counting operation of the counter 221 is reset.

When the counting operation is reset, the counter 221 starts the counting operation from the count value "O".

The counting operation in the counter 221 is performed in synchronization with the 64 kHz input clock signal 213 that is input to the clock terminal CK of the counter 221.

Since the counter 221 is a 2-bit counter, it counts from "0pa" to "3", and after "3n" it returns to "0" and continues counting. In addition, in the counting operation of the counter 221, the output from the carry-out terminal CO becomes a noise level in accordance with the count value "3°".
The output from the carry-out terminal CO of 1 is D-FF2
After being latched to 27, it is output as a generated clock signal 223.

Therefore, the input clock signal 213 (frequency 64K) (z
) is divided by the counter 221 (dividing ratio 4) to 16KH.
z's generated clock signal 223 is obtained.

Similarly, a reset signal 217 is supplied to the reset terminal R of the counter 222, and the counting operation is reset in response to the reset signal 217.

When the counting operation is reset, the counter 222 starts counting from the count value "0". Since the counter 222 is a 4-bit counter, it counts from "0" to "F", and the output from the carry-out terminal CO becomes high level in accordance with the count value "F". counter 222
The output from the carry-out terminal CO of the D-FF22
After being latched at 9, it is output as a generated clock signal 224.

Therefore, the input clock signal 213 is frequency-divided by the counter 222 (dividing ratio 16) to generate a 4KHz generated clock signal 2.
Get 24.

Next, the operation of creating the generated clock signal 223 and the generated clock signal 224 when a failure occurs in the operation of supplying the reference clock signal 215 from the outside and the reference clock signal 215 is fixed at a high level. I will explain about it.

When the reference clock signal 215 is fixed at a high level,
A high level signal is always supplied to the reset terminal R of the counter 211, and the counting operation of the counter 211 is stopped. Furthermore, since the counting operation of the counter 212 also stops as the counting operation of the counter 211 stops, the operation of generating the reset signal 217 stops.

When the reset signal 217 is not output from the D-FF 216, the counting operations in the counter 221 and the counter 222 are not reset. However, if the input clock signal 213 is normally supplied to the counters 221 and 222, the counting operations in the counters 221 and 222 continue.

Therefore, the operation of generating the generated clock signals 223 and 224 continues.

■! In this way, while synchronizing with the 400 Hz reference clock signal 215, the 64 KHz input clock signal 21
3 is divided by the counter 211 (dividing ratio 16), and the divided signal of the input clock signal 213 is divided by the counter 212 (dividing ratio 10) to generate a reset signal 217 having the same frequency as the reference clock signal 215. create.

The reset terminal R of the counter 221 has a reset signal 21
7 is supplied, and the counter 221 receives the reset signal 217.
Frequency division of input clock signal 213 synchronized with (frequency division ratio 4)
A generated clock signal 223 of 16 KHz is created by performing the following steps. Similarly, the reset signal 217 is supplied to the reset terminal R of the counter 222, and the counter 222 divides the input clock signal 213 in synchronization with the reset signal 217 (dividing ratio 16) to generate a 4KHz generated clock signal. Create 224.

Therefore, by creating the reset signal °217 having the same frequency as the reference clock signal 215, when a failure occurs in the supply of the reference clock signal 215 and the reference clock signal 215 is fixed at a high level, the counter 22
The generation operation of the generated clock signal 223 and the generated clock signal 224 can be continued 81 times without maintaining the reset state of the 1,222 counting operation.

V, (7) - Note that in the embodiment of the present invention described above, the reset signal 217 having the same frequency as the reference clock signal 215 is created by the two counters 211 and 212; Reset signal 21 by one or more counters
It is also possible to create 7.

In addition, in ``correspondence between Examples and Figure 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, the clock generation circuit generates the clock based on the reset signal created by dividing the input clock signal, so that the clock is generated when the supply of the reference clock signal stops. Since the clock generation operation in the generation circuit can be repeated m times, it is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the operation compensation method of the clock generation circuit of the present invention, FIG. 2 is a block diagram of an embodiment to which the operation compensation method of the clock generation circuit of the invention is applied, and FIG. 3 is a block diagram of the embodiment. Operation timing diagram FIG. 4 is an explanatory diagram of a conventional example. In the figure, 111 is a reset signal generation means, 113 is an input clock signal, 115 is a reference clock signal, 117 is a reset signal, 121 is a clock generation circuit, 123 is a generated clock signal, 211.212, 221.222 are counters, 213 is an input clock signal, 214 is an AND gate, 215 is a reference clock signal, 216, 227, 229 are D-FFs, 217 is a reset signal, 218 is an OR gate, and 223, 224 are generated clock signals.

Claims (1)

[Claims] Input clock signal (113) and reference clock signal (11
5), a reset signal generating means (111) for frequency-dividing the input clock signal (113) to generate a reset signal (117) having the same frequency as the reference clock signal (115); Signal (113)
and said reset signal (117) are introduced, synchronized with said reset signal (117), and said input clock signal (
A clock generation circuit (121) that generates a generated clock signal (123) by frequency-dividing a clock signal (113).