JPH01111318A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH01111318A JPH01111318A JP27081187A JP27081187A JPH01111318A JP H01111318 A JPH01111318 A JP H01111318A JP 27081187 A JP27081187 A JP 27081187A JP 27081187 A JP27081187 A JP 27081187A JP H01111318 A JPH01111318 A JP H01111318A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip
- semiconductor chip
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000011347 resin Substances 0.000 abstract description 29
- 229920005989 resin Polymers 0.000 abstract description 29
- 238000007789 sealing Methods 0.000 abstract description 14
- 230000008646 thermal stress Effects 0.000 abstract description 2
- 238000004299 exfoliation Methods 0.000 abstract 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、樹脂封止型の半導体チップの保持構造を改良
した樹脂封止型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device with an improved holding structure for a resin-sealed semiconductor chip.
従来、この種の樹脂封止型半導体装置は、第５図に示す
如き構造のものが一般的であった。Conventionally, this type of resin-sealed semiconductor device has generally had a structure as shown in FIG.
この従来の樹脂封止型半導体装置は、半導体チップ１を
リードフレーム２のアイランド部６にろう材等の接着材
で固着してｉ！置する。そして、半導体チップｌの電極
パッド（図示せず）とリードフレーム２の先端をＡｕ線
笠のポンディングワイヤ３で結合して電気的接続を図っ
ている。そして、封止金型（図示せず）によって、封止
樹脂４で封止して、外部リードのメツキ処理、リードの
成形をしている。In this conventional resin-sealed semiconductor device, a semiconductor chip 1 is fixed to an island portion 6 of a lead frame 2 using an adhesive such as a brazing material. place Then, the electrode pads (not shown) of the semiconductor chip 1 and the tip of the lead frame 2 are connected with a bonding wire 3 made of an Au wire shade to achieve electrical connection. Then, it is sealed with a sealing resin 4 using a sealing mold (not shown), and the external leads are plated and the leads are molded.
このような従来の樹脂封止型半導体装置は。 Such a conventional resin-sealed semiconductor device.
プリント回路基板への表面実装技術の発展に伴って、半
田部分を急激に加熱させて半田付けを行なう赤外線リフ
ロー装置やベーパフェーズソルダリング装置を使用する
場合が急増している。上記装置による実装では、樹脂封
止型半導体装置は、急激に加熱された封止樹脂４が熱膨
張して、第６図に図示したように、封止樹脂４と半導体
チップ１との接触面において樹脂の密着不良や剥離部分
５が発生し、装置の信頼性に悪影！を及ぼすという問題
があった。With the development of surface mounting technology for printed circuit boards, the use of infrared reflow equipment and vapor phase soldering equipment, which perform soldering by rapidly heating the solder portion, is rapidly increasing. When mounted using the above-mentioned apparatus, the resin-sealed semiconductor device has a structure in which the rapidly heated encapsulating resin 4 thermally expands, and the contact surface between the encapsulating resin 4 and the semiconductor chip 1 as shown in FIG. Poor adhesion of the resin and peeling parts 5 occur, which negatively affects the reliability of the device! There was a problem that it caused
本発明の目的は上記の問題に鑑み、急激に加熱されて封
止樹脂が８膨張しても、封止樹脂が半導体チップの表面
において密着不良や剥離を引き起こさない樹脂封止型半
導体装置を提供するものである。In view of the above problems, an object of the present invention is to provide a resin-sealed semiconductor device in which the sealing resin does not cause poor adhesion or peeling on the surface of a semiconductor chip even when the sealing resin expands due to rapid heating. It is something to do.
本発明の樹脂封止型半導体装置は、半導体チップの底部
周縁に切欠き部を設け、半導体チップの載置部材との接
触面が半導体チップの主面より小ならしめるようにした
ものである。In the resin-sealed semiconductor device of the present invention, a notch is provided at the bottom periphery of the semiconductor chip so that the contact surface of the semiconductor chip with the mounting member is smaller than the main surface of the semiconductor chip.
本発明は、半導体装置の実装の際に熱的ストレスを受け
て１Ｍ封止樹脂変形しても、半導体チップの底部に形成
されている切欠き部に封止樹脂があるため半導体チップ
を上下側方から抱え込むようになっており、封止樹脂が
熱膨張しても、封止樹脂と半導体チップの接触面におい
て密着不良や剥離が発生しない。In the present invention, even if the 1M sealing resin is deformed due to thermal stress during the mounting of the semiconductor device, the semiconductor chip can be placed on the upper and lower sides because the sealing resin is in the notch formed at the bottom of the semiconductor chip. Even if the sealing resin thermally expands, poor adhesion or peeling will not occur at the contact surface between the sealing resin and the semiconductor chip.
以下に１本発明の樹脂封止型半導体装置の実施例を図面
を参照して説明する。第１図〜第２図は、本発明の第１
実施例に関するもので、第１図は本発明の第１実施例の
縦断面図で、第２図は半導体チップを切出すウェーハダ
イシング工程を示す縦断面図である。An embodiment of a resin-sealed semiconductor device of the present invention will be described below with reference to the drawings. Figures 1 and 2 show the first embodiment of the present invention.
FIG. 1 is a longitudinal sectional view of the first embodiment of the present invention, and FIG. 2 is a longitudinal sectional view showing a wafer dicing process for cutting out semiconductor chips.
第１図に示すように、半導体チップ１は底部周縁に切欠
き部１ａが形成されていて、アイランド部６と半導体ペ
レット１とが固着されると、半導体チップ１とアイラン
ド部６との接触面の周縁に凹部が形成される。そして、
半導体素子ｌの電極端子（図示せず）とそれに対応する
リードフレーム２の先端にＡｕ線等のポンディングワイ
ヤ３で結合して電気的接続がなされた後に、封止金型（
図示せず）に樹脂を充填して封止樹脂４を形成する。こ
のとき樹脂は上記切欠き部ｌにも充填される。その後、
外部リードのメツキ処理やリードの成形を行ない、半導
体装置が製作される。この第１実施例によれば、切欠き
部１ａにも樹脂が充填されていて、半導体ペレットｌは
上下および側方から樹脂によって抱え込んだような状態
になる。したがって半導体装置を実装の際の、温度上昇
に対しても、樹脂の密着不良、剥離が生じない。As shown in FIG. 1, the semiconductor chip 1 has a notch 1a formed at the bottom periphery, and when the island part 6 and the semiconductor pellet 1 are fixed, the contact surface between the semiconductor chip 1 and the island part 6 A recess is formed around the periphery. and,
After electrical connection is made by bonding the electrode terminals (not shown) of the semiconductor element 1 and the corresponding tips of the lead frame 2 with bonding wires 3 such as Au wires, a sealing mold (
(not shown) is filled with resin to form a sealing resin 4. At this time, the resin is also filled in the notch l. after that,
A semiconductor device is manufactured by plating the external leads and molding the leads. According to this first embodiment, the notch 1a is also filled with resin, and the semiconductor pellet 1 is held in the resin from above and below and from the sides. Therefore, even when the temperature rises when mounting a semiconductor device, poor adhesion and peeling of the resin do not occur.
次に、第２図に図示したウェーハダイシング工程を示す
縦断面図を参照して、切欠き部１ａ、チップ切断方法を
説明する。Next, the notch portion 1a and the chip cutting method will be described with reference to a longitudinal cross-sectional view showing the wafer dicing process shown in FIG.
半導体ウェーハ７を、真空吸着によって吸引して、支持
台８上に位乙決めしてから裏返しにして固定しておく、
そして、ダイサーブレード９が高速に回転しながら設定
の高さまで下降して、半導体ウェーハ７にダイサーブレ
ード９の切先の形状によってＶ字状溝ｌＯを縦横方向に
形成する。そして、通常のダイサーブレードによって、
Ｖ字状溝ｌＯ内のダイシング位置１１をダイシングして
、本発明の半導体チップが得られる。The semiconductor wafer 7 is suctioned by vacuum suction, placed on the support base 8, and then fixed upside down.
Then, the dicer blade 9 descends to a set height while rotating at high speed, and V-shaped grooves 10 are formed in the vertical and horizontal directions in the semiconductor wafer 7 according to the shape of the cutting tip of the dicer blade 9. Then, with a regular dicer blade,
The semiconductor chip of the present invention is obtained by dicing at the dicing position 11 within the V-shaped groove IO.
次に、切欠き部の形状が異なる第２実施例を第３図を参
照して説明する０図からも明らかなように、この第２実
施例は、切除部１ｂの形状が矩形になっている。切欠き
部１ｂの形状を矩形にすることによって、半導体チップ
ｌの底部に入り込む樹脂量が多くなり、密着不良や剥離
がより一層起こりにくくなる。なお、切欠き部１ｂの矩
形形状の形成は、ダイサーブレード９の切先の形状をか
えれば極めて簡単に形成することができる。Next, a second embodiment in which the shape of the notch portion is different is explained with reference to FIG. 3. As is clear from FIG. There is. By making the shape of the notch 1b rectangular, the amount of resin that enters the bottom of the semiconductor chip 1 increases, making it even more difficult for poor adhesion and peeling to occur. Note that the notch portion 1b can be formed into a rectangular shape extremely easily by changing the shape of the tip of the dicer blade 9.
また、第４図に示した第３実施例は、半導体チップｌの
底面積に等しくなるようにアイランド部６の面積を小さ
くしたもので、半導体チップ１に対する熟的ストレスに
よる内部応力を低下させる利点がある。さらにリードフ
レーム２を半導体チップ１に近く寄せることができるの
で、パッケージの小型化に有効である。Further, the third embodiment shown in FIG. 4 has the area of the island portion 6 reduced so as to be equal to the bottom area of the semiconductor chip 1, which has the advantage of reducing internal stress due to stress on the semiconductor chip 1. There is. Furthermore, since the lead frame 2 can be brought close to the semiconductor chip 1, it is effective in reducing the size of the package.
以上説明したように１本発明の樹脂封止型半導体装こは
、半導体チップの底部に切欠き部を形成することで、封
止樹脂がこの切欠き部に入るようにしている。半導体装
置をプリント回路基板に実装するとき、半導体チップは
封止樹脂の膨張をうけるが切欠き部の樹脂の存在により
上下、側方より抱え込まれているので封止樹脂と半導体
チップ表面とにおいて密着不良や剥離が発生しなくなる
という優れた効果がある。As described above, in the resin-sealed semiconductor device of the present invention, a notch is formed at the bottom of the semiconductor chip, so that the sealing resin enters the notch. When a semiconductor device is mounted on a printed circuit board, the semiconductor chip is subject to expansion of the encapsulating resin, but due to the presence of the resin in the notch, it is held in from above, below, and from the sides, so that the encapsulating resin and the surface of the semiconductor chip are in close contact. This has the excellent effect of preventing defects and peeling.
第１図は本発明の第１実施例の縦断面図、第２図はウェ
ーハダイシング工程を示す縦断面図、第３図は本発明の
第２実施例の縦断面図、第４図は本発明の第３実施例の
縦断面図、第５図は従来例の縦断面図、第６図は従来例
の半導体素子端部の部分縦断面図である。
■・・・半導体チップ、ｌａ、ｌｂ・・・切欠き部、２
・・・リードフレーム、
３・・・ポンディングワイヤ、 ４・・・封止樹脂、６
・・・アイランド部、 ７・・・半導体ウエーノ＼。
９・・・グイサーブレード、 １０・・・７字状溝。
特許出願人 日本電気株□式会社
代理人 弁理士 内 原 音片１図
第２図
第３図
１ａ ５FIG. 1 is a vertical cross-sectional view of the first embodiment of the present invention, FIG. 2 is a vertical cross-sectional view showing the wafer dicing process, FIG. 3 is a vertical cross-sectional view of the second embodiment of the present invention, and FIG. FIG. 5 is a vertical cross-sectional view of a third embodiment of the invention, FIG. 5 is a vertical cross-sectional view of a conventional example, and FIG. 6 is a partial vertical cross-sectional view of an end portion of a semiconductor element of a conventional example. ■...Semiconductor chip, la, lb...notch, 2
... Lead frame, 3... Bonding wire, 4... Sealing resin, 6
...Island part, 7...Semiconductor waeno\. 9... Guisa blade, 10... Figure 7 groove. Patent applicant: NEC Co., Ltd. Representative: Patent attorney Uchihara On piece 1 Figure 2 Figure 3 Figure 1a 5
Claims (1)
ップの載置部材との接触面が半導体チップの主面より小
ならしめたことを特徴とする樹脂封止型半導体装置。1. A resin-sealed semiconductor device, characterized in that a notch is provided at the bottom periphery of the semiconductor chip, so that the contact surface of the semiconductor chip with a mounting member is smaller than the main surface of the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27081187A JPH01111318A (en) | 1987-10-26 | 1987-10-26 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27081187A JPH01111318A (en) | 1987-10-26 | 1987-10-26 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01111318A true JPH01111318A (en) | 1989-04-28 |
Family
ID=17491347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27081187A Pending JPH01111318A (en) | 1987-10-26 | 1987-10-26 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01111318A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5233222A (en) * | 1992-07-27 | 1993-08-03 | Motorola, Inc. | Semiconductor device having window-frame flag with tapered edge in opening |
-
1987
- 1987-10-26 JP JP27081187A patent/JPH01111318A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5233222A (en) * | 1992-07-27 | 1993-08-03 | Motorola, Inc. | Semiconductor device having window-frame flag with tapered edge in opening |
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