KR20010060729A - Semiconductor package and fabrication method - Google Patents
Semiconductor package and fabrication method Download PDFInfo
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- KR20010060729A KR20010060729A KR1019990063145A KR19990063145A KR20010060729A KR 20010060729 A KR20010060729 A KR 20010060729A KR 1019990063145 A KR1019990063145 A KR 1019990063145A KR 19990063145 A KR19990063145 A KR 19990063145A KR 20010060729 A KR20010060729 A KR 20010060729A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000000945 filler Substances 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 10
- 239000011888 foil Substances 0.000 claims description 9
- 239000012212 insulator Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 5
- 238000005429 filling process Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 3
- 239000011810 insulating material Substances 0.000 abstract 2
- 229910000679 solder Inorganic materials 0.000 description 18
- 235000012431 wafers Nutrition 0.000 description 18
- 239000011805 ball Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011806 microball Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로 특히, 금속 리드가 상면에 부착된 절연체로 된 절연 프레임이 칩 상부에서 본딩 패드와 연결되어 밀봉된 구조의 패키지를 웨이퍼 단위 패키지 공정을 실시한 후 칩을 절단하는 방법으로 제조하므로써 그 제조 공정 및 구조가 단순하여 비용이 절감되고 전기적 특성이 향상된 반도체 패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same. In particular, an insulating frame made of an insulator having a metal lead attached thereto is connected to a bonding pad at a top of a chip to perform a wafer-based package process on a sealed package. The present invention relates to a semiconductor package and a method of manufacturing the same, which are manufactured by cutting, thereby simplifying the manufacturing process and structure thereof, thereby reducing costs and improving electrical characteristics.
반도체소자가 고집적화 됨에 따라, 개별적인 칩 단위로 절단되는 반도체 칩의 크기도 점점 소형화 되어가는 추세이다. 소형화된 반도체 칩을 이용하여 반도체 패키지 제조 시에는 패키지 크기가 작은 칩 스케일 패키지(Chip Scale Package;이하 CSP라 약칭)타입이 적합하다.As semiconductor devices are highly integrated, the size of semiconductor chips cut into individual chip units is also becoming smaller. When manufacturing a semiconductor package using a miniaturized semiconductor chip, a chip scale package (hereinafter, abbreviated as CSP) type having a small package size is suitable.
CSP는 반도체부품의 실장면적을 가능한 한 칩 크기로 소형화하려는 기술을 말하는데 칩 크기 대비 패키지 면적이 1.2배 이하인 초소형, 초경량 구조의 패키지 형태이다.CSP refers to a technology for minimizing the mounting area of semiconductor components to the chip size as much as possible. It is a package type of ultra small and light structure having a package area of 1.2 times less than the chip size.
u-BGA(Micro-Ball Grid Array) 패키지 구조는 현재 미국 TESSERA 사에서 제조특허를 보유한 형태로서 CSP의 대표적인 구조이다.The u-BGA (Micro-Ball Grid Array) package structure is a type of CSP, which is a type of patent currently owned by TESSERA in the US.
도 1a는 종래기술에 따른 CSP 형인 u-BGA 패키지의 단면도이다.Figure 1a is a cross-sectional view of a u-BGA package of the CSP type according to the prior art.
u-BGA 패키지의 구조는 다수개의 본딩 패드(8)가 형성된 반도체 칩(1)과, 칩 상에 부착되는 절연 완충제(2)와, 다수개의 관통홀(7)이 형성된 솔더 마스크(solder mask)(4)와, 솔더 마스크 상의 관통 홀(7)상에 부착되는 솔더 볼(solder ball)(6)과, 반도체 칩(1)과 솔더 마스크(4)에 개재되어, 일측이 TAB 테이프(Tape Automatic Bonding - tape)(3)의 리드 배선과 연결되고 타측은 반도체 칩(1) 상의 다수개의 본딩 패드(8)와 연결되는 본딩 리본(3-1)과, 솔더 볼(6)이 부착된 솔더마스크(4) 사이의 관통 홀(7)을 제외한 솔더 마스크 하측의 본딩 리본(3-1) 주변과 반도체 칩(1)의 측면 전체 공간을 채워 밀봉시키는 충전재(5)로 구성된다.The structure of the u-BGA package includes a semiconductor chip 1 having a plurality of bonding pads 8, an insulating buffer 2 attached to the chip, and a solder mask having a plurality of through holes 7 formed therein. (4), a solder ball (6) attached to the through hole (7) on the solder mask, the semiconductor chip (1) and the solder mask (4) are interposed, and one side is TAB tape (Tape Automatic) Bonding ribbon 3-1 connected to the lead wiring of the bonding-tape 3 and connected to the plurality of bonding pads 8 on the semiconductor chip 1, and a solder mask to which the solder balls 6 are attached. It consists of the filler 5 which fills and seals around the bonding ribbon 3-1 of the lower side of the solder mask except the through-hole 7 between (4), and the whole side space of the semiconductor chip 1.
솔더 마스크에 형성된 관통 홀(7)을 통해 솔더 볼(6)과 TAB 테이프(3)상의 리드 배선이 연결되어 전기 신호가 전달된다.Through holes 7 formed in the solder mask are connected to the solder balls 6 and the lead wires on the TAB tape 3 to transmit electrical signals.
또, 본딩 리본은 내부에 리드 배선이 형성된 TAB 테이프(3)로부터 추출해 낸 리드를 이용하여 형성한다. 테이프의 접착성에 의해 솔더 마스크 (4)상의 관통 홀(7)을 통해 솔더 볼(6)이 부착될 수있다.Moreover, the bonding ribbon is formed using the lead extracted from the TAB tape 3 in which the lead wiring was formed inside. By the adhesiveness of the tape, the solder balls 6 can be attached through the through holes 7 on the solder mask 4.
상기 구성을 갖는 종래의 CSP 타입인 u-BGA 패키지의 제작과정을 설명한다.A manufacturing process of a u-BGA package, which is a conventional CSP type having the above configuration, will be described.
도 1b 내지 도 1e는 u-bga 패키지의 제작 공정을 순서대로 나열한 공정도이다.1B to 1E are process diagrams sequentially arranging a manufacturing process of a u-bga package.
도 1b를 참조하면 웨이퍼를 칩 단위로 절단하여 패키징(Packaging)할 반도체 칩(1)을 준비한 후, 리드 배선이 형성되어 있는 TAB(tape automated bonding) 테이프(3)에 절연 완충제(2)를 접합시킨 다음 칩을 열 압착방식으로 절연 완충제(2)에 부착한다.Referring to FIG. 1B, after preparing a semiconductor chip 1 to be packaged by cutting a wafer into chips, an insulating buffer 2 is bonded to a tape automated bonding (TAB) tape 3 on which lead wires are formed. Then, the chip is attached to the insulating buffer (2) by thermal compression.
도1c를 참조하면 칩(1) 상의 절연 완충제(2)에 부착된 TAB 테이프(3) 내에 형성된 자체 리드 배선으로부터 리드 배선일부를 추출하여 칩 상에 형성된 본딩 패드(8)에 접착하여 TAB 테이프의 리드 배선과 본딩 패드(8)를 전기적으로 연결시키는 본딩 리본(3-1)을 형성하는 본딩리본 형성 공정이 이루어진다.Referring to FIG. 1C, a part of the lead wire is extracted from the self lead wire formed in the TAB tape 3 attached to the insulating buffer 2 on the chip 1, and is bonded to the bonding pad 8 formed on the chip. A bonding ribbon forming step of forming a bonding ribbon 3-1 electrically connecting the lead wires and the bonding pads 8 is performed.
도 1d를 참조하면 본딩 리본 형성 공정이 완료되면 TAB 테이프(3) 상에 관통 홀(7)이 형성된 솔더 마스크(Solder Mask)(4)를 접착시킨 후 솔더 마스크 하측에 형성된 본딩 패드(8)와 TAB 테이프(3)를 연결하고있는 본딩 리본(3-1) 및 칩(1) 등을 외부물리적 화학적 충격으로부터 보호하기 위해 충전재(5)를 사용하여 밀봉한다.Referring to FIG. 1D, when the bonding ribbon forming process is completed, a solder mask 4 having a through hole 7 is formed on the TAB tape 3 and then a bonding pad 8 formed below the solder mask. In order to protect the bonding ribbon 3-1, the chip 1, and the like connecting the TAB tape 3 from external physical and chemical shocks, the filler 5 is sealed.
도 1e를 참조하면 밀봉이 끝난 후 솔더 마스크(4) 사이의 관통 홀(7)을 통해 TAB 테이프(3)상에 솔더 볼(6)을 부착하여 TAB 테이프(3) 내의 리드 배선과 연결 하므로써 패키지 내부 회로를 솔더 볼(6)을 통해 외부로 연결한다. 이후, 서로 연결되어 있는 패키지들를 하나씩 분리시키는 싱귤레이션(Singulation) 공정에 의해 패키지가 완성된다.Referring to FIG. 1E, after the sealing is completed, the solder balls 6 are attached onto the TAB tape 3 through the through holes 7 between the solder masks 4 and the package is connected to the lead wires in the TAB tape 3. The internal circuit is connected to the outside via solder balls (6). Thereafter, the package is completed by a singulation process of separating the packages connected to each other one by one.
하지만 종래의 기술에서는 본딩리본 형성공정시 고도의 기술이 필요하여 불량 발생률이 높고, 공정이 복잡하며 도전 패턴으로 사용되는 TAB 테이프가 고가이므로 많은 제조 비용 및 시간이 소모되며 칩의 전기적 경로가 본딩 패드,본딩 리본, 테이프 내의 리드배선, 솔더볼 등의 순서로 복잡하여 전기적 특성이 좋지 않은 점등의 문제점과 패키지 제조시 칩 단위로 제조되므로 대량 생산이 어렵다는 문제점등이 있었다.However, in the conventional technology, a high rate of technology is required in the process of forming a bonding ribbon, and thus a high incidence of defects, a complicated process, and a high cost of TAB tape used as a conductive pattern consume a lot of manufacturing cost and time. In the order of bonding ribbon, lead wiring in the tape, solder balls, etc., the electrical properties are poor, and there is a problem in that the mass production is difficult because the chips are manufactured in units of packages.
따라서 본 발명은 금속 리드가 상면에 부착된 절연체로 된 절연 프레임이 칩 상부에서 본딩 패드와 연결되어 밀봉된 구조의 패키지를 웨이퍼 단위 패키지 공정을 실시한 후 칩을 절단하는 방법으로 제조하므로써 구조및 제조 공정이 단순하며 제조 비용이 저렴하고 전기적 특성이 좋고, 대량 생산이 용이한 패키지를 제공하는데 그 목적이 있다.Therefore, the present invention is a structure and manufacturing process by manufacturing a package of a structure in which an insulating frame made of an insulator attached to the upper surface of the metal lead is connected to the bonding pads on the top of the chip, and then cutting the chip after performing a wafer unit package process. Its purpose is to provide a package that is simple, inexpensive to manufacture, has good electrical properties and is easy to mass produce.
상술한 목적을 달성하기위한 본 발명의 기술적 수단은 다수 개의 입출력 본딩 패드가 상부에 형성된 반도체 칩과, 반도체 칩 상부에 실장 되며 상측은 다수개의 금속 리드로 되고 하측은 절연체로 된 절연 프레임과, 다수개의 금속 리드 일측과 반도체 칩 상의 다수개의 입출력 본딩 패드를 각각 연결하여 전기적 신호교환이 가능하게 하는 다수개의 전도성 연결수단과, 절연 프레임을 틀로하여 반도체 칩 상부에서 절연 프레임 사이의 홀을 밀봉시키는 충전재를 포함하여 구성되고, 다수개의 금속리드의 본딩 패드와 연결되지 않은 부분은 패키지 외부로 일부 노출되어 연결할 수 있게 된 것이 특징이다. 이러한 구조의 반도체 패키지의 제조 방법은 상면에 다수개의 금속 리드를 가진 절연체의 중앙에 홀이 형성된 다수의 절연 프레임을 다수개의 반도체 칩이 형성된 웨이퍼 상에 부착하는 공정과, 반도체 칩 상에 형성된 다수개의 본딩 패드와 다수개의 금속리드의 일측을 연결하는 와이어 본딩하는 공정과, 웨이퍼의 상면으로부터 절연 프레임 상면까지의 홀을 액상의 충전재로 충전하는 충전 공정과, 충전 공정이 끝난 웨이퍼 후면에 웨이퍼 절단을 위한 접착성 포일을 붙이는 공정과, 접착성 포일이 부착된 웨이퍼를 절단 날(Saw Blade)을 이용하여 낱개의 칩 단위로 절단하고 칩 후면의 포일을 제거하는 공정을 포함하여 이루어진 것이 특징이다.Technical means of the present invention for achieving the above object is a semiconductor chip formed with a plurality of input and output bonding pads on the upper side, an insulating frame made of a plurality of metal leads on the upper side and an insulator on the lower side, A plurality of conductive connecting means for connecting electrical signals to one side of each of the metal leads and a plurality of input / output bonding pads on the semiconductor chip to enable electrical signal exchange, and a filler for sealing a hole between the insulating frames on the upper side of the semiconductor chip using the insulating frame. It is configured to include, and the portion of the plurality of metal leads that are not connected to the bonding pad is exposed to the outside of the package is characterized in that it can be connected. A method of manufacturing a semiconductor package having such a structure includes attaching a plurality of insulating frames having holes formed in the center of an insulator having a plurality of metal leads on an upper surface thereof, on a wafer on which a plurality of semiconductor chips are formed, and a plurality of formed on the semiconductor chips. Wire bonding process connecting the bonding pads with one side of the plurality of metal leads, a filling process for filling holes from the top surface of the wafer to the top surface of the insulating frame with a liquid filler, and a wafer cutting process for the wafer backside And a step of attaching the adhesive foil, and a step of cutting the wafer on which the adhesive foil is attached by a single chip unit using a saw blade and removing the foil on the back surface of the chip.
도 1a는 종래기술에 따른 CSP 형인 u-BGA 패키지의 단면도.1A is a cross-sectional view of a u-BGA package of CSP type according to the prior art;
도 1b 내지 도 1e는 u-BGA 패키지의 제작 공정을 순서대로 나열한 공정도.1B to 1E are process diagrams sequentially listing manufacturing processes of a u-BGA package.
도 2a는 본 발명에 의한 반도체 패키지의 단면도.2A is a cross-sectional view of a semiconductor package according to the present invention.
도 2b는 본 발명에 의한 반도체 패키지의 평면도.2B is a plan view of a semiconductor package according to the present invention.
도 2c는 본 발명에의한 반도체 패키지의 절연 프레임 평면도.Figure 2c is a plan view of an insulating frame of a semiconductor package according to the present invention.
도 3a 내지 도 3e는 본 발명의 반도체 패키지를 제조하는 공정을 설명한 공정 순서도.3A to 3E are process flow charts illustrating a process of manufacturing a semiconductor package of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11:웨이퍼 11-1:반도체 칩 12:절연 프레임11: Wafer 11-1: Semiconductor chip 12: Insulation frame
13:포일 14:와이어13: Foil 14: Wire
15:충전재 18:본딩 패드 20:충전재 주입기15: Filler 18: Bonding pad 20: Filler injector
21:와이어 본딩기 22:절단 날21: Wire bonding machine 22: Cutting day
이하 첨부된 도면을 참조하여 본 발명의 반도체 패키지를 설명한다.Hereinafter, a semiconductor package of the present invention will be described with reference to the accompanying drawings.
도 2a는 본 발명에 의한 반도체 패키지의 단면도이고, 도2b는 본 발명에 의한 반도체 패키지의 평면도이며, 도 2c는 본 발명에의한 반도체 패키지의 절연 프레임 평면도이다.2A is a cross-sectional view of a semiconductor package according to the present invention, FIG. 2B is a plan view of a semiconductor package according to the present invention, and FIG. 2C is a plan view of an insulating frame of the semiconductor package according to the present invention.
본 발명에 의한 반도체 패키지는 다음과 같은 구성을 가진다.The semiconductor package according to the present invention has the following configuration.
반도체 칩(11-1) 상면에 형성된 다수개의 본딩 패드(18)에 의해 칩 내부 회로의 전기신호가 외부로 출력 되거나 외부의 전기신호가 칩 내부로 들어올 수 있다.The plurality of bonding pads 18 formed on the upper surface of the semiconductor chip 11-1 may output the electrical signal of the internal circuit of the chip to the outside or the external electrical signal may enter the inside of the chip.
또, 반도체 칩(11-1) 상부에는 상면에 다수개의 금속 리드(12-1)가 부착된 접착성을 가지는 절연체(12-2)로되고 중앙에 홀(hall)(12-3)이 형성되어 있는 절연 프레임(12)이 부착되어 있다. 다수개의 금속 리드(12-1) 각각의 하단 일측은 홀(12-3)을 통해 칩 상면에 형성된 다수개의 본딩 패드(18)와는 다수개의 와이어(14)에 의해 각각 연결되어 있어 금속 리드(12-1)와 반도체 칩(11-1) 내부와의 전기적 신호 교환을 가능하게 한다.The upper surface of the semiconductor chip 11-1 is an insulator 12-2 having an adhesive property with a plurality of metal leads 12-1 attached to the upper surface thereof, and a hole 12-3 is formed in the center thereof. An insulating frame 12 is attached. One lower end of each of the plurality of metal leads 12-1 is connected to the plurality of bonding pads 18 formed on the upper surface of the chip through the holes 12-3 by a plurality of wires 14, respectively. -1) and electrical signal exchange between the inside of the semiconductor chip 11-1.
그리고, 칩(11-1) 상면에서 절연 프레임(12) 상측까지의 홀(12-3) 내에는 충전 물질(15)이 밀봉되어 외부의 물리적, 화학적 충격으로부터 칩과 와이어 및 리드등을 보호한다.In addition, the filling material 15 is sealed in the hole 12-3 from the upper surface of the chip 11-1 to the upper side of the insulating frame 12 to protect the chip, wires, and leads from external physical and chemical shocks. .
절연 프레임(12) 상측에 형성된 다수개의 금속 리드(12-1)는 본딩 패드(18)와 연결되지 않은 부분이 패키지 외부로 다소 노출되어 외부 도전체와 연결 되므로써 패키지 내부와 외부간의 전기 연결을 가능하게 한다.The plurality of metal leads 12-1 formed on the insulating frame 12 may be electrically connected to an external conductor by exposing portions of the metal pad 12-1 that are not connected to the bonding pads 18 to the outside of the package to be connected to an external conductor. Let's do it.
이때, 금속 리드(12-1)의 성분은 납과 주석 합금으로 구성되며 계단형으로 굴곡된 형상을 가져 굴곡 상부가 패키지 외부로, 하부가 패키지 내부의 와이어로 연결된다.At this time, the component of the metal lead (12-1) is composed of lead and tin alloy has a curved shape stepped, the upper part of the bent is connected to the outside of the package, the lower part is connected by a wire inside the package.
절연 프레임(12) 상의 금속 리드(12-1)와 본딩 패드(18)를 연결하는 와이어로는 골드 와이어(Gold Wire)(14)를 사용한다. 따라서, 본 발명에 의한 구성을 가진 패키지가 내부 전기신호를 외부로 출력 및 외부 신호를 내부로 입력할 때는 본딩패드(18), 골드 와이어(14), 금속 리드(12-1) 또는 그 역순의 전기적 연결 경로를 가진다. 따라서, 본딩 패드,본딩 리본, TAB 테이프 내의 리드 배선, 솔더볼의 전기적 연결 경로를 가지는 종래 기술의 반도체 패키지 보다 그 경로가 더 짧다.A gold wire 14 is used as a wire connecting the metal lead 12-1 and the bonding pad 18 on the insulating frame 12. Therefore, when the package having the structure according to the present invention outputs the internal electric signal to the outside and inputs the external signal to the inside, the bonding pad 18, the gold wire 14, the metal lead 12-1, or the reverse order thereof. Has an electrical connection path Thus, the path is shorter than the prior art semiconductor packages having bonding pads, bonding ribbons, lead wirings in TAB tape, and electrical connection paths of solder balls.
도 3a 내지 도 3e 까지는 본 발명의 반도체 패키지를 제조하는 공정을 설명한 공정 순서도이다.3A to 3E are flowcharts illustrating a process of manufacturing the semiconductor package of the present invention.
도3a 에서와 같이 노광 공정이 끝나 칩이 형성된 웨이퍼(11) 상에 절연 프레임(12)을 부착한다. 절연 프레임(12)은 상술한 대로 상면에 다수개의 금속 리드(12-1)가 형성된 접착성을 가지는 절연체(12-2)로 되어 다수의 홀(12-3)이 형성되어 있어 웨이퍼(11) 상에 접착을 용이하게 하며 칩(11-1)과의 전기적 절연 작용 및 충전시 틀체 역할을 한다.As shown in FIG. 3A, the insulating frame 12 is attached to the wafer 11 on which the chip is formed after the exposure process is completed. As described above, the insulating frame 12 is an insulator 12-2 having an adhesive having a plurality of metal leads 12-1 formed on the upper surface thereof, and a plurality of holes 12-3 are formed to form a wafer 11. It facilitates adhesion to the phase and serves as a framework for electrical insulation and charging with the chip (11-1).
웨이퍼(11) 상에 절연 프레임(12) 부착이 끝나면 도3b 에서와 같이 기존의 와이어 본드 툴(Wire-Bond tool) (21)을 그대로 이용하여 와이어(14)를 다수개의 본딩 패드(18)와 절연 프레임(12)에 형성된 다수개 금속 리드(12-1)의 굴곡 하부 일측에 접합하여 연결한다. 와이어로는 골드 와이어(Gold Wire)(14)를 사용하며 초음파에 의한 마찰열, 압력 그리고 일정온도의 열등을 사용하여 골드 와이어를 접합하는 열 압착 방식으로 금속 리드(12-1) 및 본딩 패드(18)상에 접합한다. 이 외에 고주파를 이용한 마찰열과 압력에의한 고주파 압착방식등을 사용할 수도 있다. 상술한 공정을 와이어 본딩 공정이라 한다.After the insulation frame 12 is attached to the wafer 11, the wire 14 is connected to the plurality of bonding pads 18 using the existing wire-bond tool 21 as shown in FIG. 3B. A plurality of metal leads 12-1 formed on the insulating frame 12 are joined to and connected to one side of the bent bottom side. Gold wire (14) is used as the wire, and the metal leads 12-1 and the bonding pads 18 are thermally crimped to bond the gold wire using friction heat, pressure, and constant temperature inferiority by ultrasonic waves. ) To the phase. In addition, high frequency friction heat using high frequency and high frequency crimping by pressure may be used. The above-mentioned process is called a wire bonding process.
골드 와이어(14)에 의해 본딩 패드(18)와 금속 리드(12-1)가 연결되면 도3c 에서와 같이 충전 공정이 시작된다. 이때, 따로 충전을 위한 금형을 사용하지 않고 절연프레임(12)에 형성된 홀(12-3)을 틀체(??) 로하여 액상의 충전재(15)를 이용하여 웨이퍼(11) 상면을 저면으로 한 절연 프레임(12)의 금속 리드(12-1)높이 까지의 홀(12-3)을 에폭시수지 등의 물질로 된 액상 충전재(15)가 내재된 주입기(20)를 사용하여 충전한다. 충전이 끝난 웨이퍼는 베이크 오븐(Bake Oven)을 이용하여 충전재를 경화한다.When the bonding pad 18 and the metal lead 12-1 are connected by the gold wire 14, the charging process starts as shown in FIG. 3C. At this time, the hole 12-3 formed in the insulating frame 12 is used as a frame (??) without using a mold for filling, and the upper surface of the wafer 11 is bottomed using the liquid filler 15. The hole 12-3 up to the height of the metal lead 12-1 of the insulating frame 12 is filled using the injector 20 in which the liquid filler 15 made of a material such as epoxy resin is embedded. After filling, the wafer is baked using a bake oven.
충전재가 경화되고, 상부의 모든 실장이 끝난 웨이퍼는 도3d 에서와 같이 칩 단위로 절단하기 위해 웨이퍼(11) 후면에 접착성 포일(13)을 붙인 후 절단 날(Saw Blade)(22)등을 이용하여 낱개의 칩(11-1) 단위로 절단하고 칩 후면의 포일(13)을 제거 하므로써 본 발명에 의한 반도체 패키지가 완성된다.The filler is cured, and all the mounted wafers on top are attached with an adhesive foil 13 on the back side of the wafer 11 in order to cut chip by chip, as shown in FIG. 3d, and then saw blades 22 and the like. The semiconductor package according to the present invention is completed by cutting the single chip 11-1 by using each unit and removing the foil 13 on the rear surface of the chip.
즉, 본 발명에서는 웨이퍼 전체에 각 공정을 수행한 후 모든 작업이 종료되면 칩 단위로 절단하여 분리하는 방법을 이용한다.That is, in the present invention, after performing each process on the entire wafer, when all the work is completed, a method of cutting and separating by chip unit is used.
이상에서 설명한 바와 같이 본 발명은 본딩 패드와는 전도성 연결수단에 의해 연결되어 외부로의 전기신호 입출을 가능하게 하며, 충전시는 금형을 대신하여 사용되는 홀이 형성되고, 칩에 접착되어 칩을 충격으로 보호하는 다양한 기능을 가진 절연 프레임을 사용하므로써 제조 공정 및 칩 구조를 단순화 하여 제조 비용 및 시간을 절약하고, 칩의 전기적 경로를 줄여 전기적 특성을 좋게하고,As described above, the present invention is connected to the bonding pad by a conductive connecting means to enable the input and output of electrical signals to the outside, and during charging, holes used in place of the mold are formed, and are bonded to the chip to form a chip. By using an insulating frame with various functions to protect against impact, the manufacturing process and chip structure can be simplified, saving manufacturing cost and time, and reducing the electrical path of the chip to improve electrical characteristics.
웨이퍼 단위로 패키지 제조 공정이 진행된 후 마지막 단계에서 칩 단위로 절단되는 제조 방법을 사용하기 때문에 칩의 생산능력이 증대되어 대량생산이 용이하며 싱귤레이션 공정을 생략하므로 공정이 줄어들고,Since the package manufacturing process is carried out in wafer units and then used in the last step, the manufacturing method is cut into chips, so the production capacity of the chips is increased and mass production is easy, and the process is reduced because the singulation process is omitted.
작업이 난해한 본딩 리본 형성 공정 대신 상대적으로 작업이 용이한 와이어 본딩 공정으로 대체되므로 공정 진행이 용이해진 반도체 패키지 및 제조 방법을 제공하는 효과를 가진다.Since the work is replaced by a wire bonding process, which is relatively easy to work, instead of a difficult process of forming a bonding ribbon, there is an effect of providing a semiconductor package and a manufacturing method which are easily processed.
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| KR1019990063145A KR100348862B1 (en) | 1999-12-28 | 1999-12-28 | Method for fabricating Semiconductor package |
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|---|---|---|---|
| KR1019990063145A KR100348862B1 (en) | 1999-12-28 | 1999-12-28 | Method for fabricating Semiconductor package |
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| KR100348862B1 KR100348862B1 (en) | 2002-08-17 |
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| CN110285125A (en) * | 2019-05-17 | 2019-09-27 | 杭州戬威机电科技有限公司 | The adhered probe encapsulation of one kind and intelligent bolt |
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| JP3163961B2 (en) * | 1995-09-22 | 2001-05-08 | 日立電線株式会社 | Semiconductor device |
| KR100248023B1 (en) * | 1996-02-15 | 2000-05-01 | 윤종용 | Super resolution optical pickup for various type disc |
| KR100221918B1 (en) * | 1996-12-30 | 1999-09-15 | 윤종용 | Chip scale package |
| KR19990060455A (en) * | 1997-12-31 | 1999-07-26 | 구본준 | Semiconductor Chip Size Package |
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| CN110285125A (en) * | 2019-05-17 | 2019-09-27 | 杭州戬威机电科技有限公司 | The adhered probe encapsulation of one kind and intelligent bolt |
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