JPH01109816A - Integrated circuit device using complementary semiconductor - Google Patents

Abstract

PURPOSE:To reduce the scale of the circuit and to decrease the delay time by providing complementary pair transistors(TRs) connected in series with drains connected in common between a power supply and ground and complementary pair TRs connected in series with sources connected in common. CONSTITUTION:A single phase clock inputted to a clock input terminal 1 is inverted by a PMOSFET 2 and an NMOSFET 4 connected in series between the power supply and ground with drains connected in common and inputted to a buffer inverter circuit 6a. On the other hand, a single phase clock inputted from the clock input terminal 1 is given to an NMOSFET 4 and a PMOSFET 5 connected between the power supply and ground in series with sources connected in common without inversion. Thus, in selecting the characteristic of the PMOSFETs 2, 5 and the NMOSFETs 3, 4 properly, clocks whose phases are deviated just by 180 deg. are obtained from output terminals 7a and 7b.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a complementary semiconductor integrated circuit device that can obtain positive and negative two-phase clock pulses with, for example, a phase difference of 180°.

(Prior Art) FIG. 3 is a diagram showing a clock shaping circuit for obtaining a positive and negative two-phase clock with a phase difference of 1800 from a one-phase clock signal, as described in, for example, Japanese Patent Publication No. 61-7773. be.

In the figure, 11 is a clock input terminal, 12a, 12b
is a phase correction inverter circuit whose driving ability is corrected to generate positive and negative two-phase clock pulses with a phase difference of 180°. 13a.

13b is the phase correction inverter circuit 12a.

12m), and 14a and 14b are output terminals of the buffer inverter circuit connected to the output of the buffer inverter circuit 12m).

Next, the operation will be explained.

After the one-phase clock input from the clock input terminal 11 is branched, it passes through phase correction inverter circuits 12a and 12b whose number of stages and drive capacity are changed in order to obtain a positive and negative two-phase clock. , the phases of the respective clocks are corrected based on the difference in delay time due to the difference in the number of stages, and the clocks pass through the buffer inverter circuits 13a, 13b to reach the output terminals 14a, 14b.

[Problem that the invention seeks to solve]

In the conventional complementary semiconductor integrated circuit device as described above, three or more inverters are used to obtain positive and negative two-phase clocks.
That is, at the transistor level, it is necessary to add at least six transistors or more, which increases the size of the circuit. Moreover, since there are four stages of gates until a signal inputted manually is output, there is a problem in that there is a long delay time from when the signal is inputted manually until the signal is output.

The present invention was made to solve these problems, and an object of the present invention is to obtain a complementary semiconductor integrated circuit device that can obtain positive and negative two-phase clocks with a phase difference of 180° using a small number of transistors. .

[Means for solving problems]

A complementary semiconductor integrated circuit device according to the present invention is connected in series with a common drain electrode between a power source and a ground,
a first pair of complementary pairs whose gate electrodes are connected to the input terminals;
and a second transistor, and third and fourth transistors forming a complementary pair connected in series with a common source electrode between the power supply and ground, and having gate electrodes connected to the input terminal. be.

(Operation) In the present invention, a signal that is substantially the inversion of the human input signal is output from the drain electrodes of the first transistor and the second transistor, and a signal that is substantially the inverse of the human input signal is output from the source electrodes of the third transistor and the fourth transistor. Signals having substantially the same phase are output, and as a result, two-phase signals with a phase difference of 180° are obtained.

〔Example〕

FIG. 1 is a diagram showing the configuration of an embodiment of a complementary semiconductor integrated circuit device of the present invention.

In this figure, 1 is a clock input terminal, 2 is a P-channel metal/oxide film/semiconductor field effect transistor (hereinafter abbreviated as PMO-5FET) as a first transistor whose gate electrode is connected to the clock input terminal 1; 3 is a second gate electrode whose gate electrode is connected to the clock input terminal 1;
4 is an N-channel metal/oxide film/semiconductor field effect transistor (hereinafter abbreviated as NJO5FET) as a transistor, and 4 is an NMO5FET as a third transistor whose gate electrode is connected to the clock input terminal 1.
5 is a PMO5FET as a fourth transistor whose gate electrode is connected to the clock input terminal 1;
a is the drain electrode of the PMO5F-ET2 and the NM
A buffer inverter circuit in which the drain electrode of O5FET 3 is connected to the input terminal, 6b is the NMO5FET
A buffer inverter circuit 7a in which the source electrode of the PMO5FET 5 and the source electrode of the PMO5FET5 are connected to an input terminal.
, 7b are output terminals of the buffer inverter circuits 6a, 6b.

Next, the operation will be explained.

The one-phase clock input to the clock input terminal 1 is inverted by the PMO5FET2 and NMO5EET3 connected in series with a common drain electrode between the power supply and the ground, and inputted to the buffer inverter circuit 6a. After being inverted by the buffer inverter circuit 6a, a clock whose phase is slightly shifted from the input clock due to the delay is outputted to the output terminal 7a.

On the other hand, in the 8MO5FET4 and PMO5FET5 connected in series between the power supply and the ground with a common source electrode, the one-phase clock inputted from the clock input terminal 1 is inputted to the buffer inverter circuit 6b without being inverted. After being inverted by the buffer inverter circuit 6b, the phase of the input clock is 1 due to the delay.
A clock slightly shifted from 800 is output to the output terminal 7b.

i.e. PMO5FET2,5 and NMO5FE
T3.

If the characteristics of 4 are selected appropriately, the output terminal 7a.

A clock whose phase is shifted by exactly 180° from 7b is obtained.

The difference in the load applied to the output terminals 7a and 7b can be adjusted by the difference in the capacity of the buffer inverter circuits 6a and 6b, or by using the same capacity and providing a dummy load (not shown). It is also possible to do so.

Further, FIG. 2 is a diagram showing the configuration of another embodiment of the complementary semiconductor integrated circuit device of the present invention.

In this figure, the same reference numerals as in FIG.
It is connected to the drain electrode of T3, and its drain electrode and source electrode are connected to the source electrode and drain electrode of NMO5FET4, respectively. 9 is an NMO5FET as the sixth transistor, whose gate electrode is PMO.
It is connected to the drain electrodes of 5FET5 and NMO5FET3, and the drain electrode and source electrode are PM respectively.
It is connected to the source electrode and drain electrode of O5FET5.

The basic operation of this embodiment is the same as that of the above embodiment, but in this embodiment, NMO3FET4 and PM
The potential which has dropped by the threshold portion by O5FET5 is raised to the same level as the power supply or ground by PMO5FET8 and NMO5FET9, and then input to the buffer inverter circuit 6b.

〔Effect of the invention〕

As described above, the present invention includes first and second transistors that form a complementary pair, which are connected in series with a common drain electrode between a power source and a ground, and whose gate electrodes are connected to an input terminal; The third and fourth transistors are connected in series with a common source electrode between them, forming a complementary pair with the gate electrode connected to the input terminal, so that the circuit can be configured with a minimum of four transistors. This has the advantage that the delay time from when a signal is input to when it is output is small.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of one embodiment of the complementary semiconductor integrated circuit device of the present invention, FIG. 2 is a diagram showing the configuration of another embodiment of the invention, and FIG. 3 is a diagram showing the configuration of a conventional clock shaping circuit. FIG. In the figure, 1 is the clock input terminal, 2.5°8 is the PM
O5FET, 3.4.9 is NMO5FET, 6 a
. 6b is a buffer inverter circuit, and 7a and 7b are output terminals. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 1: Clock input terminal 'ta, Vb - output leakage

Claims (2)

[Claims] (1) First and second transistors forming a complementary pair, connected in series with a common drain electrode between the power supply and ground, and whose gate electrode is connected to the input terminal, and a source electrode connected between the power supply and ground. 1. A complementary semiconductor integrated circuit device comprising a complementary pair of third and fourth transistors that are commonly connected in series and have gate electrodes connected to the input terminal. (2) The third and fourth transistors have drain electrodes and source electrodes, and gate electrodes are connected to the first and second transistors.
Claim (1), characterized in that the source electrodes and drain electrodes of the fifth and sixth transistors forming a complementary pair connected to the drain electrode of the transistor are respectively connected to each other. Complementary semiconductor integrated circuit device.