JP2001060860A - Inverter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter circuit which greatly improves breakdown voltage and also improve its reliability without changing its process or sacrificing the operation of a transistor. SOLUTION: In shift transistor having its single unit transfer circuit consisting of circuit blocks 1-3 and defining a CMOS inverter circuit as its basic constitution, for example, the PMOS transistors Tr mp6, mp7 and mp8 connected together via diodes are placed in series at the power supply side together with the NMOS Tr mn6, mn7 and mn8 connected together via diodes placed in series at the ground side respectively to a 1st CMOS inverter 1a consisting of a PMOS Tr mp1 and an NMOS Tr mn1, a 2nd CMOS inverter 2a consisting of a PMOS Tr mp3 and an NMOS Tr mn3 and a 3rd CMOS inverter 3a consisting of the source of a PMOS Tr mp5 and an NMOS Tr mn5, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter circuit, and more particularly, to an inverter circuit formed by a thin film transistor (TFT).

[0002]

2. Description of the Related Art For example, a shift register is used as a circuit for holding a signal generated by a certain circuit for a predetermined period or delaying the signal for a predetermined period and outputting it to a next circuit. I have.

FIG. 3 is a circuit diagram showing an example of a conventional shift register. This circuit includes a first transistor composed of a PMOS transistor mp1 and an NMOS transistor mn1.
CMOS inverter and PMOS transistor mp3
CMO composed of an NMOS transistor mn3
S inverter, PMOS transistor mp5 and NMO
A third CMOS inverter including the S transistor mn5 is provided.

[0004] Of the CMOS inverters, the third CMO
In the S inverter, the source of the PMOS transistor mp5 and the source of the NMOS transistor mn5 are connected to the power supply VD
D and ground GND, respectively.

On the other hand, in the first and second CMOS inverters, PMOS transistors mp2 and mp4 are provided on the power supply side, and NMOS transistors mn2 and mn4 are provided on the ground side. The clock signal VC is supplied to the MOS transistors mp4 and mn2.
K is supplied, and the inverted clock signal VCKX of the clock signal VCK is supplied to the MOS transistors mp2 and mn4.

The shift register is configured by arranging a plurality of transfer circuits each having such a configuration as one unit in series. Then, as shown in the timing chart of FIG.
A signal (A) in which the input signal VIN is synchronized with the clock signals VCK and VCKX is generated at the input side of the third CMOS transistor. Further, a signal (B) obtained by inverting the phase of the signal (A) to have the same phase as the input signal VIN is the third C signal.
Generated at the output side of the MOS transistor. Further, signals (C) and (D) obtained by delaying the signals (A) and (B) by one clock are generated by the next-stage transfer circuit.

[0007]

The above-mentioned power supply voltage VDD
Usually, a high voltage of, for example, about 14 to 18 V is used. However, when such a high voltage is applied between the nodes of the TFT, there is a problem that the reliability of the device is reduced.
To solve this problem, for example, it is conceivable to increase the thickness of the gate oxide film of the MOS transistor. However, when the gate oxide film is thickened, the threshold voltage Vth
In addition, there are inconveniences such as an increase in the operating speed and a decrease in the operation speed (a decrease in gm), and there is a possibility that the entire process must be changed.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an inverter circuit which has a high breakdown voltage and improved reliability without changing the process or sacrificing the operating characteristics of the transistor. I do.

[0009]

An inverter circuit according to the present invention is an inverter circuit composed of TFTs, and includes a PMOS transistor connected to a power supply side, an NMOS transistor connected to a ground side, and a MOS transistor connected to a ground side. And a diode-connected MOS transistor interposed in series between the power supply side and the ground side.

In the inverter circuit having the above configuration, PM
MOS diode-connected to the power supply side and the ground side with respect to the OS transistor and the NMOS transistor
By connecting the transistors in series, the signal level decreases by the threshold voltage of the diode-connected transistor on the high level side and increases by the threshold voltage on the low level side. Thereby, the magnitude of the voltage applied between the gate and the drain, between the gate and the source, and between the drain and the source of each MOS transistor constituting the inverter circuit is larger than the magnitude of the voltage applied from the outside. Is reduced by the threshold voltage, and as a result, the withstand voltage of the inverter circuit is improved.

[0011]

FIG. 1 is a circuit diagram of a main part of a shift register using an inverter circuit according to an embodiment of the present invention.

As is clear from FIG. 1, this shift register has one unit transfer circuit composed of a first circuit block 1, a second circuit block 2, and a third circuit block 3. Then, these circuit blocks 1 to 3
Has a CMOS inverter circuit as its basic configuration.

The first circuit block 1 has a first CMOS inverter 1a composed of a PMOS transistor mp1 and an NMOS transistor mn1, and the first CM
A PMOS transistor m is provided on the power supply side of the OS inverter 1a.
In addition to p2, an NMOS transistor mn2 is provided on the ground side. A diode-connected PMOS transistor mp6 is interposed between the PMOS transistor mp2 and the power supply VDD, and the NMOS transistor mn2 and the ground GN
A diode-connected NMOS transistor mn6 is interposed between D and D.

The second circuit block 2 comprises a PMOS
A second CMOS inverter 2a including a transistor mp3 and an NMOS transistor mn3;
A PMOS transistor mp4 is provided on the power supply side of the CMOS inverter 2a, and an NMOS transistor mp4 is provided on the ground side.
An S transistor mn4 is provided. And the above PM
A diode-connected PMOS transistor mp7 is interposed between the OS transistor mp4 and the power supply VDD, and a diode-connected NMO is connected between the NMOS transistor mn4 and the ground GND.
An S transistor mn7 is provided.

On the other hand, the third circuit block 3 comprises a PMOS
A third CMOS inverter 3a comprising a source of the transistor mp5 and an NMOS transistor mn5;
The OS transistor mp8 is connected. An NMOS transistor mn8 is connected to the ground side.

The input signal VIN is supplied to the first circuit block 1
Is provided to the input terminal of the CMOS inverter 1a. Further, the NMOS transistor mn2 of the first circuit block 1 and the PMO of the second circuit block 2
The clock signal VCK is applied to each gate of the S transistor mp4.
And the PMO of the first circuit block 1
S transistor mp2 and N of second circuit block 2
The inverted clock signal VCKX of the clock signal VCK is supplied to each gate of the MOS transistor mn4.

The output terminal of the first CMOS inverter 1a is connected to the output terminal of the second CMOS inverter 2a and the input terminal of the third CMOS inverter 3a, respectively. On the other hand, the third CMOS inverter 3
a and the input terminal of the second CMOS inverter 2a is connected to the third CMOS inverter 3a.
The output signal (B) of the first-stage circuit is derived from the output terminal of the first stage to the first output terminal OUT1.

The shift register according to this embodiment has such a circuit configuration as one unit of transfer circuit, and a plurality of the transfer circuits are arranged in series. Therefore, as shown in the timing chart of FIG. 2, the signal (A) obtained by synchronizing the input signal VIN with the clock signals VCK and VCKX is the third signal.
At the input side of the CMOS inverter 3a. Further, the input signal VIN is inverted by inverting the phase of the signal (A).
The signal (B) in phase with the third CMOS inverter 3
a is generated at the output side.

Signals (C) and (D) obtained by delaying the signals (A) and (B) by one clock are generated by a transfer circuit connected to the next stage. 2 output terminal OUT2.

The signal transfer operation in the shift register according to the present embodiment configured as described above is exactly the same as that of the conventional shift register shown in FIG. However, in this example, the power supply VDD side of each of the circuit blocks 1 to 3 and the ground G
MOS transistors (nm6, nm7, nm8) and (mp) diode-connected to all nodes on the ND side
6, mp7, mp8), the withstand voltage can be improved without changing the external drive conditions.

That is, as shown in the timing chart of FIG. 2, also in the shift register according to the present embodiment, the power supply VDD, the input signal VIN, the clock signal VCK, and the inverted clock signal VCKX are given with a predetermined high voltage value. However, as described above, in the case of the shift register according to the present example, since MOS transistors diode-connected to all the nodes on the power supply VDD side and the ground GND side are inserted, their outputs are limited to Vthn and Vthp, respectively. . Therefore, the internal transfer operation in the transfer unit 5 indicated by the broken line in FIG. 1 is performed at a signal level higher than the ground GND by Vthn and lower than the power supply VDD by Vthp.

As a result, in the shift register according to the present embodiment, the voltage applied between any nodes of all the MOS transistors can be suppressed to a maximum of | VDD-Vthp |, and the entire shift register is accordingly reduced. Can be improved. Accordingly, a high breakdown voltage can be achieved without changing the process or sacrificing the operation characteristics of the transistor, and the reliability of the shift register can be improved.

The diode-connected transistor does not necessarily have to be configured as shown in FIG. 1, and the PMOS transistor and the NMOS transistor in FIG. 1 may be replaced.

[0024]

As described above, according to the present invention,
In an inverter circuit composed of TFTs, P
The MOS transistors and the NMOS transistors are diode-connected to the power supply side and the ground side.
Since the S transistor is interposed in series, the signal level can be reduced by the threshold voltage of the diode-connected transistor on the high level side, and
On the low level side, it can be increased by the threshold voltage. Therefore, between the gate and the drain of each MOS transistor constituting the inverter circuit,
The magnitude of the voltage applied between the gate and the source and between the drain and the source can be made smaller than the magnitude of the externally applied voltage by the threshold voltage of the diode-connected transistor. Therefore, high breakdown voltage can be achieved without changing the process, and the reliability of the inverter circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a shift register using an inverter circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart of the circuit of FIG.

FIG. 3 is a main part circuit diagram showing an example of a shift register according to a conventional example.

FIG. 4 is a timing chart of the circuit of FIG. 4;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st circuit block, 1a ... 1st CMOS inverter, 2 ... 2nd circuit block, 2a ... 2nd CMOS
Inverter, 3 ... third circuit block, 3a ... third C
MOS transistor, VIN: input signal, VDD: power supply, GND: ground, VCK: clock signal, VCK
X: inverted clock signal

Claims (1)

[Claims] 1. An inverter circuit comprising a thin film transistor, comprising: a PMOS transistor connected to a power supply side; an NMOS transistor connected to a ground side; and a power supply side with respect to the PMOS transistor and the NMOS transistor. An inverter circuit, comprising: a diode-connected MOS transistor interposed in series with the ground side.