JPH04238198A - Shift register - Google Patents

Abstract

PURPOSE:To obtain higher voltage resistance and to improve the reliability of a shift register without changing a process and without sacrificing the operating characteristics of transistors. CONSTITUTION:The diode-connected MOS transistors are connected to all nodes on a power source side and ground side of respective circuit blocks constituting the shift register, by which the signal level of internal transfer is lowered by as much as the threshold voltage-component of the above-mentioned diode- connected TRs on a high-level side and is raised by as much as the above- mentioned threshold voltage-component on a low level side.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to shift registers, and is particularly suitable for use in improving the withstand voltage of shift registers composed of TFTs.

0002

BACKGROUND OF THE INVENTION For example, a shift register is used as a circuit to hold a signal generated in a certain circuit for a predetermined period of time, or to delay it by a predetermined period and output it to the next stage circuit. There is. FIG. 3 is a circuit configuration diagram showing an example of a conventional shift register. This circuit is PM
OS transistor mp1 and NMOS transistor mn1
A second CMOS transistor includes a PMOS transistor mp3 and an NMOS transistor mn3, and a third CMOS transistor includes a PMOS transistor mp5 and an NMOS transistor mn5.

[0003] The third CM of each CMOS transistor
The source of the OS transistor PMOS transistor mp5 and the source of the NMOS transistor mn5 are directly connected to the power supply VDD and the ground GND, respectively. On the other hand, the first and second CMOS transistors include PMOS transistors mp2 and mp4 on the power supply side, and NMOS transistors mn2 and mn4 on the ground side. And the above MO
A clock signal VCK is applied to the S transistors mp4 and mn2, and an inverted clock signal VCKX of the clock signal VCK is applied to the MOS transistors mp2 and mn4.

[0004] A shift register is constructed by arranging a plurality of transfer circuits in series each having such a configuration as one unit. Then, as shown in the timing chart of FIG.
A signal (A) in which the input signal VIN is synchronized with the clock signals VCK and VCKX is generated on the input side of the third CMOS transistor. Furthermore, the signal (B) obtained by inverting the phase of the above signal (A) to be in phase with the input signal VIN is transmitted to the third C.
Generated on the output side of the MOS transistor. Further, signals (C) and (D), which are obtained by delaying the above-mentioned signals (A) and (B) by one clock, are generated by the next-stage transfer circuit.

[0005]

[Problems to be Solved by the Invention] As the power supply voltage VDD, a high voltage of, for example, 14 to 18 V is normally used, but if such a high voltage is applied between each node of the TFT, the reliability of the device decreases. There was a problem. In order to solve this problem, it is conceivable to increase the thickness of the gate oxide film of the MOS transistor, for example. However, if the gate oxide film is thickened, the threshold voltage Vth
In addition to causing inconveniences such as an increase in gm or a decrease in operating speed (decreased gm), there was also the possibility that the entire process would have to be changed. In view of the above-mentioned problems, it is an object of the present invention to increase the withstand voltage without changing the process or sacrificing the operating characteristics of the transistor, and to improve the reliability of the shift register.

[0006]

[Means for Solving the Problems] The shift register of the present invention is a CMOS to which an input signal supplied from a previous stage is applied.
A first circuit block provided with a transistor and having MOS transistors for inputting a clock signal connected to its power supply side and ground side, respectively, and whose input terminal is connected to an output terminal of the first circuit block. C
a second circuit block having a MOS transistor, to which a MOS transistor for inputting a clock signal is connected to the power supply side and the ground side; and an input terminal thereof to each output terminal of the first and second circuit blocks. and a third circuit block consisting of a CMOS transistor, the output terminal of which is connected to the input terminal of the second circuit block, and each of the first to third circuit blocks. Diode-connected MOS transistors are provided on the power supply side and the ground side, respectively.

[0007]

[Operation] By connecting diode-connected MOS transistors to all nodes on the power supply VDD side and the ground GND side in the first to third circuit blocks constituting the shift register, the internal transfer signal level is set to the high level side. On the low level side, the voltage decreases by the threshold voltage of the diode-connected transistor, and increases by the threshold voltage on the low level side. This results in
The magnitude of the voltage applied between the gate and drain, between the gate and source, and between the drain and source of each MOS transistor constituting the shift register is greater than or equal to the magnitude of the externally applied voltage. The voltage decreases by the threshold voltage, and as a result, the withstand voltage of the shift register improves.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of a main part of a shift register showing an embodiment of the present invention. As is clear from FIG. 1, in this shift register, a first circuit block 1, a second circuit block 2, and a third circuit block 3 constitute one unit transfer circuit. The first circuit block 1 is
PMOS transistor mp1 and NMOS transistor m
The first CMOS transistor 1a has a PM transistor on the power supply side of the first CMOS transistor 1a.
An OS transistor mp2 is provided, and an NMOS transistor mn2 is provided on the ground side. Further, a diode-connected PMOS transistor mp6 is interposed between the PMOS transistor mp2 and the power supply VDD, and the NMOS transistor m
A similarly diode-connected NMOS transistor mn6 is interposed between n2 and the ground GND.

Further, the second circuit block 2 is a PMOS
It has a second CMOS transistor 2a consisting of a transistor mp3 and an NMOS transistor mn3, and a PMOS transistor mp4 is interposed on the power supply side of the second CMOS transistor 2a, and an NMOS transistor mp4 is provided on the ground side.
A MOS transistor mn4 is interposed. A diode-connected PMOS transistor mp7 is interposed between the PMOS transistor mp4 and the power supply VDD, and a diode-connected NMOS transistor mp7 is also provided between the NMOS transistor mn4 and the ground GND.
A MOS transistor mn7 is provided.

On the other hand, the third circuit block 3 is a PMOS
It has a third CMOS transistor 3a consisting of the source of the transistor mp5 and an NMOS transistor mn5, and a P is connected to the power supply side of the third CMOS transistor 3a.
A MOS transistor mp8 is connected. Further, an NMOS transistor mn8 is connected to the ground side.

The input signal VIN is input to the first circuit block 1.
It is applied to the input terminal of the CMOS transistor 1a that constitutes the circuit. Furthermore, the NMOS transistor mn2 of the first circuit block 1 and the PM of the second circuit block 2 are
A clock signal VC is applied to each gate of the OS transistor mp4.
K is given, and the PM of the first circuit block 1 is
An inverted clock signal VCKX of the clock signal VCK is applied to each gate of the OS transistor mp2 and the NMOS transistor mn4 of the second circuit block 2.

Furthermore, the output terminal of the first CMOS transistor 1a is connected to the output terminal of the second CMOS transistor 2a and the input terminal of the third CMOS transistor 3a, respectively. On the other hand, the output terminal of the third CMOS transistor 3a and the second CMOS transistor 2
The output signal (B) of the first stage circuit is output from the output terminal of the third CMOS transistor 3a to the first output terminal OUT1.

The shift register of this embodiment has such a circuit configuration as one unit of transfer circuit, and is constructed by arranging a plurality of such circuits in series. Therefore, as shown in the timing chart of FIG. 2, the signal (A) obtained by synchronizing the input signal VIN with the clock signals VCK and VCKX is
is generated on the input side of the CMOS transistor 3a. Furthermore, the input signal VIN is obtained by inverting the phase of the above signal (A).
A signal (B) which is in phase with , is generated on the output side of the third CMOS transistor 3a. In addition, the above signal (A), (
Signals (C) and (D) that are obtained by delaying B) by one clock
is generated by the transfer circuit connected to the next stage, and the above signal (D
) is led out to the second output terminal OUT2.

The signal transfer operation in the shift register of this embodiment configured as described above is exactly the same as that of the conventional shift register shown in FIG. However, in this embodiment, all nodes on the power supply VDD side and ground GND side of each circuit block 1 to 3 are connected to diode-connected MOS
Transistors (nm6, nm7, nm8) and (mp
6, mp7, mp8), the withstand voltage can be improved without changing the external drive conditions.

That is, as shown in the timing chart of FIG. 2, in the shift register of this embodiment, the power supply V
DD, input signal VIN, clock signal VCK and inverted clock signal VCKX are given at predetermined high voltage values. However, as mentioned above, in the case of the shift register of this embodiment, diode-connected MOS transistors are inserted in all nodes on the power supply VDD side and the ground GND side, so the outputs are limited to Vthn and Vthp, respectively. . Therefore, the internal transfer operation in the transfer unit 5 shown by the broken line in FIG.
The signal level is higher by thn and lower by Vthp than the power supply VDD.

[0016] As a result, the voltage applied between any nodes of all MOS transistors in the shift register of this embodiment can be suppressed to a maximum of |VDD-Vthp|, and the voltage of the entire shift register can be suppressed by that much. It is possible to improve pressure resistance. Therefore, it is possible to increase the withstand voltage without changing the process or sacrificing the operating characteristics of the transistor, and the reliability of the shift register can be improved. Note that the diode-connected transistor does not necessarily have to be configured as shown in FIG. 1, and the PMOS transistor and NMOS transistor in FIG. 1 may be replaced.

[0017]

Effects of the Invention As described above, the present invention provides diode-connected MOS transistors at all nodes on the power supply VDD side and the ground GND side in each circuit block constituting the shift register. The level can be lowered by the threshold voltage of the diode-connected transistor on the high level side, and raised by the threshold voltage on the low level side. Therefore, the magnitude of the voltage applied between the gate and drain, between the gate and source, and between the drain and source of each MOS transistor constituting the shift register is set to be smaller than the magnitude of the externally applied voltage. can also be reduced by the threshold voltage of the diode-connected transistor. Therefore, a high breakdown voltage can be achieved without changing the process, and the reliability of the shift register can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a main part of a shift register showing an embodiment of the present invention.

FIG. 2 is a timing chart of the circuit of FIG. 1;

FIG. 3 is a circuit diagram of a main part of a shift register showing an example of a conventional shift register.

FIG. 4 is a timing chart of the circuit of FIG. 4;

[Explanation of symbols]

1 First circuit block 1a First CMOS transistor 2 Second circuit block 2a Second CMOS transistor 3 Third circuit block 3a Third CMOS transistor VIN input signal VDD power supply GND Ground VCK Clock signal VCKX Inverted clock signal

Claims (1)

[Claims] 1. A first circuit block provided with a CMOS transistor to which an input signal supplied from a previous stage is provided, and a MOS transistor for inputting a clock signal is connected to the power supply side and the ground side, respectively; a second circuit block having a CMOS transistor whose input terminal is connected to the output terminal of the first circuit block, and a second circuit block having a clock signal input MOS transistor connected to its power supply side and ground side, respectively;
A C whose input terminal is connected to each output terminal of the first and second circuit blocks, and whose output terminal is connected to the input terminal of the second circuit block.
and a third circuit block made of MOS transistors, and a diode-connected MOS transistor is provided on the power supply side and ground side of each of the first to third circuit blocks, respectively. register.