JPH01109440A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To shorten processing time by providing two systems of error correcting pattern holding circuits, ceasing switching to be executed next when an error is detected, and executing reading/writing in the same role condition as before. CONSTITUTION:The title circuit is equipped with first and second error correcting pattern holding circuits 15 and 15' to which an error correcting pattern outputted from an error correcting pattern generating circuit 16 are impressed respectively and in parallel and a switching circuit 17 to be able to switch and control the device so that the holding circuits 15 and 15' can be alternately loaded and stored each time plural data parts and an ECC (Error Correcting Code) data part in a data recording block are successively inputted. When the error is detected in the data part inputted at this time, the switching circuit 17 does not execute switching control for the holding circuits 15 and 15', holds the current control condition, and allows the device to execute the processing of the data part to be inputted next. Thus, the error can be corrected instantaneously without adding any excess time.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data recording prop P error correction circuit in a data format with ECC.

The object of the present invention is to provide an error correction circuit that can immediately correct an error without adding extra time when an error occurs.

An error correction pattern generation circuit with an exclusive OR operation function.

A first error correction pattern holding circuit to which the error correction patterns output from the error correction pattern generation circuit are respectively applied in parallel, a second error correction pattern holding circuit, and a plurality of data portions and E in the data recording block.
The switching circuit is provided with a switching circuit capable of switching control so as to alternately load and store the first error correction pattern holding circuit and the second error correction pattern holding circuit each time the CC data section is inputted one after another. , when an error is detected in the data section that was input this time.

The configuration is such that the first and second error correction pattern holding circuits are not controlled to switch between loading and storing, but are made to maintain the current control state and process the data portion inputted ninth time.

[Industrial application field]

The present invention is based on ECC (Error Correctin).
The present invention relates to an error correction circuit for data recording blocks recorded in a storage device or transmitted in a data format with a g code.

In a typical magnetic tape device, recording or reproduction is performed using data recording blocks having a recording format as shown in FIG.

In the illustrated data recording block, the check character CC of each data section is at the end of the data section, and whether or not the data in each data section is correct cannot be determined until the check character is read or if there is an abnormal format, for example, in the middle of the data. 2 cannot be discriminated until a gap is detected.

Further, the ECC data section is recorded all together at the end of the data recording block, and the generation of the error correction pattern is completed only when the end of the data recording block is read.

The present invention particularly relates to an error correction circuit that reads data recording blocks in such a format and automatically corrects errors.

In general, with magnetic tape, data may drop out due to defects in the medium such as pinholes, adhesion of dust, or poor contact on the head surface due to the fact that it is a flexible medium, resulting in data not being output in the middle of the data section. Occurs often.

Furthermore, since the magnetic tape device is a sequential access device, processing time will increase unless control is performed to perform continuous processing in one direction.

Especially reel to reel
) In streaming magnetic tape devices that use the control method, immediate error correction is required because stopping the tape and re-reading the original block requires a large amount of time due to the repositioning operation. It is said that

[Conventional technology]

FIG. 9 shows an example of a conventional error correction circuit.

In the figure, 91 is a data reading circuit such as a magnetic tape device, 92 is a data memory for storing four data sections A, B, C, and D in a data recording block, and 93 is a data memory for storing data "OO" in the data memory 92. ” data “00” generation circuit for clearing, 94 is an error correction circuit, 95
is an error correction pattern generation circuit composed of EOR, 9
6 is an error correction pattern holding circuit.

97 is a normal data generation circuit composed of HOR.

The principle of this error correction circuit is that AeBeCΦD=II
From CC, when any one of A, B, C, and D, for example C, is an error (represented by C'), the normal value C is.

(AeBeC'ΦDeECC) ∎C' This method takes advantage of the fact that it is impossible to obtain a smile.

The data reading circuit 91 reads the data recording block 90 in the order of data parts A, B, C, D, and the ECC data part, and inputs them to the data memory 92 and the error correction pattern generation circuit 95 of the error correction circuit 94.

The error correction pattern generation circuit 95 generates [! Perform an OR (exclusive OR) operation,
The result is input to the error correction/turn holding circuit 96 and its contents are updated. Manipulating this motion, t hchi, A-A69B-(AΦB)Φc-(AeBΦC) e
D-... is executed and the error correction pattern holding circuit 96
includes each data section of the data recording block 90 and the EC
Error correction pattern data is generated as a result of EOII accumulation between the C data sections.

After all data parts p, , B, C, and D are stored in the data memory 92, the normal data generation circuit 97 determines whether an error has been detected in any of the data parts (in this case, data part C). If so, the error data (C') and
EO[l with the error correction pattern AΦBeCΦDΦECC generated in the error correction pattern holding circuit 96
The calculation is performed to generate normal data (C) and update the error data in the data memory 92. This operation is expressed by a 9th order equation.

(AeB■C'■DΦECC)eC'-C [Problem to be Solved by the Invention] In the conventional error correction circuit shown in FIG.

Since only one system of error correction pattern holding circuit is provided, an error correction pattern is generated including data in the error data section, and error correction is performed by performing an EOR operation on error correction/< turn and error data.

Here, if some data in the data section is missing.

The total number of data in the error data section is insufficient, and the error correction pattern has the same result as replacing the missing 9 data with data "00". Therefore, the data corresponding to the missing data length of the read error data is “OO”.
Dena (not.

However, when data is lost in this way, the data memory 9
Previously input data left in 2 becomes apparent,
Since the data is fixed, error correction using ECC data will result in an error.

To prevent this, it is necessary to set all the contents of the data holding section to "OO" before starting data reading, but it is impossible to predict which part of the program will be missing when reading starts. Because it is.

It is necessary to initialize all data holding areas of the data memory 92 to 00''. However, since the time required for this process is longer than the time required to pass through the gap between blocks, it is determined that error correction is necessary. The tape is stopped only when an error block is detected, the data holding area of the data memory 92 is set to OO'', the tape is repositioned to the error block, the data is read, and the error is corrected.

Therefore, there are problems in that the control becomes complicated and the processing time increases.

The present invention enables instantaneous processing without adding extra time when read data is lost in the middle.
It is an object of the present invention to provide an error correction circuit capable of correcting errors in an E-fly.

[Means for solving problems]

The present invention provides an error correction circuit with two systems of error correction pattern holding circuits that hold error correction patterns that are in the process of being generated, and each of them is alternately used for reading and writing by the error correction pattern generation circuit. Use while switching to.

When an error is detected in the input data section, the next alternating switching between reading and writing is paused, and reading/writing is performed in the same role as before, thereby eliminating the error data section. The included FOR cumulative data is not adopted, and the EOR cumulative data, that is, the error correction pattern can be automatically obtained only from the data section excluding the error data section.

FIG. 1 shows the basic configuration of the present invention.

In fig.

Reference numeral 10 denotes a data recording block, which in this example is composed of four data sections A, B, C, and D, and an ECC data section. Each data section and ECC data section can be independently checked for errors using check characters CC.

Reference numeral 11 denotes a data reading circuit to which a reading signal from, for example, a magnetic tape is input, and outputs a data signal Data. It also outputs a block signal Block for identifying the data portion of the data recording block IO.

Reference numeral 12 denotes an error detection circuit, which performs an error check on each of the input data sections A, B, C, D and ECC data section using check characters CC, etc., and outputs an error signal Error when an error is detected. do.

13 is a data memory, and a data reading circuit 11
Based on the data signal Data output from.

Data of data portions A, B, C, and D are stored.

14 is an error correction circuit to which the present invention is directed.

15 and 15' are first and second error correction pattern holding circuits, respectively.

Reference numeral 16 denotes an error correction pattern generation circuit, which reads the data signal Data from the data reading circuit 11 and the first and second error correction pattern holding circuits Is from one of the circuits designated for reading out of 15'. An EOR operation is performed on the data, and the result is written and updated in the other circuit designated for writing among the first and second error correction pattern holding circuits.

17 is a switching circuit which applies load/store switching signals L/S and L/S to the first and second error correction pattern holding circuits 15 and 15', respectively, so that one is used for loading and the other is used for loading. control for the store.

These load/store switching signals L/S and L/S are.

When no error is detected in the input data section (
1Error = O) For the inverted data portion inputted in the 6th order, the role of loading and storing for the first and second error correction pattern holding circuits 15 and 15' is switched.

However, when an error is detected in the input data section (
For Error-1), the load/store switching signal is not inverted, and the roles of the first and second error correction pattern holding circuits 15 and 15' are not changed for the next input data portion.

[For production]

The operation of the circuit of the present invention shown in FIG. 1 will be explained using FIG. 2.

In fig.

(al is a data recording block. Data section A.

Of the B, C, D and ECC data sections, data section C is shown as having an error.

(b) shows a change in the contents of the first error correction pattern holding circuit 15.

(C) shows a change in the contents of the second error correction pattern holding circuit 15'.

(dl indicates a change in the load/store switching signal L/S applied from the switching circuit 17 to the first error correction pattern holding circuit 15.

(e) shows changes in the load/store switching signal L/S applied from the switching circuit 17 to the second error correction pattern holding circuit 15'.

(f) shows an initialization signal (“00” clear signal) generated to the first error correction pattern holding circuit 15 during the reading period of the data portion A.

(Kozue is from the data reading circuit 11 to the switching circuit 1.
2 shows a block signal Block applied to 2.

(h) shows an error signal Error applied from the error detection circuit 12 to the switching circuit 17.

The data lengths of the data parts A to D and the ECC data part are all equal (n), and the ECC data part has f! The OR result is recorded as shown below.

A+eB+ΦCIeDt -ECG+ AzeBtΦCt eDt -14CCzA, eB, Φ
C, eD, = When reading BCC% + C11-
When the data of 11 to C,1 is incorrect or missing, the correct data C,, C, . . . of the data section C can be reproduced as follows.

A1 ■B+ eD+ e ECC+ =C+
A2 ■B z e D t e ECCz =
CzA, 1 ■B, l eDI% (t) ECC,=
When starting to read the 01% data recording block, the initialization signal to the first error correction pattern holding circuit 15 is always turned ON, and turned OFF when the data section A is correctly read. As a result, the first error correction pattern holding circuit 15 is cleared to "oo".

When reading the data portion A, the load/store switching signal L/S7'l<L and the signal L/S is S.

The read data A and 00'' loaded from the first circuit 15 are EORed, and the resultant A is stored in the second circuit 15'.

Next, if the data part A is read normally, the error signal Err
Since or is OFF and the block signal Block is ON, the signal L/S becomes low and the signal L/S becomes S.

The data in the data section B and the error correction pattern (A) held in the second circuit 15' are EORed and stored in the first circuit 15.

When the data section B is read normally, the load and store circuits are switched in the same way as above, and the read data section C and the error correction pattern held in the first circuit 15 (
AeB) and the result (AeBeC) as the second
Circuit 15' is varnished.

Next, if a dropout occurs in the middle of the data section C, the IBG (Inter Block G, not shown in Figure 1)
ap) signal is turned ON, and a gap is detected before reading the predetermined data length, resulting in a short block error, and the error detection circuit 12 turns on the error signal Error, and the load/store switching signal of the switching circuit 17 is activated. L
Hold /S and L/S without inverting them.

Therefore, when reading the data part, the error correction pattern (A(9B) held in the first circuit 15 and data D are BOR'ed, and the u result (A69BIEEID) is read from the second circuit.
The data is stored in the circuit 15'.

Next, when reading the ECC data section, the FCC data and the error correction pattern of the second circuit 15' are EORed and written to the address corresponding to data C in the data memory, completing automatic error correction.

〔Example〕

The present invention will be explained in detail using FIGS. 3 to 7.

FIG. 3 is a block diagram of the error correction circuit.

30 is a drive for magnetic tape or the like.

31 is a serial/parallel converter that converts read data in serial format into parallel format (bytes).

32 is a read register that temporarily holds read data.

33 is a format error detection circuit.

34 is a CRC check circuit.

35 is a block detection circuit.

36 is a data register that holds read data.

37 is an FCC register into which an error correction pattern is loaded.

38 is an EOR circuit, in order to update and generate the error correction pattern sequentially, the F of the read data of the data register 36 and the previous error correction pattern of the ECC register 37 is
Perform an OR operation.

39 is an ECC memory that holds error correction patterns, and is composed of two banks Bank O + Bank 1 (error correction pattern holding circuit 15.1 in Fig. 1).
5').

40 is a switching circuit that generates a bank address for load/store control of the ECC memory 39 and an initialization signal for the ECC register 37;

41 is a data memory.

42 is a block counter, which continuously generates each block address indicating the storage location of the data portions A, B, C, and D in the data memory 41.

43 is an intra-block address counter;
Generate a byte address in (data part).

44 is an error block address register.

The block address in the data memory 41 of the block (data section) in which the error was detected is held.

45 is a multiplexer MPX, which selects the block address that is the output of the block counter 42 when sequentially writing the data of each input data section to the data memory 41, and selects the block address that is the output of the block counter 42, and selects the error block address register when writing error-corrected data. The error block addresses output from 44 are selected and applied to the data memory 41 as respective data bank addresses.

46 is a write control circuit, ECCCYCLf! In other periods, data write D of data sections A, B, C, and D is performed.
At the time of ATA WRITIIj and during the IICCCYCLE period, the write enable -E of the data memory 41 is turned ON at the time of store control 5TOR8.

47 is a read bus.

48 is a data buffer bus. 49 is a data transfer circuit to the host device.

FIG. 4 shows details of the various control signal generation circuits used in the embodiment circuit of FIG. Further, FIGS. 5 to 7 each show the operation timing in the embodiment circuit of FIG. 3.

(a) in FIG. 4 shows the load control signal LOAD, data write signal Data l1rite, and store control signal 5T.
A circuit configuration including a counter shift register for generating each timing signal of ORH is shown (note that the corresponding circuit is omitted from FIG. 3).

By dividing the read clock with a counter and delaying it with a shift register as shown.

Each control signal LOAD, Data l1rite, 5
TORE is generated sequentially and cyclically as shown in FIG.

4) is the switching circuit 40 in FIG. Block counter 42. Error block address register 44
．． The detailed configuration of MPX 45 is shown.

In the switching circuit 40, JK-pp is the block signal B
This JK-FP performs a toggle operation that alternately inverts by lock (FIG. 5 (C)).
et (FIG. 5(b)), it is reset before the start of block reading, so it always starts at Q-0°Q-1, and by using an AND gate, LOA
It is controlled to output ECC bank address -0 at the D signal timing, and output ECC bank address -1 at the 5TORE signal timing.

After that, every time Block turns ON, LO^D, 5
Although the ECC bank address for TORfl is inverted.

When Error is ON, B for JK-FF
Since the application of the lock is blocked, the toggle operation of the JK-PF stops (Fig. 5(d), (k) to (→)).

Also, after D-PF is reset by Re5et.

When "1" is set by Block, an initialization signal that is turned ON only in the data section A is output as shown in FIG. 5 (14).

The block counter 42 is a 3-bit quinary counter and is reset by Re5et.

Each time Block is applied, block address 2t
'.

5(f).

(Kozue) Finally, turn on the IICCCYCLE output at the timing corresponding to the ECC data part (Figure 5 (h))
.

When an error is detected in a certain data section and Error is turned ON, the error block address register 44 holds the block addresses 2° and 2I at that time.
Data memory 41 (third
(Figure) can be used to write modified data.

The MPX 45 selects block addresses 2@ and 2t when IICCCYCLE is OFF, that is, during reading of data sections A, B, C, and D, and
c CYCL[! is ON, selects error block address 2), 21, and data bank address 2°, 2
1 to the data memory 41 (FIG. 5, 11) (
J)).

Note that FIG. 5 is for the case where there is an error in the data section C, similar to FIG. 2, and +111) in FIG.
The error correction pattern shown in (0) is the ECC memory 3
9 (FIG. 3) in each bank Bank O and Bank I.

Stored and loaded sequentially.

In FIG. 3, the IICC memory 39 is 5TOR
When E is ON, write enable l1lE is ON, and when LOAD is ON, output enable O
E turns ON.

As a result, when 5TORE is ON, the bank of ECC memory 39 specified by the ECC bank address is transferred.

The error correction pattern output from the EOR circuit 38 is stored via the data buffer bus 48, and when LOAD is ON, the error correction pattern in the bank of the ECC memory 39 specified by the FCC bank address is stored on the data buffer bus 48. ECC register 37 via 48
This enables EOR operation with the secondary data section.

FIG. 6 shows the operation timing during the period when ECCCYCLE is OFF, and FIG. 7 shows the operation timing during the period when ECCCYCLE is ON.

In FIGS. 6 and 7.

(a) represents read data held in the read register 32, and D, , D, . . . are byte data, respectively.

(mountain) represents transfer data on the data buffer bus 48, DI, Dz, . . . are read data transferred to the data register 36, and E+, Ex, . . . are error correction patterns loaded from the ECC memory 39. data + D s' + 02' + . . . is read data transferred to the data memory 41, and X is the error correction pattern transferred from the EOR circuit 38 to the ECC memory 39 or to the data memory 41 in the case of error correction. It is data.

(e) is a read clock.

(dl represents read data held in the data register 36.

(61 is the load control signal LOAII.

([1 represents the error correction pattern data held in the ECC register 37.

(1 is the data write control signal Data Write.

(hl represents read data stored in the data memory 41.

(1) is the store control signal 5TORE.

('') is an error correction pattern held in the ECC memory 39. Note that EI', E2'+ ``'' is EC
C register 37 error correction pattern and data memory 4
This is an updated error correction pattern as a result of performing an EOR operation on the read data of No. 1.

(kl is FICCCYCt, E.

〔Effect of the invention〕

According to the present invention, data read by a magnetic tape device, etc. is continuously checked, and even if an error is detected, the error is automatically corrected in real time without adding any special control, and the data is output to the host device. Therefore, processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is an explanatory diagram of the operation of the present invention, FIG. 3 is a block diagram of an error correction circuit according to an embodiment of the present invention, and FIG. 4 is a diagram of the embodiment of the present invention. Detailed diagrams of various control signal generation circuits. FIG. 5 is an operation timing diagram centered on control signals in the embodiment of FIG. 3, and FIG. 6 is an operation timing diagram when IICCCYCLE is OF.
An operation timing diagram centered on data at F. FIG. 7 is an operation timing diagram centered on data when BCCCYCIF+ is ON, FIG. 8 is an explanatory diagram of the recording format of data recording blocks, and FIG. 9 is a configuration diagram of a conventional error correction circuit. In Figure 1. IO is a data recording block. 11 is a data reading circuit. 12 is an error detection circuit. 13 is data memory. 14 is an error correction circuit. 15 is a first error correction pattern holding circuit; 15' is a second error correction pattern holding circuit. 16 is an error correction pattern generation circuit. 17 is a switching circuit.

Claims (1)

[Scope of Claims] An error correction circuit that reads a data recording block including a plurality of data sections each having a check character and an ECC data section and automatically corrects errors in the data section, comprising an exclusive OR operation function. a first error correction pattern holding circuit (15) to which the error correction patterns output from the error correction pattern generation circuit (16) are respectively applied in parallel; The error correction pattern holding circuit (15') and the first error correction pattern holding circuit (15') each time a plurality of data parts and ECC data parts in the data recording block are inputted sequentially.
) and a second error correction pattern holding circuit (15') are provided with a switching circuit (17) capable of switching control so as to alternately load and store the error correction pattern holding circuit (15'). , and sequentially apply each data of a plurality of data sections and an ECC data section of a data recording block, and to the other input, first and second error correction pattern holding circuits (
15, 15'), the contents of the circuit that was under store control immediately before are loaded, and at the same time, the output of the error correction pattern generation circuit (16) is held as the error correction pattern that was under load control immediately before. When an error is detected in the currently input data section, the switching circuit (17) performs load and store operations on the first and second error correction pattern holding circuits (15, 15'). Maintains the current control state without performing switching control,
An error correction circuit characterized in that it processes the next input data part.