JPH0668730B2 - Error correction circuit - Google Patents

Description

The present invention relates to an error correction circuit for a data recording block in a data format with ECC, and an error correction circuit capable of immediately correcting an error without adding extra time when an error occurs. As an object, an error correction pattern generation circuit having an exclusive OR operation function, a first error correction pattern holding circuit to which the error correction patterns output from the error correction pattern generation circuit are respectively applied in parallel, and a second error correction pattern holding circuit Error correction pattern holding circuit, multiple data parts in data recording block and EC
Each time the C data section is sequentially input, the switching circuit has a switching circuit capable of switching control so that the first error correction pattern holding circuit and the second error correction pattern holding circuit are alternately loaded and stored. , When an error is detected in the data part input this time, the first and second
The error correction pattern holding circuit of No. 1 is configured to hold the current control state without performing load / store switching control and process the next input data portion.

[Industrial application field]

The present invention relates to an error correction circuit for a data recording block recorded or transmitted in a storage device in a data format with an ECC (Error Correcting Code).

In a normal magnetic tape device, recording or reproducing is performed using a data recording block having a recording format (format) as shown in FIG. In the illustrated data recording block, the check character CC of each data part is at the end of the data part, and whether or not the data of each data part is correct depends on whether the check character is read or during the abnormal format, for example, in the middle of the data. It cannot be distinguished until the gap is detected.

Further, the ECC data part is collectively recorded at the end of the data recording block, and the generation of the error correction pattern is completed only after reading to the end of the data recording block.

The present invention particularly relates to an error correction circuit which reads a data recording block of such a format and automatically corrects an error.

Generally, in magnetic tape, data may drop out due to defective media such as pinholes, adhesion of dust, or poor contact on the head surface due to being a flexible medium, and data may not be output in the middle of the data section. It often happens.

Further, since the magnetic tape device is a sequential access device, the processing time will increase unless the control for continuously processing in one direction is performed.

In particular, in a streaming magnetic tape device that uses a reel-to-reel (Reel to Reel) control system, in order to read the original block again when the tape is stopped,
Since the repositioning operation takes a lot of time, immediate error correction is required.

[Conventional technology]

 FIG. 9 shows an example of a conventional error correction circuit.

In the figure, 91 is a data reading circuit such as a magnetic tape device, 92 is four data parts A in a data recording block,
Data memory for storing B, C, D, 93 is data "0" for clearing the data memory 92 with data "00"
0 is a generation circuit, 94 is an error correction circuit, 95 is an error correction pattern generation circuit composed of EOR, 96 is an error correction pattern holding circuit, and 97 is a normal data generation circuit composed of EOR.

The principle of this error correction circuit is that from ABCD = ECC, when any of A, B, C and D, for example C is an error (denoted by C '), the normal value C is (ABC'
It utilizes what is required by DECC) C '.

The data reading circuit 91 reads the data recording block 90 in the order of the data part A, B, C, D, and ECC data part,
The data is input to the data memory 92 and the error correction pattern generation circuit 95 of the error correction circuit 94.

The error correction pattern generation circuit 95 performs an EOR (exclusive OR) operation for each data section between the input read data and the content of the error correction pattern holding circuit 96, and inputs the result to the error correction pattern holding circuit 96. And update its contents. This operation is repeated, that is, A ← AB ←
By executing (AB) C ← (ABC) D ← ..., the data recording block is stored in the error correction pattern holding circuit 96.
Error correction pattern data is generated as a result of EOR accumulation between each of the 90 data parts and the ECC data part.

In the normal data generation circuit 97, after all of the data parts A, B, C and D are stored in the data memory 92, it is detected that one of the data parts (in this case, the data part C) has an error. Occasionally, the error data (C ′) and the error correction pattern ABCDECC generated in the error correction pattern holding circuit 96 are subjected to EOR operation,
The normal data (C) is generated and the error data in the data memory 92 is updated. This operation is expressed by the following equation.

(ABC'DECC) C '→ C [Problems to be solved by the invention] In the conventional error correction circuit shown in FIG. 9, since only one system of error correction pattern holding circuit is provided, error data Generate an error correction pattern including the partial data, and set the error correction pattern and error data to EO.
R calculation is performed to correct the error.

Here, when the data in the middle of the data part is lost, the total number of data in the error data part is insufficient, and the error correction pattern has the same result as when the insufficient data is replaced with the data “00”. Therefore, the data corresponding to the insufficient data length of the read error data must be "00".

However, when data is lost in this way, the data memory 92
Since the previously input data that remains in the [3] becomes apparent and the data becomes indeterminate, error correction by the ECC data becomes incorrect.

To prevent this, it is necessary to set all the contents of the data holding part to "00" before starting data reading, but at the start of reading, it is impossible to predict which part of the block will be missing. Therefore, it is necessary to initialize all the data holding areas of the data memory 92 to "00". However, since the time required for this processing is longer than the block gap passing time, the tape is stopped only when an error block (block determined to need error correction) is detected, and the data in the data memory 92 is deleted. The holding area was set to "00", the tape was repositioned to the error block, the data was read, and the error was corrected.

Therefore, there are problems that control becomes complicated and processing time increases.

The present invention provides an immediate (on the fl) method without adding extra time when read data is lost in the middle.
It is an object to provide an error correction circuit that can correct the error in y).

[Means for solving problems]

According to the present invention, in the error correction circuit, two systems of error correction pattern holding circuits for holding error correction patterns in the process of generation are provided, and the roles of the error correction pattern holding circuits are switched alternately for reading and writing by the error correction pattern generating circuit. However, when an error is detected in the input data section, the next alternate switching between reading and writing is paused, and reading / writing is executed in the same role as before, The EOR accumulated data including the error data part is not adopted, and the EOR accumulated data, that is, the error correction pattern is automatically obtained only by the data part excluding the error data part.

FIG. 1 shows the basic configuration of the present invention.

In the figure, reference numeral 10 is a data recording block, which is composed of four data parts A, B, C, D and an ECC data part in this example. Each data part and ECC data part can be independently error checked by the check character CC.

Reference numeral 11 is a data reading circuit, which inputs a read signal of a magnetic tape, for example, and outputs a data signal Data.
It also outputs a block signal Block that identifies the data portion of the data recording block 10.

Reference numeral 12 is an error detection circuit, which performs an error check with a check character CC or the like on each of the input data parts A, B, C, D and ECC data parts, and outputs an error signal Error when an error is detected. To do.

Reference numeral 13 is a data memory, and based on the data signal Data output from the data reading circuit 11, the data section A,
B, C, and D data are stored.

Reference numeral 14 is an error correction circuit targeted by the present invention.

Reference numerals 15 and 15 'are the first and second error correction pattern holding circuits, respectively.

Reference numeral 16 is an error correction pattern generation circuit, which reads from the data signal Data from the data reading circuit 11 and one of the first and second error correction pattern holding circuits 15 and 15 'which is designated for reading. To and from the data
The EOR operation is performed, and the result is written and updated in the other of the first and second error correction pattern holding circuits for which writing is designated.

A switching circuit 17 applies load / store switching signals L / S and ▲ ▼ to the first and second error correction pattern holding circuits 15 and 15 ', respectively, one for loading and the other for loading. Control for store.

This load / store switching signal L / S, ▲ ▼ is
When an error is not detected in the input data part (Error = 0), it is inverted, and the first and second error correction pattern holding circuits 15 and 1 for the next input data part are inverted.
Switch roles for loading and store for 5 '.

However, when an error is detected in the input data portion (Error = 1), the load / store switching signal is not inverted and the first and second error correction pattern holding circuits 1
The role of 5,15 'remains unchanged for the next input data part.

[Action]

The operation of the circuit of the present invention shown in FIG. 1 will be described with reference to FIG.

In FIG. 2, (a) is a data recording block. Data section A, B,
Of the C, D and ECC data parts, the data part C is shown as having an error.

(b) shows changes in the contents of the first error correction pattern holding circuit 15.

(c) shows changes in the contents of the second error correction pattern holding circuit 15 '.

(d) is a load / store switching signal L / applied to the first error correction pattern holding circuit 15 from the switching circuit 17.
The change in S is shown.

(e) shows a change of the load / store switching signal ▲ ▼ applied from the switching circuit 17 to the second error correction pattern holding circuit 15 '.

(f) shows an initialization signal (“00” clear signal) generated for the first error correction pattern holding circuit 15 during the reading period of the data section A.

(g) shows a block signal Block applied from the data reading circuit 11 to the switching circuit 12.

(h) shows an error signal Error applied from the error detection circuit 12 to the switching circuit 17.

The data lengths of the data parts A to D and ECC data part are all the same.
(n), ECC data part has EOR for each data order in each data part.
The results are recorded as shown below.

When reading, when the data of C _{n-n to} C _n is erroneous or missing, the correct data C ₁ of the data section C ₁ ,
C ₂ , ... Can be reproduced as follows.

When starting reading the data recording block, be sure that the initialization signal to the first error correction pattern holding circuit 15 is
It is turned on, and turned off when the data section A can be read correctly.
Becomes As a result, the first error correction pattern holding circuit 15 is cleared to "00".

When reading the data part A, the load / store switching signal L / S is L and the signal ▲ ▼ is S, so the read data A and “00” loaded from the first circuit 15 are read.
EOR and store the resulting A in the second circuit 15 '.

Next, when the data part A can be read normally, the error signal Error
Is OFF and the block signal Block is ON, the signal ▲
Since ▼ is L and the signal L / S is S, the data of the data section B and the error correction pattern (A) held in the second circuit 15 'are EORed and stored in the first circuit 15. To do.

When the data section B can be read normally, the load and store circuits are switched in the same manner as described above, and the read data section C and the error correction pattern (A
B) and EOR and the result (ABC) in the second circuit 1
Store at 5 '.

Next, if a dropout occurs in the middle of the data section C, an IBG (Inter Block Gap) signal (not shown) is turned on, and a short block error occurs because a gap is detected before the end of reading the predetermined data length. Error detection circuit 12
Turns on the error signal Error and holds the load / store switching signal L / S of the switching circuit 17, ▲ ▼, without inverting it.

Therefore, when reading the data section D, the error correction pattern (AB) and the data D held in the first circuit 15 are read.
EOR and store the result (ABD) in the second circuit 15 '.

Next, when the ECC data part is read, the ECC data and the error correction pattern of the second circuit 15 'are EOR'ed and written to the address corresponding to the data C in the data memory to complete the automatic error correction.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS.

FIG. 3 is a block diagram of the error correction circuit, and 30 is a drive such as a magnetic tape.

Reference numeral 31 is a serial-parallel converter that converts read data in serial format into parallel format (byte).

Reference numeral 32 is a read register that temporarily holds read data.

33 is a format error detection circuit.

34 is a CRC check circuit.

Reference numeral 35 is a block detection circuit.

36 is a data register that holds the read data, 37 is an ECC register that loads the error correction pattern, and 38 is an EOR circuit. Since the error correction pattern is sequentially updated and generated, the read data of the data register 36 and the previous time of the ECC register 37 are stored. EOR operation with the error correction pattern of.

39 is an ECC memory that holds an error correction pattern,
It is composed of two banks Bank0 and Bank1 (corresponding to the error correction pattern holding circuits 15 and 15 'in FIG. 1).

A switching circuit 40 generates a bank address for load / store control of the ECC memory 39 and an initialization signal for the ECC register 37.

41 is a data memory.

Reference numeral 42 is a block counter, which continuously generates respective block addresses indicating the storage positions of the data parts A, B, C, D in the data memory 41.

An in-block address counter 43 generates a byte address in the block (data section).

An error block address register 44 holds the block address in the data memory 41 of the block (data part) in which an error is detected.

Reference numeral 45 denotes a multiplexer MPX, which is used to sequentially write the input data of each data section to the data memory 41.
The block address output from the block counter 42 is selected, and when the error-corrected data is written, the error block address output from the error block address register 44 is selected and applied to the data memory 41 as a data bank address.

A write control circuit 46 turns on the write enable WE of the data memory 41 at the time of data write DATA WRITE of the data section A, B, C, D during the period other than ECC CYCLE and at the time of store control STORE during the ECC CYCLE period. To

47 is a lead bus.

48 is a data buffer bus.

Reference numeral 49 is a data transfer circuit to the upper device.

FIG. 4 shows the details of the circuit for generating various control signals used in the embodiment circuit of FIG. 5 to 7 show the operation timing in the embodiment circuit of FIG. 3, respectively.

FIG. 4A shows a circuit configuration including a counter shift register for generating each timing signal of the load control signal LOAD, the data write signal Data Write, and the store control signal STORE (note that FIG. 3 shows the circuit configuration). The circuit corresponding to this is omitted inside).

As shown in the figure, the read clock is divided by the counter and delayed by the shift register, so that each control signal LOA
D, Data Write and STORE are sequentially and cyclically generated as shown in (e), (g) and (i) of FIG.

FIG. 4B shows the switching circuit 40, the block counter 42, the error block address register 44, and the MPX4 shown in FIG.
5 shows the detailed configuration.

In the switching circuit 40, the JK-FF outputs the block signal Block (5th
As shown in Figure (c), the toggle operation is performed, which is alternately inverted. This JK-FF is reset by the reset signal Reset (Fig. 5 (b)) before the reading of the block is started, so it is always started at Q = 0 and Q = 1. The ECC bank address = 0 is output at the timing of the LOAD signal, and the ECC bank address = 1 is output at the timing of the STORE signal.

After that, the ECC bank address for LOAD and STORE is inverted every time Block turns ON, but when Error is ON, J
Block application to K-FF is blocked, and the toggle operation of JK-FF stops (Fig. 5, (d), (k) to (m)).

Further, D-FF is reset by Reset and then set to "1" by Block, thereby outputting an initialization signal which is turned ON only in the data section A as shown in FIG. 5 (e).

The block counter 42 is a 3-bit quinary counter
After being reset by Reset, each time a Block is applied to the block address 2 ^0, 2 ¹ "00", "01",
Outputs "10" and "11" (Fig. 5 (f), (g)), and finally ECC
Turn on the ECC CYCLE output at the timing corresponding to the data section (Fig. 5 (h)).

Error block address register 44 is detected an error in a certain data unit, when Error is turned ON, holds the block address 2 ^0, 2 ¹ at that time, the data memory 41 (FIG. 3 as an error block address ) To write modified data to.

MPX45 has block address 2 when ECC CYCLE is OFF, that is, during the reading of data section A, B, C, D.
^{0, 2 1} is selected, and select the error block address ² 0, ^{2 1} when ECC CYCLE is ON, the data bank address ² 0, ^{2 1} to the data memory 41 as a (FIG. 5 (i) ( j)).

It should be noted that FIG. 5 shows the case where the data section C has an error as in FIG. 2, and the error correction patterns shown in (m) and (o) of FIG. It is sequentially stored and loaded in each bank Bank0 and Bank1 (Fig. 3).

In FIG. 3, in the ECC memory 39, the write enable WE is ON when STORE is ON, and the output enable OE is ON when LOAD is ON.

As a result, when STORE is ON, the error correction pattern of the output of the EOR circuit 38 is stored in the bank of the ECC memory 39 designated by the ECC bank address via the data buffer bus 48, and when LOAD is ON. , The error correction pattern in the bank of the ECC memory 39 designated by the ECC bank address is loaded into the ECC register 37 via the data buffer bus 48 and enables the EOR operation with the next data section.

FIG. 6 shows the operation timing when the ECC CYCLE is OFF, and FIG. 7 shows the operation timing when the ECC CYCLE is ON.

6 and 7, (a) shows the read data held in the read register 32, and D ₁ , D ₂ , ... Are byte data, respectively.

(b) represents the transfer data on the data buffer bus 48,
D ₁ , D ₂ , ... Are read data transferred to the data register 36, E ₁ , E ₂ , ... Are data of the error correction pattern loaded from the ECC memory 39, D ₁ ′, D ₂ ′,. The read data, X, transferred to the memory 41 is the data of the error correction pattern transferred from the EOR circuit 38 to the ECC memory 39 or to the data memory 41 in the case of error correction.

(c) is a read clock.

(d) represents the read data held in the data register 36.

(e) is the load control signal LOAD.

(f) represents the data of the error correction pattern held in the ECC register 37.

(g) is a data write control signal Data Write.

(h) represents the read data stored in the data memory 41.

(i) is a store control signal STORE.

(j) is an error correction pattern held in the ECC memory 39. E ₁ ′, E ₂ ′, ... Are the error correction pattern of the ECC register 37 and the read data of the data memory 41, which are EO.
It is the updated error correction pattern of the result of R calculation.

(k) is ECC CYCLE.

〔The invention's effect〕

According to the present invention, data read by a magnetic tape device or the like is continuously checked, and even if an error is detected, the error is automatically corrected in real time without adding special control and output to a host device. Therefore, the processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is an explanatory view of the operation of the present invention, FIG. 3 is a block diagram of an error correction circuit according to an embodiment of the present invention, and FIG. 4 is an embodiment of FIG. Detailed diagrams of various control signal generating circuits, FIG. 5 is an operation timing diagram centering on control signals in the embodiment of FIG. 3, and FIG. 6 is
Operation timing diagram centered on data when ECC CYCLE is OFF, Fig. 7 is an operation timing diagram centered on data when ECC CYCLE is ON, Fig. 8 is an explanatory diagram of the recording format of the data recording block, FIG. 9 is a block diagram of an error correction circuit according to a conventional example. In FIG. 1, 10 is a data recording block, 11 is a data reading circuit, 12 is an error detection circuit, 13 is a data memory, 14 is an error correction circuit, 15 is a first error correction pattern holding circuit, and 15 'is a second. Error correction pattern holding circuit, 16 is an error correction pattern generation circuit, and 17 is a switching circuit.

Claims (1)

[Claims] 1. An exclusive OR operation function in an error correction circuit for reading a data recording block including a plurality of data parts each having a check character and an ECC data part and automatically correcting an error in the data part. The error correction pattern generation circuit (16), the first error correction pattern holding circuit (15) to which the error correction patterns output from the error correction pattern generation circuit (16) are respectively applied in parallel, and the second error The correction pattern holding circuit (15 ') and the first error correction pattern holding circuit (15) and the second error correction pattern holding each time a plurality of data parts and ECC data parts in the data recording block are sequentially input. Circuit (1
5 ′) and a switching circuit (17) capable of switching control so as to alternately load and store, and one input of the error correction pattern generation circuit (16) has a plurality of data parts of the data recording block and ECC. While sequentially applying each data in the data section, the other input is applied to the first and second error correction pattern holding circuits (15, 1).
5 ') Loads the contents of the circuit that was store-controlled immediately before, and at the same time, the error correction pattern generation circuit (16)
The output of is stored in the error correction pattern holding circuit that was under load control immediately before, and the switching circuit (17) detects the first and second errors when an error is detected in the data section input this time. An error characterized in that the control pattern switching circuit (15, 15 ') is not controlled to switch between load and store, the current control state is retained, and the data portion to be input next is processed. Correction circuit.