JPH0675716A - Auxiliary storage - Google Patents

Abstract

PURPOSE:To attain the correction of the wrong data over a wide range that can not be processed with the error correction code and with use of a single auxiliary storage by applying an RAID to an information processing system of a small scale. CONSTITUTION:An auxiliary storage 1 stores the data and corrects the data by means of the parity data. Then a parity control circuit 8 is added to the storage 1 to generate the parity data for each data contained in each of plural blocks divided from a storage area together with a parity storage circuit 10 which stores the generated parity data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used for correcting data in an auxiliary storage device. The present invention relates to an auxiliary storage device that corrects data in units of sectors or tracks.

[0002]

2. Description of the Related Art Conventionally, in the data correction of an auxiliary storage device, an error detection code is added to each arbitrary data, and an error is detected by using the error detection code at the time of reading to correct the data.

Further, by dividing the data into a plurality of auxiliary storage devices and storing the parity data of the divided data in another auxiliary storage device, a problem occurs in the auxiliary storage device storing the original data. Also made it possible to correct data (RAID LEVEL 3).

[0004]

In such a conventional data correction method using an error correction code, it is possible to correct only a few data in a series of data to which the error correction code is added, and the data of the medium can be corrected. When a large number of errors occurred in the adjacent area due to scratches or the like, it was impossible to correct them. Also,
When all the data in a specific sector or track becomes unreadable, there is a problem that all the data including the syndrome cannot be read and correction cannot be performed.

Further, when RAID level 13 is used, when the number of data divisions is small, the ratio of parity data to the total storage capacity is large and the storage device area which is not used during normal operation is large, and when the number of divisions is large. R
The minimum constitutional unit of AID becomes large, and the storage capacity of the auxiliary storage device becomes considerably larger than the required storage capacity depending on the system used. Therefore, in a small-scale information processing system regardless of the number of divisions. RAID
There was a problem that the adoption of was difficult.

The present invention solves such a problem, and an object thereof is to provide an apparatus capable of correcting error data generated in a wide range that cannot be processed by an error correction code.

[0007]

According to the present invention, there is provided an auxiliary storage device comprising storage means for holding data and a parity control circuit including means for correcting data using parity data, wherein the parity control circuit is A parity storage circuit for holding the parity data generated by the parity control circuit, including means for generating parity data for each data included in each of a plurality of blocks obtained by dividing the storage area of the storage means. Is characterized by.

A sub-parity storage circuit for storing parity data created based on data excluding the data in which the error has occurred, in a block including the data in which the error has occurred,
It is preferable that the parity control circuit includes means for writing a parity data value prepared in advance to the parity storage circuit when performing initialization for writing the same data in all storage areas.

[0009]

When writing data, the control circuit reads the data of the track n including the sector in which new data D1, ..., Dz are written and transfers it to the parity control circuit. On the other hand, the old data d1 on the parity storage circuit,
,, parity data p1 generated based on dz,
pz is also transferred to the parity control circuit. Next, writing is executed, and this write data is transferred to the parity control circuit. The parity control circuit uses the data d1, ..., Dz,
Parity data p1, ..., Pz and data d1 ,.
Parity data P1, ..., Pz is newly generated using dz.

Upon initialization of the magnetic disk, the parity control circuit, when the write disk has a specific value,
Write a specific initial value to the parity storage circuit, and if the write data is not a specific value, write the data belonging to the block in which the data was written to the data buffer,
Create a parity track from that value.

In reading data, when a read error occurs, the CPU instructs the parity control circuit to read using the parity track. In response to this instruction, the parity control circuit reads the data on the other data track of the data block to which the data track to be restored belongs and stores it in the data buffer. Also, the parity control circuit creates a sub parity track from the data on the other data tracks stored in the data buffer and the data block to which the data track to be repaired on the parity storage circuit belongs, and creates this sub parity track. The data is stored in the parity storage circuit, and the correct data is calculated using the data of this sub parity track.

As a result, the normal data can be read from the error-occurring data track after the second access without reading the data on the other data tracks.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

The embodiment of the present invention includes a control circuit 6, a data buffer 9, a magnetic disk device 7 as a storage means for holding data, and a parity control circuit 8 including means for performing data correction using parity data. The parity control circuit 8 includes means for generating parity data for each data included in each of a plurality of blocks obtained by dividing the storage area of the magnetic disk device 7, and the parity control circuit 8 generates the parity data. A parity storage circuit 10 for holding parity data is provided, and a parity control circuit 8 is further provided.
Includes means for writing a parity data value prepared in advance to the parity storage circuit 10 when performing initialization for writing the same data in all storage areas.

(First Embodiment) The first embodiment of the present invention has as many parity tracks as the number of heads of the magnetic disk device 7 for storing parity data, and is connected to the CPU 2 through the interface 3 and the inside thereof. At interface 3
Is branched into a control signal line 400 and a data bus 5, the control signal line 4 is connected to the control circuit 6, and the data bus 5 is connected to the magnetic data device 7, the parity control circuit 8, and the data buffer 9. Further, the parity control circuit 8 is connected to the parity storage circuit 10 via the memory bus 11,
The control circuit 6 is connected to the magnetic disk device 7 via the control signal line 401, connected to the parity control circuit 8 via the control signal line 402, connected to the data buffer 9 via the control signal line 403, and each operation. Is controlled.

The data in the parity storage circuit 10 must be retained even when the power of the auxiliary storage device 1 is not turned on. FIG. 2 is a schematic diagram showing a data division state of the magnetic disk device 7. This magnetic disk device 7 has x cylinders, each cylinder has y heads, and one cylinder per head. (1 per head
A cylinder is called one track) and is composed of z sectors. The entire storage area of the magnetic disk device 7 is divided into arbitrary blocks, and one parity track is generated for each block. Each parity track has the same data length as the track length of the magnetic disk device 7.

An example of creating parity data to be stored in the parity track will be described with reference to FIG. In this example, the entire storage area is divided into the same number of blocks as the number of heads. When preparing the same number of parity tracks as the head number z, one parity track is generated from the same number of tracks T1, T2, ..., Tx as the number of cylinders x. Each track is composed of z sectors, and the data of the nth sector of an arbitrary track T1 is D.
If it is written as 1n, the data Pn of the nth sector of the parity track is the exclusive OR of the data forming the nth sector of the tracks T1, T2, ..., Tx assigned to the parity track. Become. That is,

[0018]

[Equation 1] Need to save.

At this time, instead of dividing tracks using the same head into blocks as shown in FIG. 3, by shifting the heads into blocks, it is possible to eliminate the influence of scratches on the medium in the cylinder direction due to vibration and the like. Is preferred.

Next, the circuit operation of the auxiliary storage device 1 having such a parity track will be described. C
When writing data from the PU 2 to an arbitrary sector on the magnetic disk device 7, the control circuit 6 reads the data on the track n including the arbitrary sector from the magnetic disk device 7 before writing the data to the magnetic disk device 7. Transfer data to. At the same time, the data p1, p2, ..., Pz of the parity track Pn generated from the data of the track n from the parity storage circuit 10 are also sent to the parity control circuit 8. After the data transfer is completed, the control circuit 6 requests the CPU 2 for the write data, and the sent write data is written on the magnetic disk device 7 and also sent to the parity control circuit 8.

The parity control circuit 8 writes the old data d1, d2, ... Dz of the track n, which has been written in advance, and the p1, p2, ..., Pz of the parity data generated by this d1, d2 ,. , Dz to be written next to the parity track Pn using the written data D1, D2, ... Dz.
Is generated and written back to the parity storage circuit 10. On this occasion,
New parity data P1, P2, ..., Pz can be generated by the following equations.

[0022]

[Equation 2] Although an alternative sector and an alternative track are prepared for replacement when a problem occurs in the normal storage area, if this replacement processing occurs, the data in the replaced area cannot be used. It is necessary to carry out the processing assuming that all the data in the designated area are "1". In addition, all the data in the alternative areas that are not used are regarded as "0". When the magnetic disk device 7 is initialized, it is not necessary to create the parity track data from the actually written data. That is, since a specified value in all storage areas is written in the initialization, the data of the parity track is a repetition of a certain value. Therefore, during the initialization work, the parity control circuit 8 may directly write the specific initial value to the parity storage circuit 10. Note that the parity track data needs to be rewritten only in the area where the alternative process has been performed.

When the data to be written is not a specific value and is initialized, the data is once written in all the storage areas, and then the data belonging to the same block is written in the data buffer 9,
It is necessary to create a parity track from that value.

Next, a method of reading data will be described. In the normal state, read data is sent to the CPU 2 via the data bus 5 and the interface 3 by the control circuit 6 accessing the magnetic disk device 7 in accordance with the instruction from the CPU 2. However, if the read operation is abnormal or a multi-bit data error occurs, the CPU 2 instructs the control circuit 6 to correct the data using the parity track. The control circuit 6 is the CPU 2
When instructed to read using the parity track, all the other data tracks existing in the same block as the data track to be restored are read and stored in the data buffer 9.

The parity control circuit 8 stores the data of another data track written in the data buffer 9 and the defective data track in the parity track generated from the data block including the data track to be corrected read from the parity storage circuit 10. Generate data and.

In this reading method, in order to generate the data in the data track in which an error has occurred, it is necessary to read all the data of the other data tracks existing in the same block, so the data of one track is read. Takes time.

(Second Embodiment) The second embodiment of the present invention is intended to speed up the reading of error data tracks in the first embodiment, and a plurality of tracks are used to generate data in one parity track. Data is used. Therefore, in order to correct the data of the arbitrary data track by the parity track, it is necessary to read all the data tracks used for generating the same parity track as the data track to be corrected, and in order to prevent this, in the second embodiment, As shown in FIG. 4, the parity of the data in another data track used for modifying the data track is held in the memory, and the parity control circuit 8 is connected to the sub parity storage circuit 12 via the memory bus 11. Although the data writing and the initialization operation from the CPU 2 are performed in the same manner as the first embodiment, the read operation when an error occurs can be speeded up by performing the following operation.

When the control circuit 6 is instructed by the CPU 2 to read an arbitrary data track in which an error has occurred,
The control circuit 6 reads all the data blocks located in the same block as the data track in which the error has occurred,
A new parity track is generated by a data track other than the data track in which the error has occurred, and is used as a sub parity track. The sub parity track is stored in the sub parity storage circuit 12 by the parity control circuit 8.
The data of the sub parity track is S1, S2, ..., Sz
If so, the correct data Dt1, Dt2, ..., Which should have been written in the data track in which the error has occurred,
Dtz can be obtained by performing the following calculation inside the parity control circuit 8.

[0029]

[Equation 3] As a result, a sub parity track corresponding to the data track in which an error has occurred is generated, and the sub parity storage circuit 1
The data can be stored in No. 2 and the normal data read operation from the error data track can be performed at high speed without reading other data tracks after the second access.

[0030]

As described above, according to the present invention, the entire storage area can be divided into arbitrary blocks and the parity of the data contained in each block can be stored separately, and a single auxiliary storage is also provided. Even in equipment, it is possible to correct a wide range of data that cannot be processed by error correction codes.
This has the effect of improving the data reliability of the auxiliary storage device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of a storage area form in the first embodiment of the present invention.

FIG. 3 is a conceptual diagram showing an example of parity track generation in the first embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a second embodiment of the present invention.

[Explanation of symbols]

 1 Auxiliary storage device 2 CPU 3 Interface 5 Data bus 6 Control circuit 7 Magnetic disk device 8 Parity control circuit 9 Data buffer 10 Parity storage circuit 11 Memory bus 12 Sub parity storage circuit 400, 401, 402, 403 Control signal line

Claims (3)

[Claims] 1. An auxiliary storage device comprising storage means for holding data and a parity control circuit including means for correcting data using parity data, wherein the parity control circuit stores a storage area of the storage means. An auxiliary storage device comprising a parity storage circuit that includes a unit that generates parity data for each data included in each of a plurality of divided blocks and that holds the parity data generated by the parity control circuit. 2. The auxiliary storage device according to claim 1, further comprising a sub-parity storage circuit for storing parity data created based on data excluding the data in which the error has occurred, in a block including the data in which the error has occurred. 3. The parity control circuit comprises means for writing a parity data value prepared in advance to the parity storage circuit when performing initialization for writing the same data in all storage areas. Auxiliary storage device.