JPH01107566A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH01107566A JPH01107566A JP62264390A JP26439087A JPH01107566A JP H01107566 A JPH01107566 A JP H01107566A JP 62264390 A JP62264390 A JP 62264390A JP 26439087 A JP26439087 A JP 26439087A JP H01107566 A JPH01107566 A JP H01107566A
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- iil
- injector
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000003321 amplification Effects 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Abstract
Description
【発明の詳細な説明】 (イ)産業上の利用分野 。[Detailed description of the invention] (b) Industrial application field.
本発明は半導体装置、特にIILとその入力トランジス
タを同一島領域に集積化した半導体装置に関する。The present invention relates to a semiconductor device, and particularly to a semiconductor device in which an IIL and its input transistor are integrated in the same island region.
(ロ)従来の技術
I I L (Integrated Injecti
on Logic)は一般のバイポーラ型ICに組み込
み可能な論理回路素子であり、低消費電力、高速動作、
素子分離が不要である等の特徴を有する。その構造は、
通常のコレクタをエミッタとする逆方向構造のインバー
タNPNトランジスタとこのトランジスタのベースをコ
レクタとする横方向構造のインジェクタPNP)ランジ
スタとの複合構造を有する。(b) Conventional technology I I L (Integrated Injecti)
on Logic) is a logic circuit element that can be incorporated into general bipolar ICs, and has low power consumption, high-speed operation,
It has features such as no need for element isolation. Its structure is
It has a composite structure of an inverter NPN transistor with an inverted structure whose emitter is the normal collector and an injector PNP transistor with a lateral structure whose collector is the base of this transistor.
ところで、バイポーラリニア回路からの信号を入力しI
ILで信号処理する場合、IILのインバータトランジ
スタと同一構造の入力トランジスタを介しIIL論理回
路へ入力している。この時前記入力トランジスタにはI
ILのインジェクタトランジスタを形成してはならない
、なぜならば、バイポーラリニア回路の出力端子が“L
”の時前記インジェクタトランジスタのインジェクタ電
流の一部が前記大カートランジスタのベースに流入し前
記入力トランジスタを誤動作きせてしまう為である。そ
の為、前記入力トランジスタをIILとは別個のアイラ
ンドに形成していた。By the way, if you input the signal from the bipolar linear circuit,
When processing signals in the IL, the signals are input to the IIL logic circuit via an input transistor having the same structure as the inverter transistor of the IIL. At this time, the input transistor has I
The injector transistor of IL must not be formed because the output terminal of the bipolar linear circuit is “L”.
This is because when ``, a part of the injector current of the injector transistor flows into the base of the large Kerr transistor and causes the input transistor to malfunction.Therefore, the input transistor is formed on an island separate from the IIL. was.
斯上した構造を第411!Jに示す、同図において、(
1)はP4型の分離領域、(2)(3)はN型のアイラ
ンド、(4)はIIL、(りは入力トランジスタ、(6
)はI I L(4)のP型インジェクタ領域、(7)
はIIL(りのP型ベース領域、(8)はIILす)の
N+型フレクタ領域、(9)は入力トランジスタ(互)
のP型ベース領域、(10)は入力トランジスタ(塁)
のN+型コレクタ領域である。尚、IILとしては例え
ば特開昭59−145563号公報等で公知である。The above structure is the 411th! In the figure shown in J, (
1) is a P4-type isolation region, (2) and (3) are N-type islands, (4) is an IIL, (is an input transistor, and (6) is an N-type island.
) is the P-type injector region of I I L (4), (7)
is the P-type base region of the IIL, (8) is the N+-type deflector region of the IIL, and (9) is the input transistor (mutual).
P-type base region of , (10) is input transistor (base)
This is the N+ type collector region of . Incidentally, IIL is known from, for example, Japanese Patent Laid-Open No. 145563/1983.
(ハ)発明が解決しようとする問題点
しかしながら、従来の構造はI I L(4)と入力ト
ランジスタ(すを夫々単独アイランド(2)(3)に形
成している為、占有面積が大である欠点があった。(c) Problems to be solved by the invention However, in the conventional structure, the IIL (4) and the input transistor (s) are formed on individual islands (2) and (3), respectively, so the occupied area is large. There was a certain drawback.
(ニ)問題点を解決するための手段
本発明は斯上した欠点に鑑みてなされ、IIL(ν)と
入力トランジスタ(麩)を同一アイランド(15)に組
み込むと共に、IIL(■)のインジェクタ領域(16
)と入力トランジスタ(ハ)のベース領域(20)の間
にN+型のカラー領・域(24)を形成し、インジェク
タ領域(16)からの注入電流を抑制したことを特徴と
する。(d) Means for solving the problems The present invention has been made in view of the above-mentioned drawbacks, and it incorporates the IIL (ν) and the input transistor (fu) into the same island (15), and also incorporates the injector area of the IIL (■). (16
) and the base region (20) of the input transistor (c), an N+ type collar region (24) is formed to suppress the injection current from the injector region (16).
(*)作用
本発明によれば、カラー領域(24)を設けることによ
ってIIL(■)のインジェクタ領域(16)とアイラ
ンド(15)と入力トランジスタ(2X)とで形成する
寄生のインジェクタトランジスタのα(電流増 ′幅率
)が大幅に低下する。その為、インジェクタ領域(16
)から入力トランジスタ(ハ)のベース領域(20)へ
の注入電流、を抑1制することができる。(*) Effect According to the present invention, by providing the collar region (24), the parasitic injector transistor α formed by the injector region (16), island (15), and input transistor (2X) of the IIL (■) (current amplification rate) decreases significantly. Therefore, the injector area (16
) to the base region (20) of the input transistor (c) can be suppressed.
(へ)実施例 以下、本発明を図面を参照しながら詳細に説明する。(f) Example Hereinafter, the present invention will be explained in detail with reference to the drawings.
第1図及び第2図は夫々本発明の半導体集積回路を示す
平面、図及び断面図である。同図において、(11)は
P型半導体基板、(12)は基板(11)全面に積層し
て形成したN型エピタキシャル層、(13)は基板(1
1)表面に形成したN”型埋込層、(14)はエピタキ
シャル層(12)を貫通するP′″型分離領域、<15
)は分離領域(14)によって島状に形成したアイラン
ド、(16)はアイランド(15)表面に設けたIIL
(■)のP型インジェクタ領域、(18)はインジェク
タ領域(16)の両脇にインジェクタトランジスタのベ
ース幅分だけ離間して等間隔に並設したI I L(1
7)(7)P型ベース領域、(19)はI I L(1
7)のベース領域(18)表面に車数側又は複数個形成
したN”型ノフレクタ領域、(20)はI I L(1
7>と同じアイランド(15)表面に形成した入力トラ
ンジスタ(ハ)のP型ベース領域、<22)は入力トラ
ンジスタ(ハ)のベース領域(20)表面に形成したN
゛型のコレクタ領域、(23)はアイランド(15)表
面のベース領域(18)(2G)とインジェクタトラン
ジスタのベースとなる領域を除く領域に形成したインバ
ータトランジスタ間の寄生防止とキャリア蓄積効果抑制
及びアイランド(15)への接地電位印加の為のN+型
カラー領域である。−IIL(■)のインジェクタトラ
ンジスタはインジェクタ領域(16)をエミッタ、アイ
ランド(15)をベース、IIL(■2のベース領域(
18)をコレクタとするベース接地型のラテラルPNP
)ランジスタ・で、IIL(■)のインバータトラン
ジスタと入力トランジスタ(2X)はアイランド(15
)をエミッタとするエミッタ接地型の逆方向縦型NPN
トランジスタで構成する。FIGS. 1 and 2 are a plan view, a diagram, and a sectional view, respectively, showing a semiconductor integrated circuit of the present invention. In the figure, (11) is a P-type semiconductor substrate, (12) is an N-type epitaxial layer laminated over the entire surface of the substrate (11), and (13) is a substrate (1).
1) N'' type buried layer formed on the surface, (14) is a P'' type isolation region penetrating the epitaxial layer (12), <15
) is an island formed into an island shape by the separation region (14), and (16) is an IIL provided on the surface of the island (15).
(■) is a P-type injector region, and (18) is an I I L (1
7) (7) P-type base region, (19) is I I L (1
7) N" type no reflector region formed on the surface of the base region (18) on the vehicle number side or in plural numbers, (20) is I I L (1
The P type base region of the input transistor (C) formed on the same island (15) surface as in 7>, and the N type base region formed on the base region (20) of the input transistor (C) in <22).
The collector region (23) of the ゛ type is used to prevent parasiticism between the inverter transistors formed in the region excluding the base region (18) (2G) on the surface of the island (15) and the region that becomes the base of the injector transistor, suppress the carrier accumulation effect, and This is an N+ type collar area for applying a ground potential to the island (15). - The injector transistor of IIL (■) uses the injector region (16) as the emitter, the island (15) as the base, and the base region of IIL (■2) (
Base-grounded lateral PNP with collector as 18)
) transistor, the inverter transistor of IIL (■) and input transistor (2X) are island (15
) is the emitter grounded reverse vertical NPN.
Consists of transistors.
そして本願の特徴とする如く、IIL(■)のインジェ
クタ領域(16)と入力トランジスタ(ハ)のベース領
域(20)との間のアイランド(15)表面にもカラー
領域(24)を設け、カラー領域(23)(24)が入
力トランジスタ(麩)のベース領域(20)を囲むよう
に形成する。アイランド(15)は最多のコレクタ領域
(19)を有するIIL(■)のベース領域(18)の
大きさに対応しているので、好ましくは入力トランジス
タ(以)のベース領域(20)をインジェクタ領域(1
6)から後退させ両者の離間距離を拡大するのが良い。As a feature of the present application, a collar region (24) is also provided on the surface of the island (15) between the injector region (16) of the IIL (■) and the base region (20) of the input transistor (c). Regions (23) and (24) are formed to surround the base region (20) of the input transistor (fu). Since the island (15) corresponds to the size of the base region (18) of the IIL (■) with the largest number of collector regions (19), it is preferable to use the base region (20) of the input transistor (below) as the injector region. (1
It is better to move back from 6) and increase the distance between them.
第3図は本願構造の等価回路を示す、 (3G)はPN
P)ランジスタ(31)とNPNトランジスタ(32)
から成るリニア回路、(33)は入力トランジスタ、(
34)は次段IIL(■)のインジェクタトランジスタ
、(35)はインジェクタ領域(16)とアイランド(
15)と入力トランジスタ(2X)のベース領域(20
)から成る寄生のインジェクタトランジスタであり、P
NPトランジスタ(31)がON、NPN)ランジスタ
(32)がOFFの時入力トランジスタ(33)がON
し、その逆の場合がOFFする様な構成である。Figure 3 shows the equivalent circuit of the structure of the present application, (3G) is PN
P) Transistor (31) and NPN transistor (32)
A linear circuit consisting of (33) is an input transistor, (33) is an input transistor, (
34) is the injector transistor of the next stage IIL (■), (35) is the injector region (16) and the island (
15) and the base region (20
) is a parasitic injector transistor consisting of P
When the NP transistor (31) is ON and the NPN transistor (32) is OFF, the input transistor (33) is ON.
However, the configuration is such that the switch is turned off in the opposite case.
斯上した本願構造によれば、ベースに高不純物濃度のカ
ラー領域(24)を形成したので、インジェクタ領域(
16)から注入された注入電流の大部分は接地電位へ逃
げ、寄生のインジェクタトランジスタ(35)のα(電
流増幅率)は正規のインジェクタトランジスタ(34)
のものより極めて小さくなる。According to the above structure of the present invention, since the color region (24) with high impurity concentration is formed in the base, the injector region (24) is formed in the base.
Most of the injection current injected from 16) escapes to the ground potential, and α (current amplification factor) of the parasitic injector transistor (35) is equal to that of the regular injector transistor (34).
It is much smaller than that of .
その為、インジェクタ領域(16)から入力トランジス
タ(ハ)のベース領域(20)へ注入される注入電流を
抑制し、NPNトランジスタ(32)が08時の入力ト
ランジスタ(33)の誤動作を肪止できる。Therefore, the injection current injected from the injector region (16) to the base region (20) of the input transistor (c) is suppressed, and the NPN transistor (32) can prevent malfunction of the input transistor (33) at 08:00. .
(ト)発明の詳細
な説明した如く、本願によれば同一アイランド(15)
内にIIL(■)と入力トランジスタ(≦1)とを集積
化できるので、占有面積を縮、#11できる利点を有す
る。また、IIL(■)は極めて小さい電圧で駆動する
ので、カラー領域(24)とベース領域(20)やイン
ジェクタ領域(16)等は拡散領域の境を接する様に形
成でき、カラー領域(24)を設けたことによるアイラ
ンド(15)の面積増大は無い。さらにカラー領域(2
3)(24)はフレフタ領域(19)と共にNPN)ラ
ンジスタのエミッタ拡散工程で形成できるので、特に設
計変更を要しない利点をも有する。(G) As described in detail of the invention, according to the present application, the same island (15)
Since the IIL (■) and the input transistor (≦1) can be integrated within the device, the occupied area can be reduced and has the advantage of #11. In addition, since the IIL (■) is driven with an extremely small voltage, the color area (24), base area (20), injector area (16), etc. can be formed so as to touch the boundary of the diffusion area, and the color area (24) There is no increase in the area of the island (15) due to the provision of the island (15). In addition, the color area (2
3) Since (24) can be formed together with the flapter region (19) in the emitter diffusion process of an NPN transistor, it also has the advantage of not requiring any particular design change.
第1図乃至第3図は夫々本発明を説明する為の平面図、
断面図及び回路図、第4図は従来例を説明する為の平面
図である。
(15)はアイランド、 (16〉はIIL(■)の
インジェクタ領域、(1B)はIIL(■)のベース領
域、(20)は入力トランジスタ(ハ)のベース領域、
(23)(24)はカラー領域である。1 to 3 are plan views for explaining the present invention, respectively;
A sectional view and a circuit diagram, and FIG. 4 is a plan view for explaining a conventional example. (15) is the island, (16> is the injector region of IIL (■), (1B) is the base region of IIL (■), (20) is the base region of the input transistor (c),
(23) and (24) are color areas.
Claims (1)
入力トランジスタとを組み込み、前記IILのインジェ
クタ領域と前記入力トランジスタのベース領域との間に
前記ベース領域とは逆導電型のカラー領域を設けて前記
インジェクタ領域から前記ベース領域へのインジェクタ
電流の注入を抑制したことを特徴とする半導体集積回路
。(1) An IIL and an input transistor with a reverse vertical structure are incorporated in one island, and a collar region of a conductivity type opposite to the base region is provided between the injector region of the IIL and the base region of the input transistor. What is claimed is: 1. A semiconductor integrated circuit characterized in that the semiconductor integrated circuit is provided to suppress injection of an injector current from the injector region to the base region.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62264390A JPH01107566A (en) | 1987-10-20 | 1987-10-20 | Semiconductor integrated circuit |
KR1019880013545A KR910009424B1 (en) | 1987-10-20 | 1988-10-17 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62264390A JPH01107566A (en) | 1987-10-20 | 1987-10-20 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01107566A true JPH01107566A (en) | 1989-04-25 |
Family
ID=17402490
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62264390A Pending JPH01107566A (en) | 1987-10-20 | 1987-10-20 | Semiconductor integrated circuit |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH01107566A (en) |
KR (1) | KR910009424B1 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57167671A (en) * | 1981-04-08 | 1982-10-15 | Hitachi Ltd | Semiconductor integrated circuit |
-
1987
- 1987-10-20 JP JP62264390A patent/JPH01107566A/en active Pending
-
1988
- 1988-10-17 KR KR1019880013545A patent/KR910009424B1/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57167671A (en) * | 1981-04-08 | 1982-10-15 | Hitachi Ltd | Semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
KR890007428A (en) | 1989-06-19 |
KR910009424B1 (en) | 1991-11-15 |
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