JPS6130752B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a semiconductor device, and particularly to an IIL.
The present invention relates to an improvement of a semiconductor device that constitutes an injection type logic element called (Integrated Injection Logic).

Recently, bipolar LSI products by IIL have been announced one after another. IIL has excellent features such as high density and low power consumption, and is an injection type logic element that is expected to be further developed in the future.

FIG. 1 is a sectional view showing the basic inverter structure of a normal IIL.

In the figure, 1 is an n ⁺ type substrate, 2 is an n type semiconductor layer epitaxially grown on one main surface of this n ⁺ type substrate 1, and 3 is an n type semiconductor layer selectively formed within this n type semiconductor layer 2. A first P-type region 4 is located at a predetermined distance from the first P-type region 3 in the n-type semiconductor layer 2.
A second P-type region, 5 and 6, selectively formed within said second P-type region 4 and a first n ⁺ -type region selectively formed within said second P-type region 4 are separated from each other.
n ⁺ type area, 7 is the power terminal, 8 is the input terminal, 9
is a first output terminal, 10 is a second output terminal, the n-type semiconductor layer 2 is an emitter, the second P-type region 4 is a base, and the first and second n ⁺ type regions 5, 6
A reverse vertical npn transistor 11 operates with the emitter as the collector and the emitter is grounded, the first P-type region 3 is the emitter, the n-type semiconductor layer 2 is the base, and the second P-type region 4 is the collector and the base is grounded. , a horizontal pnp transistor 12 for supplying a constant base current to the npn transistor 11.
is made up of.

As shown in the figure, the base and emitter of the npn transistor 11 are configured to share the same regions as the collector and base of the pnp transistor 12, respectively, and are structurally complex and simplified.

Note that the emitter 3 of the pnp transistor 12 is also called an injector. This is as mentioned above
This is because the pnp transistor 12 serves as a constant current source for the base current of the npn transistor 11.

The basic differences between an IIL having such a configuration and a conventional bipolar IC are as follows.

(a) There is no need to separate elements.

(b) The emitter and collector of the npn transistor 11 are reversed compared to conventional ICs.

(c) The emitter is common to the n ⁺ type substrate 1.

(d) Since the pnp transistor 12 serves as a current supply source, no resistor is required.

(e) IIL and conventional bipolar IC can be integrated on the same board.

FIG. 2 shows an equivalent circuit of the IIL having the configuration shown in FIG. In order for a system configured with IIL to operate stably, the output current absorption capacity of the npn transistor 11, which is an operating condition for this basic circuit, must be sufficient to bring the IIL connected to the next stage into a cut-off state. It is capable of absorbing current. this is,
Composite current amplification factor α when viewed from injector 3
_H・βu (injection rate α _H of pnp transistor 12 and
The product of the current amplification factor βu of the npn transistor 11) needs to be at least 2 or more, and the larger this value is, the more stable the operation will be, and the more similar basic circuits can be connected to the next stage.

However, in the conventional IIL, the impurity concentration of the emitter 2 of the reverse vertical NPN transistor 11 is 10 ¹⁴ cm ^-3
Since the impurity concentration gradient in the base 4 is high toward the collectors 5 and 6, a reverse electric field is generated inside the base 4, and the travel time of the carrier becomes longer due to the reverse drift effect. , current amplification factor βu of the reverse vertical npn transistor 11
It had the disadvantage that the value was significantly reduced. Then IIL
The problem when incorporating the injector into a system is its operating frequency, but in the low current operating region, it is determined by the charging and discharging time of the charge accumulated in the depletion layer capacitance formed at the junction. The operating speed increases in proportion to the injected current. but,
When the current exceeds a certain level, in the conventional IIL, βu of the reverse vertical npn transistor 11 is low;
IIL had the disadvantage of reaching a low inherent operating frequency.

This invention was made to eliminate the above-mentioned drawbacks of the conventional IIL. In order to increase the current amplification factor βu of the reverse direction vertical transistor, a horizontal transistor serving as a driver is added and connected to the Darlington. Using the product βd・βu of the current amplification factor βd of the horizontal transistor and the current amplification factor βu of the vertical transistor, the composite current amplification factor α of IIL is calculated.
The purpose is to significantly increase _H , βd, and βu to provide IIL with lower power consumption and higher speed than conventional ones.

Hereinafter, an embodiment of the IIL according to the present invention will be described along with a manufacturing method thereof with reference to the drawings.

First, as shown in Figure 3, the impurity concentration is about 5
An n-type semiconductor layer 2 is epitaxially grown on an n ⁺ -type substrate 1 with a crystal axis direction <111> of x10 ¹⁸ cm ^-3 . The impurity concentration of this n-type semiconductor layer 2 is 3.5×
10 ¹⁴ cm ^-3 and the thickness was 27.2 μ.

Next, as shown in Figure 4, boron is introduced into the n-type semiconductor layer 2 at an impurity surface concentration by simultaneous selective diffusion.
10 ¹⁸ cm ^-3 to form first, second and third P-type regions 3, 4 and 13 spaced apart from each other.

Next, as shown in FIG. 5, phosphorus is introduced into the second and third P-type regions 4 and 13 at an impurity surface concentration of about 10 ²¹ cm ^-3 by simultaneous selective diffusion. Then, second n ⁺ -type regions 5 and 6 and third and fourth n ⁺ -type regions 14 and 15 are formed.

In this way, the n-type semiconductor layer 2 is formed into an emitter,
The second P-type region 4 is the base, the first and second
A reverse vertical npn transistor 11 with the n ⁺ type region as the collector, and the first P type region 3 as the emitter,
A lateral pnp transistor 12 having an n-type semiconductor layer 2 as a base and a third P-type region 13 as a collector, a third n ⁺ -type region 14 as a collector, a third P-type region 13 as a base, and a fourth n A lateral nPn transistor 16 having the ⁺ -type region 15 as an emitter is configured.

Next, as shown in FIG ^. 15 is provided with an aluminum electrode, for example, and the electrodes provided in the first P-type region 3 and the third P-type region 13 are used as the power supply terminal 7 and the input terminal ⁸ , respectively. The electrodes provided in the third n ⁺ type region 14 are connected in common to form the first output terminal 9.
In addition, the electrodes provided in the second n ⁺ type region 6 and the third n ⁺ type region 14 are commonly connected to form the second output terminal 10, and the second P type region 4 and the fourth
The electrodes provided in the n ⁺ type region 15 are commonly connected.

With such a connection, the horizontal npn transistor 16 is connected to the driver stage, and the vertical npn transistor 11 is connected to the driver stage.
A Darlington connection is achieved with the IIL in the output stage, and the equivalent circuit of the IIL shown in FIG. 6 becomes as shown in FIG.

According to the IIL having such a configuration, if the current amplification factor of the horizontal npn transistor 16 is βd (>>1), then the vertical npn in the conventional IIL shown in FIG.
β is higher than the current amplification factor βu of transistor 11 alone.
Current amplification factor βd/βu that is more than one order of magnitude higher by d times
can be easily obtained without adding any extra manufacturing steps, making it possible to significantly reduce power consumption and speed up IIL.

In the above embodiment, an IIL was described in which a horizontal pnp transistor is used as an injector, a horizontal npn transistor is used as a driver stage, and a vertical npn transistor in the opposite direction is used as an output stage. It may be an IIL in which a reverse direction pnp transistor is used as an output stage, and the same effect as in the above embodiment can be achieved.

As described above, according to the present invention, it is possible to greatly improve βu of the reverse direction vertical transistor, so it is possible to realize high speed IIL with extremely low power consumption.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing the basic inverter structure of a conventional IIL, Fig. 2 is its equivalent circuit diagram, and Figs. 3 to 6 are sectional views showing main steps of an embodiment of the present invention together with its manufacturing method. , FIG. 7 is an equivalent circuit diagram of an embodiment of the present invention. In the figure, 1 is an n ⁺ type substrate, 2 is an n-type semiconductor layer, 3 is a first P-type region, 4 is a second P-type region,
5 is the first n ⁺ type area, 6 is the second n ⁺ type area, 1
1 is a reverse vertical npn transistor, 12 is a horizontal type
pnp transistor, 13 third P-type region, 14
is the third n ⁺ type area, 15 is the fourth n ⁺ type area, 1
6 is a horizontal npn transistor. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 first, second and third second conductivity type regions formed separately from each other on the surface of the first conductivity type semiconductor layer; and a second conductivity type region separated from each other on the surface of the second second conductivity type region. and third and fourth first conductivity type regions formed separately from each other on the surface of the third second conductivity type region. , a horizontal first transistor is formed with the first second conductivity type region as an emitter, the semiconductor layer as a base, and the second second conductivity type region as a collector;
and forming a horizontal second transistor with the second first conductivity type region as an emitter and collector, the second second conductivity type region as a base, the semiconductor layer as an emitter, and a third second conductivity type region as a base; A semiconductor device in which a vertical third transistor is formed using the third and fourth first conductivity type regions as collectors, and the second transistor and the third transistor are connected in a Darlington connection.