JPH01107376A - System for detecting synchronizing signal - Google Patents

Abstract

PURPOSE:To highly secure prediction precision and to secure the detection of a synchronizing signal by executing plural prediction countings in parallel at the time of detecting the synchronizing signal and sequentially taking precedence over and adopting the prediction countings from reference parts in positions near the synchronizing signal. CONSTITUTION:Plural reference parts are provided in one and the same sector. At the time of reading the reference parts, counters A36 and A37 respectively start prediction counting the position of the synchronizing signal. The prediction countings from the reference parts in the positions near the synchronizing signal SYZC3 are taken with priority and adopted, and the detecting time range of the synchronizing signal is controlled by the prediction counting. Namely, plural prediction countings are executed in parallel and the prediction counting from the reference parts in the positions near the synchronizing signal are sequentially taken with priority and adopted among plural prediction countings. Thus, prediction precision can highly be secured and the detection of the synchronizing signal can securely be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to detection of synchronization signals, and particularly to a synchronization signal detection method that can detect synchronization signals indicating the beginning position of a data portion with high accuracy.

[Conventional technology]

BACKGROUND ART In data transfer technology, it is known to detect the leading position of data to be transferred and perform synchronization control to prevent data transfer errors.

Examples of the synchronization signal detection technology for detecting such synchronization signals that arrive at a predetermined period include Japanese Patent Laid-Open No. 61-177678 and Japanese Patent Laid-Open No. 61-177.
There is a publication No. 679.

The above-mentioned document discloses a technique for preventing synchronization signal detection errors by controlling the detection period according to a signal obtained within a predetermined period including the scheduled time when the synchronization signal should originally be obtained when detecting the synchronization signal. Disclosed.

[Problem that the invention seeks to solve]

However, in the above technology, if the actual synchronization signal deviates from the scheduled timing of synchronization signal detection, the synchronization signal may become undetectable, which may result in detection errors such as non-detection of the synchronization signal. This was discovered by the present inventor.

The present invention has been made focusing on the above problems,
The purpose is to provide a technique that can reliably detect synchronization signals.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, a plurality of reference points are provided in the same sector, and when these reference points are read, a predictive count of the synchronization signal position is started independently, and among these, the prediction count of the synchronization signal position from the reference point at the nearest position of the synchronization signal is counted. The predicted count is adopted with priority, and the synchronization signal detection time range is controlled using the predicted count.

[Effect]

According to the above-mentioned means, a plurality of prediction counts are performed in parallel, and among these prediction counts, the prediction counts from the reference point located near the synchronization signal are sequentially adopted with priority, so that the prediction accuracy is improved. The synchronization signal can be detected reliably.

〔Example〕

FIG. 1 is a block diagram showing the control logic of a control device for an optical disk system that switches the detection gate width of a synchronization signal, which is an embodiment of the present invention, and FIG. 2 is an overall diagram of the optical disk system, which is an embodiment of the present invention. FIG. 3 is an explanatory diagram showing the configuration of the optical disc system.

In FIG. 2, 1 is an optical disk controller (OFC);
2 indicates an optical disk drive device (ODD), and during OFCI data reading operation, 0DD
2 is read data 3. Lead clock 4. A sector mark signal 5 and a write clock 6 are sent to the OFC 1.

Here, the data format of one sector on the optical disk medium in this embodiment has the configuration shown in FIG. 2, and in FIG. The first synchronization signal 5YN in this embodiment indicates the beginning position of the first ID field (IDI) of the VFO1 in which the VFO pattern is written.
CI is located. Subsequently, it is further divided into a track number 11a, a sector number 12a, and a CRC 13a as an error check code, which constitute the IDI. Furthermore, following VFO2, a second ID field (ID2
> second synchronization signal 5YNC2, ID2 indicating the start position of
It is divided into a track number 11b, a sector number 12b, and a CRC 13b as an error check code. Next to ID2 is FLAG21+ surrounded by gap 20 and gap 22, :: Continued, FV
O3 and a third synchronizing signal 5YNC3 indicating the beginning position of data 25, and following this, data 25 in which user data is written.

As is clear from the explanation of FIG. 3, accurate detection of the synchronization signal 5YNC3 for reading the data 25 is important in reading the data 25, and in this embodiment, the three sector marks 7.1DI and ID2 are detected. Functions as a reference point.

FIG. 1 shows a control circuit of an optical disk control device OFCI. In the figure, 30 is a shift register, 31
38 is a synchronous signal detection circuit, 38 is a demodulation circuit, 39 is a CRC check circuit, and 40 is an ID check circuit. In this embodiment, in addition to the above circuit configuration, an IDI
and a counter A36 that controls reading of ID2 and starts predictive counting based on sector mark signal 5, and counter B37 that starts predictive counting based on reading of IDI or ID2.

In addition, 33 and 42 are flip-flops, and 4
1 indicates a selector that switches the counter. Furthermore, 34 is an OR gate, 32 and 35 are each AN
D gate is shown, each of these games) 32, 34.3
5 constitutes a gate circuit G (range indicated by a broken line in FIG. 3) corresponding to the detection time range of the synchronizing signal 5YNC3 in this embodiment.

In FIG. 1, read data 3 and a read clock 4 are input to a shift register 30, and the read data 3 is shifted out by the read clock 4. The output is input to the synchronization signal detection circuit 31, and the synchronization signal 5Y
NC1, 5YNC2 and 5YNC3 are detected, respectively, and the detection outputs are input to the AND gate 32.

On the other hand, both counters A36 and B37 are counted by the write clock 6, and among these, - counter A3
Counter B37 starts counting when sector mark signal 50 is input, and counter B37 starts counting when sector mark signal 50 is input.
Counting starts upon detection of NC2.

The counter A36 outputs the IDI area signal 51 and the 102 area signal 52 to the OR gate 34 and the counter B3'l. The counter A36 further outputs a reset signal 54 to the flip-flop 33 and the demodulation circuit 38, and outputs a counter output 56 to the selector 41 based on the predicted count.

On the other hand, the counter B37 receives the synchronization detection signal 57 from the flip-flop 33 in addition to the above-mentioned human power, and
A counter output 55 based on the predicted count is provided to the selector 41.

In addition, the demodulation circuit 38 receives the synchronization detection signal 57 and performs the following based on the read data 3 and the read clock 4.
ID1. ID2 and data 25 are demodulated. Also,
CRC check times? ! &39 is the CRC13 in IDI and ID2 based on the output of the demodulation circuit 38.
a and 13b, that is, error detection is performed.

Furthermore, the ID check circuit 40 includes the demodulation circuit 3g,
CRC check circuit 39 and from outside the circuit! D number Human power 58 determines whether or not the target ID field has been successfully read, and if it is normal, the target ID field is read.
The read signal 59 is output to the selector 41 at level "1". On the other hand, purpose! If the D field cannot be read normally, the purpose ID read signal 59 becomes “0”.
″ level remains.

The selector 41 selects the two counters A36 . It has a function of switching the input from the counter B37, and when the target ID reading signal 59 is input as "1", the counter output 55 from the counter B is input, and the target ID reading signal 5 is inputted.
9 is input as 0'', the counter output 56 from the counter A is input manually.The selector 41 outputs the OPEN signal 50 to the OR gate based on the counter output 55 or 56. Output to 34.

The OR gate 34 receives the ID1 output signal, ID2 output signal or gate 0PEN signal 50 from the counter A.
The gate is opened by the input of the "1" level to any one of the gates, and the synchronizing signal 5YNC3 can be detected.

Note that the flip 70 knob 42 is added in order to prevent duplicate detection of the synchronization detection signal 57 from being performed again after the OR gate 34 is opened and the synchronization detection signal 57 is first output from the 7 lip 70 knob 33. The output on the O side is inputted to the output from the OR gate 34 and the AND gate 35, and the output obtained by the logical product of the two is inputted to the AND gate 32 along with the output of the synchronization signal detection circuit 31. The structure is such that The flip-flop 33 outputs the AND gate 3 in synchronization with the read clock 4.
2, a synchronization detection signal 57 is output.

Next, the operation of this embodiment will be explained.

First, read data 3. Lead clock 4. When the sector mark signal 5 and the write clock 6 are input manually, the counter A36 starts a predictive count using the input of the sector mark signal 5 as an initial value.

Next, the synchronization signal detection circuit 31 detects the synchronization signals 5YNCI and 5YNC2 from the output of the shift register 30, and the ID1 factory signal 51 from the counter A.
Alternatively, the flip-flop 33 outputs the synchronization detection signal 57 to the demodulation circuit 38 and the counter B by ORing it with the ID2 processing signal 52. The counter B starts predictive counting based on the write clock 6 using the manual input of the synchronization detection signal 57 as an initial value.

On the other hand, in the demodulation circuit 38, based on the input of the synchronization detection signal 57, the ID field, that is, IDI and ID
Track number 11a in 2.

11b, sector numbers 12a and 12b are read.

Subsequently, an error check is performed by the CRC check circuit 39, and further an ID check is performed by the ID check circuit 40 by the ID number manual 58, and the target ID field is successfully read. As a result, the ID read signal is output as "1". In the selector 41, when the ID reading signal is inputted with a value of "1", the counter output 55 from the counter B37 is selected manually. The predicted count of the counter B37 is determined by the synchronization detection signal 57, that is, I
Since counting starts from DI or ID2, the selector 41 can be used as a more accurate prediction range)
The OPEN signal 50 can be output to the OR gate 34.

In this way, OR gate 3 is activated by gate 0PEN signal 50 based on the predicted count value from counter B3'7.
Output is performed from 4, which passes through an AND circuit 35 to 32
is man-powered. In this way, in the cooking state where the gate circuit G is set to 0PEN, the synchronization signal 5YNC3 is detected by the synchronization signal detection circuit 31, and this output signal is sent to the AND gate 32.
, a logic match is made, and the flip-flop 33 inputs the synchronization detection signal 57 to the demodulation circuit 38, whereupon the data 25 is read.

As described above, counter B3'7 determines whether IDI or I
When predicting the position of the synchronization signal 5YNC3 from D2, relatively highly accurate prediction is possible. Therefore, for example, it is sufficient to keep the gate G1, that is, the gate 0PEN signal 50 based on the counter B37, in the QPEN state for a time range of about ±n/2 cycle period with respect to the predicted position of the synchronization signal 5YNC3 based on the write clock 6. .

The predicted count by the counter B37 explained above is
First, it starts by reading the track number 11a and sector number 12a of the IDI based on the detection of the synchronization signal 5YNC1, and if this fails, reading the track number 11b1 of ID2 of ID2 based on the detection of the synchronization signal 5YNC2.
It starts by reading sector number 12b.

However, if neither of the ID fields, IDI and ID2, is successfully read, the synchronization detection signal 57 is not input to the counter B37.
It becomes difficult to predict the position of the synchronization signal 5YNC3 from the ID field of IDI or ID2. In this case,
The ID read signal 59 from the ID check circuit 40 is "
0" value is input to the selector 41, and the input to the selector 41 causes the counter output 56 from the counter A'36 to be selected. In the selector 41, the counter output 56 from the counter A, that is, the sector An OPEN signal 50 representing the detection time range of the synchronizing signal 5YNC3 from the position of the mark signal 5 is output to the OR gate 34 of the gate G.

In this way, from the position of the sector mark signal 5, the synchronization signal 5
When predicting the position of YNC3, the I
Since the precision is somewhat lower than the predicted count from the ID field of Dl or ID2, the OPEN signal 50 for G) is calculated based on the write clock 6 for the predicted position of 5YNC3 in the case of counter B. 2
It is sufficient to maintain the 0PEN state in a time range of about twice that, that is, about ±n cycle period.

As described above, according to this embodiment, the following effects can be obtained.

(1) If the ID field of IDl or ID2 is successfully read, the gate circuit G is set to 0PEN state using the predicted count value from these ID fields closer to the synchronization signal position, and the synchronization signal 5YNC3 is output.
If these ID fields are not read correctly, the gate circuit G is detected based on the predicted count value from the sector mark signal 5 at the beginning of the sector.
By setting 0PEN to the 0PEN state, it is possible to increase the setting accuracy of the detection time range of synchronization signal 5YNC3 by adopting the one with the highest accuracy among multiple prediction counts, and to enable the detection error of synchronization signal. can be prevented.

(2) According to the above (1), the detection accuracy of the synchronization signal 5YNC3 is improved, so it is possible to prevent data reading errors from occurring and to enable highly reliable data transfer.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and various changes can be made without departing from the gist thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, when detecting the synchronization signal, a plurality of reference points are provided in the same sector, and by reading these reference points, a predictive count of the synchronization signal position is started. By preferentially adopting the predicted count from the reference point at the nearest position of the signal and controlling the detection time range of the synchronization signal using the adopted predicted count, multiple predicted counts are performed in parallel, and these Among the predicted counts, the predicted counts from the reference point located near the synchronization signal are sequentially adopted with priority, so that a high prediction accuracy can be ensured, and the synchronization signal can be detected reliably.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the control logic of a control device of an optical disk system that switches the detection gate width of a synchronization signal according to an embodiment, and FIG. 2 is an explanation showing the overall configuration of the optical disk system according to this embodiment. FIG. 3 is an explanatory diagram showing the recording format on the optical disk system of the embodiment. 1...OFC (optical disk control device), 2...OD
D (optical disk drive equipment, 3...read data, 4
... Read clock, 5 ... Sector mark signal, 6
...Light clock, 7...Sector mark, 11a
,, 11b...Track number, 12a, 12b...
Sector number, 13a, 13b...-CRC120, 22
... Gisep, 21 ... FLAG, 25 ... Data, 30 ... Shift register, 31 ... Synchronization signal detection circuit, 32.35 ... AND gate, 33°42.
...Flip 70 Tsubu, 34...OR game), 36.
...Counter A137...Counter B138...Demodulation circuit, 39...CRC check circuit, 40...I
D check circuit, 41...Selector, 50...Game) OPEN signal, 51...IDt area signal, 52...
...ID2 rear signal, 54...Reset signal, 55
．． 56...Counter output, 57...Synchronization detection signal,
58...ID number input, 59...ID reading signal.

Claims (1)

[Scope of Claims] 1. A synchronization signal detection method that synchronizes using a synchronization signal written immediately before the data signal when reading a data signal transferred to the control system via the drive system, the method comprising: When detecting a synchronization signal, a predictive count of the synchronization signal position is started based on the reading of a plurality of reference locations in the same sector, and from among these reference locations that can be read and are closest to the synchronization signal, A synchronization signal detection method characterized in that a predicted count of 1 is preferentially adopted, and a detection time range of the synchronization signal is controlled by the adopted predicted count. 2. The synchronization signal detection method according to claim 1, wherein the reference point is a sector mark signal written at the beginning of a sector, or a track number or sector number written in an ID field. 3. The detection time range of the synchronization signal is set narrow for predicted counts from a reference point located near the synchronization signal, and wide for predicted counts from a reference point located far away. Characteristic claim 1
Synchronous signal detection method described in section.