JPH0421975A - Sector mark detector - Google Patents

Abstract

PURPOSE:To prevent a sector mark from being undetected by fastening timing for release an erroneous detection avoiding gate in the case of detecting the next sector mark when a sector mark detection signal is not outputted. CONSTITUTION:An SM signal in a read signal is impressed into an SM detection signal/interpolated SM detection signal generating circuit 2, and a window generating circuit 24 outputs mark width detection signals (a) and (b) corresponding to the SM signal. Then, mark detection signals (e) and (f) synchronized to a clock are obtained from detection circuit 26a and 26b. A detection circuit 28 outputs an SM detection signal (h). When this signal (h) is not inputted, a signal generating circuit 29 outputs an interpolated SM detection signal (i). These signals (h) and (i) are inputted to an erroneous detection proof gate generating circuit 5, and an erroneous detection avoiding gate signal (m) is outputted. When the signal (h) is not outputted, a signal (l) is outputted from an erroneous detection avoiding gate width generating circuit 3, and the timing for canceling the signal (m) next is fastened so as to detect the next SM pattern without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sector mark detection device used when reading data from a recording medium in a recording/reproducing device.

[Prior Art] In recent years, information recording and reproducing devices such as optical disk devices have been used in a wide range of applications. Particularly recently, the amount of data handled has increased dramatically, and optical recording and reproducing devices capable of recording large amounts of data, such as optical disk devices, are attracting attention.

By the way, in the above-mentioned optical disk device and the like, data is serially recorded in each sector divided into a plurality of sectors in each track. At the beginning of each sector is JP-A-62-2023
As disclosed in the conventional example No. 33, a sector mark indicating the starting point of a sector is recorded.

This sector mark is an important mark that indicates the sector start point, and timing control is activated by detecting this mark. Therefore, a detection method or a detection device that can accurately detect the sector mark is desired.

In the conventional example, a plurality of patterns are used as sector marks, these patterns are parallelized by a shift register, and a sector mark detection signal is obtained depending on whether the patterns match a comparison pattern.

However, signals read from a disk may contain patterns similar to sector marks due to defects or the like.

[Problem to be solved by the invention] In cases where all patterns are not compared to prevent non-detection as in the conventional example, this defect tends to cause false detection; however, in the conventional example, this countermeasure is not possible. There is a system that outputs an interpolated sector mark detection signal when a sector mark is not detected or a sector mark is not detected, but this interpolated sector mark detection signal is delayed from the original sector mark detection signal. Therefore, there is a problem in that detection of the next sector mark may fail.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a sector mark detection device that can effectively prevent erroneous detection that tends to occur in the conventional example.

[Means and effects for solving the problem] As shown in FIG.
is input to the SM detection signal/interpolated SM detection signal generation circuit 2 which generates a sector mark (hereinafter abbreviated as SM) detection signal and an interpolated SM detection signal. A gate width switching circuit 3 for preventing false detection that outputs gate width switching signals Gl and G2 for switching to the gate width, and a gate width switching signal Gl from this circuit 3.
. Prevention gate generation circuit 5
It is composed of.

FIG. 1(B) shows a timing chart explaining the operation of FIG. 1(B). is input, and when an SM is detected, an SM detection signal is output, and when an SM is not detected, an interpolated SM detection signal is output.

Both of these detection signals are input to the false detection prevention gate generating circuit 5 via the OR gate 4, and the false detection prevention gate is activated as shown in FIG. 1(B) at the fall of the detection signal. On the other hand, when the SM detection signal is not input, the false detection prevention gate width switching circuit 3 changes the gate width of the false detection prevention gate generation circuit 5 to a point immediately before the timing at which the SM of the next sector is expected to be detected. When the gate width switching signal G1 that makes the gate inactive is output and the interpolated SM detection signal is input, the false detection prevention gate is activated well before the timing when the SM of the next sector is expected to be detected. A gate width switching signal G2 having a gate width that makes the gate inactive is output.

Note that the timing of making this inactive is based on the interpolation SM
It is determined from the output timing of the detection signal and the rotation deviation of the spindle motor that rotates the disk.

In the present invention, when the SM detection signal is correctly detected, the period during which the false detection prevention gate is inactive is as follows:
Since the detection occurs only near the timing of normal detection, it is possible to effectively prevent false detection. In addition, when the interpolated SM detection signal is output, the period for inactivating the false detection prevention gate is made earlier, so the timing at which the interpolated SM detection signal is output is shorter than the timing at which the SM detection signal is output. Even if there is a delay, the false detection prevention gate will be released during the next 8M pattern detection period to ensure that the 8M pattern is detected.
It allows for pattern detection.

[Example] Hereinafter, the present invention will be specifically described with reference to the drawings.

2 to 5 relate to one embodiment of the present invention, FIG. 2 is a configuration diagram of a sector mark detection device of one embodiment, FIG. 3 is a timing chart for explaining the operation of one embodiment, and FIG. The figure is a circuit diagram of the erroneous detection prevention gate generation circuit, and FIG. 5 is a timing chart diagram for explaining the operation of FIG. 4.

As illustrated in FIG.
．． 22, the clock 2FcLK is applied to the clear terminal CLR of the counter 23, and is applied to the clock terminal while the read signal is "H". .

As shown in FIG. 3, this window generation circuit 24 generates a mark width detection signal a from two output terminals based on the count value corresponding to the SM flaw signal in the input read signal.
, b. Note that this window generation circuit 24 is
It consists of a decoder. The above SM flaw signal basic clock IFCL is one cycle, that is, IT is three cycles 3T.
and 5 cycles and a width of 5T. Outputs a and b of the window generation circuit 24 are applied to data input terminals of flip-flops 25a and 25b, respectively,
At the rising edge of the read signal passed through the inverter 21, signals shown at c and d in FIG. 3 are output from the Q output terminal. Each flip-flop 25a.

Outputs c and d of 25b are respectively input to detection circuits (3T detection circuit 26a, 5T detection circuit 26b) of 3 cycles 3T and 5 cycles 5T. That is, 3 cycles 3T, 5 cycles 5
When the signal T is input to the window generation circuit 24, the flip-flop 25a.

Detection signals as shown in FIG. 3e and d are obtained from 25b.

Since a clock IFCLK output from a crystal oscillator or the like is input to the 3T detection circuit 26a and 5T detection circuit 26b, mark detection signals e and f synchronized with this clock IFCL are obtained. In addition, clock 2FCL
K is a clock having twice the frequency of clock IFcL. These signals e and f are input to the delay circuit 27.

A clock IFcL is also input to this delay circuit 27. This delay circuit 27 receives the input signal e.

The other input signals are delayed to match the final pattern of the SM at f. In other words, the signal f in Fig. 3
The last detected signal fn (i.e. signal gl) at
The other signal f1 is added to the signal g2 so that the signal e
is delayed and output as signal g3. These signals g2°g3. ... is a combination selection detection circuit (
For example, since three combinations are selected from five 8M patterns, the circuit is abbreviated as 503 detection circuit. )28.

The final SM pattern detection signal g1 of the signal f is also input to this SCS detection circuit 28, and the input signal gl.

g2. g3. When it detects an 8M pattern from the combination of..., it outputs an SM detection signal.

This SM detection signal is generated by the interpolated SM detection signal generation circuit 29.
is applied to the set terminal of the SR flip-flop constituting the false detection inhibiting gate width generation circuit 3.

The interpolation SM detection signal generation circuit 29 includes a clock IF
When CL is input and no SM detection signal is input, the interpolated SM detection signal i is output to the reset terminal of the flip-flop.

The interpolated SM detection signal generation circuit 29 is composed of, for example, a counter. This takes advantage of the fact that SMs should be detected at equal intervals, and the counter is reset by the SM detection signal. Normally, when the SM detection signal is detected, the counter does not output because a reset signal is input.
However, if the SM detection signal is not detected, the counting operation continues until a certain set count value is reached and the counter outputs an output. The output of this counter is interpolated S
This becomes the M detection signal i. In addition, the present inventor's Japanese Patent Application Laid-open No.
-277369 (Japanese Patent Application No. 63-105975), Interpolated S to Japanese Patent Application No. 63-253258 and Japanese Patent Application No. 1308979
A specific configuration of the M detection signal generation circuit is described, and this configuration may be used.

The SM detection signal 1 and the interpolated SM detection signal i pass through an OR gate 4, become a signal j, and are input to an erroneous detection prevention gate generation circuit 5. The clock IFCLK, the Q output k and the Q (inverted) output 1 of the flip-flop are input to this erroneous detection prevention gate generation circuit 5, and outputs an erroneous detection prevention gate signal m to, for example, 503 & output circuit 28.

When the flip-flop receives the SM detection signal, it outputs the signal k to the false detection prevention gate generation circuit 5 as the first gate width switching signal G1.

That is, when this signal k is output, the timing at which the false detection prevention gate signal m is canceled next is immediately before the timing at which the 5C3 detection circuit 28 normally performs 3M pattern detection. In other words, the erroneous detection prevention gate period that prevents erroneous detection is set long, and the period during which the 5C3 detection circuit 28 can detect the 3M pattern (that is, the SM pattern detection window period) is set short.

On the other hand, when the SM detection signal 1 is not output, the interpolated SM detection signal i is output, so that the flip-flop outputs the signal p as the second gate width switching signal G2. In other words, when this signal 1 is output, the timing at which the false detection prevention gate signal m is canceled is made earlier (before the timing for regular 3M pattern detection), and the next time the false detection prevention gate signal m is released. 3M pattern detection can be performed reliably.

In FIG. 3, if the normal detection gate length is, for example, T1, then the interpolation gate length T2 is set such that T2<Tl. (Also, in the normal case when the 8M pattern is detected, the period t1 in which the next signal m becomes "'L"' is 8M
The next signal m when pattern detection fails is “
1. It is shorter than the period t2 during which TI occurs (tl<t2>). Specifically, the false detection prevention gate signal m becomes "H°'" at the falling edge of the signal j, as shown in FIG. When the signal k is “H”, after a certain period T1, “l l, II
On the other hand, when the signal p is "H", it is set to become "II L" after a period T2 shorter than the fixed period TI. The configuration is as shown in FIG.

The clock IFCL is applied to each clock input terminal of the first counter 31a and the second counter 31b, and the count outputs of the counters 31a and 31b are respectively input to the first decoder 32a and the second decoder 32b,
When the count values of the counters 31a and 31b reach a certain value, the outputs nl and n2 of the decoders 32a and 32b are set, for example, from "H" 1 to II L II.

In this embodiment, the first decoder 32a is set to go low at a count value larger than that of the second decoder 32b.

The outputs nl and n2 of each of the decoders 32a and 32b are sent to the OR circuit 3 through AND gates 33a and 33b, respectively.
A signal m is input to the sC3C3 detection 28 from the OR circuit 34 and output to the sC3C3 detection 28.

Signals k and 1 from the flip 70 are input to the AND gates 33a and 33b, respectively, and these signals are sent to the decoder 32a by 11.

The outputs nl and n2 of 32b are passed through the gate or blocked.

Note that the counters 31a and 31b are counters that are reset at the falling edge of the signal j.

(The counter output reset by II HII can also be constructed using a differentiating circuit.) The operation of this false detection prevention gate generation circuit 5 is shown in FIG.

The signals j, k in FIG. 5 are the signals j, k in FIG.

The counters 31a and 31b each start counting at the falling edge of the signal j. When the count value reaches a preset value, the output n2 of the second decoder 32b changes from "H" to 'L' as shown in FIG.
After that, the output n1 of the first decoder 32a also becomes '
It changes from H" to 'L". On the other hand, when the SM detection signal is output, the Q output k of the flip-flop becomes "H", so the output n1 of the first decoder 32a passes through the AND gate 33a and the OR circuit 34, and is output as the signal m. be done.

On the other hand, when the interpolated SM signal is output, the output 1 becomes .degree.H.degree., so the output n2 of the second decoder 32b is outputted via the ant game 1-33b and the OR circuit 34.

, 11 is the decoder output n1. , n2 are inverted at the same time after becoming "L"' and before rising to "H", so the signal m is not affected by this inversion, and
When the signal j falls, it rises to "H"'.

With this configuration, when an SM detection signal is generated, the period during which the detection window opens for the next 8M pattern detection is narrowed to reliably prevent false detection.
When the detection signal i is output, the detection window is widened early to ensure that the next 8M pattern can be detected even if the timing at which this interpolated SM detection signal is output is delayed. There is.

As the false detection prevention gate length of this false detection prevention gate signal m, for example, one sector length is 1024 bytes/sector, and the transfer rate is 5.55M [in the case of bpsl, 130
mm I S O7t'? Approximately 1.96
m [SeC], so the gate length for preventing false detection during normal detection is set to the time length excluding the spindle motor rotation deviation and the SM section. For example, if the rotational deviation of the spindle motor is ±0.5%, then 1.96x0.99
55M length ("7.21s) -1,94m [Se
C].

When generating an interpolated SM detection signal, the gate length excluding the preformat portion is used, and is approximately 1.87 m [SeC].

The SM detection signal is sent to a demodulation circuit for signals recorded on a disk (not shown) or a modulation circuit for modulating a signal transferred from a higher level, and is used as a timing signal for operating these circuits.

In the first embodiment described above, the gate length of the next false detection prevention gate signal is switched depending on whether the SM detection signal or the interpolated SM detection signal is detected, but the interpolated SM detection signal is not output. The gate length may be changed depending on whether the Furthermore, the next gate length may be switched depending on whether or not the SM detection signal is output.

[Effects of the Invention] As described above, according to the present invention, there is provided a sector mark detection signal generating means for generating a sector mark detection signal by detecting a sector mark, and a sector mark for interpolation when a sector mark detection signal is not generated. In other words, an interpolated sector mark detection signal generation means that generates an interpolated sector mark detection signal, and a sector mark error when detecting the next sector mark based on at least one of the sector mark detection signal and the interpolated sector mark detection signal. An erroneous detection prevention gate generation means for outputting a sector mark erroneous detection prevention gate signal for preventing detection is provided, and when the sector mark detection signal is not output, the erroneous detection prevention gate is released when performing the next sector mark detection. Since the timing is set early, it is possible to prevent sector marks from not being detected. Further, when the sector mark detection signal is output, it is possible to prevent the next sector mark from being erroneously detected.

[Brief explanation of drawings]

FIG. 1 (8) is a schematic configuration diagram of the present invention, FIG. 1 (8) is an explanatory diagram of the operation of FIG. 2 is a block diagram of the sector mark detection device of the first embodiment, FIG. 3 is a timing chart for explaining the operation of the first embodiment, FIG. 4 is a block diagram of the gate signal generation circuit for preventing false detection, and FIG. FIG. 4 is a timing chart diagram for explaining the operation of FIG. 4; 1. Sector mark detection device 2... SM detection signal/interpolation SM detection signal generation circuit 3.
... Erroneous detection prevention gate width switching circuit 4 ... OR gate 5 ... Erroneous detection prevention gate generation circuit Wisdom C

Claims (1)

[Claims] A sector for detecting a sector mark indicating the starting point of a sector in order to perform recording and reproduction in sector units on an optical recording medium having sectors as a plurality of recording units formed on a recording track. In the mark detection device, sector mark detection signal generating means outputs a sector mark detection signal when a sector mark is detected, and an interpolated sector mark detection signal outputs an interpolated sector mark detection signal when the sector mark detection signal is not output. and a false detection prevention gate for preventing malfunction of the next sector mark detection of the sector mark detection signal generating means based on at least one of the sector mark detection signal and the interpolated sector mark detection signal. A sector mark detection device comprising sector mark erroneous detection prevention gate generation means for making the gate length of a signal shorter when the interpolated sector mark detection signal is generated than when the sector mark detection signal is generated. .