JPH01107132U - - Google Patents
Info
- Publication number
- JPH01107132U JPH01107132U JP1988002272U JP227288U JPH01107132U JP H01107132 U JPH01107132 U JP H01107132U JP 1988002272 U JP1988002272 U JP 1988002272U JP 227288 U JP227288 U JP 227288U JP H01107132 U JPH01107132 U JP H01107132U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- input
- external wiring
- wiring terminal
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の半導体装置の一実施例を示す
斜視図、第２図は第１図の要部拡大平面図、第３
図は第２図のＡ―Ａ断面図、第４図は従来の半導
体装置の斜視図、第５図は第４図の要部拡大平面
図である。
２……半導体素子、３ａ，３ｂ……外部配線端
子、４ａ，４ｂ……入出力用端子、５……ボンデ
イングワイヤ、６……電源用パターン、７……バ
イアス素子。
FIG. 1 is a perspective view showing an embodiment of the semiconductor device of the present invention, FIG. 2 is an enlarged plan view of the main part of FIG. 1, and FIG.
The drawings are a sectional view taken along the line AA in FIG. 2, FIG. 4 is a perspective view of a conventional semiconductor device, and FIG. 5 is an enlarged plan view of the main part of FIG. 4. 2... Semiconductor element, 3a, 3b... External wiring terminal, 4a, 4b... Input/output terminal, 5... Bonding wire, 6... Power supply pattern, 7... Bias element.
Claims (1)
配線端子とがボンデイングワイヤにより電気接続
される半導体装置において、前記外部配線端子の
電源用パターンに一端が接続され、前記半導体素
子の入出力用端子に他端が選択的に接続されるバ
イアス素子を備えたことを特徴とする半導体装置
。 In a semiconductor device in which a semiconductor element having a plurality of input/output terminals and an external wiring terminal are electrically connected by a bonding wire, one end is connected to the power supply pattern of the external wiring terminal, and one end is connected to the input/output terminal of the semiconductor element. A semiconductor device comprising a bias element whose other end is selectively connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988002272U JPH01107132U (en) | 1988-01-12 | 1988-01-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988002272U JPH01107132U (en) | 1988-01-12 | 1988-01-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01107132U true JPH01107132U (en) | 1989-07-19 |
Family
ID=31202894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988002272U Pending JPH01107132U (en) | 1988-01-12 | 1988-01-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01107132U (en) |
-
1988
- 1988-01-12 JP JP1988002272U patent/JPH01107132U/ja active Pending