JPH01106548A - Modulator circuit - Google Patents

Abstract

PURPOSE:To make the modulated waveform of data signals having a peculiar pattern obtainable with a modulation circuit, by constituting the modulation circuit of the combination of a counter, decoder, matrix circuit, and gate circuit. CONSTITUTION:The modulation circuit of this invention is constituted of a counter 103, decoder circuit 104, matrix circuit 105, and gate circuit 106. Namely, a modulating pulse pattern corresponding to three data signals is formed and the modulating pulse pattern corresponding to the three data signals is switched at the gate circuit 106 and outputted through a filter 108. Therefore, the modulating waveform form of data signals becomes freely settable and easily changeable and the modulated waveform of data signals having a peculiar pattern other than ordinary 'H' and 'L' signals can be obtained. Accordingly, the complicated control, etc., of a reception station can be coped with by constituting complicated data formats.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention provides a modulation signal of N periods or N/2 periods within one bit time of a data signal, and further changes the periodic waveform to generate a plurality of data. FSK to modulate the signal
The present invention relates to a modulation circuit of the system.

[Prior Art and Its Disadvantages] As a conventional FSK modulation circuit, the one shown in FIG. 5 is known.

That is, for example, when creating modulation signals of one period and two periods within one bit time of a data signal, first, a pulse of two periods is oscillated for one bit of the data signal from the oscillation circuit 501, and the pulse is sent to the counter 503. is supplied to the input terminal P of. The period of the pulse is kept stable by the crystal oscillator 501, and the period of the pulse is kept stable by the crystal resonator 501.
The frequency is divided by /2 and output to the input terminal X of the gate circuit 505. At this time, the other input terminal Y of the gate circuit 505
The output of the oscillation circuit 501 is supplied to the oscillation circuit 501. 6th
The figure shows the output waveform 601 of the counter 503 and the oscillation circuit 503.
An output waveform 602 is shown.

On the other hand, the oscillation circuit 50 also includes the synchronization pulse generation circuit 504.
2 and the output of the counter 503 are supplied, and the synchronizing pulse generating circuit 504 outputs a transmission clock for data transmission timing to a device on the data signal transmission side via a terminal 508.

A data signal is inputted from the above device via a terminal 509 as shown in a waveform 603 shown in FIG. This terminal 509
The data signal input via the gate circuit 505 is supplied to the input terminal C of the gate circuit 505. This data signal causes the gate circuit 505 to output T2 as shown in the waveform 604 shown in FIG.
A signal having a 1/2 cycle is output during the period. This signal is output to a filter 507 via a driver circuit 506 that amplifies the signal to a predetermined level.

The filter 507 is configured with a low-pass filter or a band-pass filter, and removes high frequency components of the output signal of the gate circuit 505 amplified via the driver circuit 506. This filter 507 converts the output signal into an analog signal as shown in a waveform 605 shown in FIG. 6, and outputs it from a terminal 510.

Incidentally, in recent years, with the increase in the number of data devices, there has been an increasing demand for data exchange between stations. in this case,
In order to make economical use of the lines, the data signal transmission form of each data device uses a method in which two lines are used and a modulated signal is sent out in the form of a burst wave on the same lines. For this reason, it is necessary to packetize the data structure, and the normal r
There may be cases where a special pattern other than the HJ and "L" signals is used.

However, in the conventional modulation circuit as shown in FIG. 5, the modulation waveform format of the data signal cannot be freely set. For this reason, it is not possible to obtain a modulation waveform of a data signal having a special pattern other than the normal rHJ and "L" signals.
There was a drawback that it could not support the packetization of the data structure described above.

[Object of the Invention] The present invention has been made in view of the above points, and allows the modulation waveform format of the data signal to be freely set.
It is an object of the present invention to provide a modulation circuit that can obtain a modulation waveform of a data signal having a special waveform other than an "L" signal.

[Summary of the Invention] That is, the modulation circuit according to the present invention has a circuit configuration that combines a counter, a decoder, a matrix circuit, and a gate circuit, forms a modulation pulse pattern corresponding to three data signals, and uses the gate circuit to generate a modulation pulse pattern corresponding to three data signals. The modulation pulse pattern corresponding to the data signal is switched and outputted via a filter.

[Embodiment of the Invention] A modulation circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a modulation circuit according to one embodiment. First, before explaining the configuration and operation of this modulation circuit, in order to facilitate understanding, the FSK modulation method realized by the modulation circuit will be explained with reference to FIGS. 2 to 4. Here, an example will be taken in which the number of pulse divisions within one bit time of the data signal is four.

FIG. 2 is a diagram showing an example of a data format. In FIG. 2, a data signal 201 includes a first data signal indicating "L" or rHJ of data, a second data signal indicating whether modulation output is possible, a Briand sample for establishing synchronization when transmitting data, and a second data signal indicating whether or not modulated output is possible. It is composed of a third data signal for creating a special format modulation signal indicating the start and end delimiters of data, and has periods S, P, SD, D,
I have ED.

S during m indicates a state in which the modulation signal output from the modulation circuit is cut off. The period tip indicates a preamble period for data bit synchronization at the other station. The period SD indicates a start delimiter period indicating the start of data.

The period indicates the data period. Period 11ED indicates an end limiter period indicating the end of data.

Data signal DO~ to represent this data format
The waveforms of D2 are shown at 202 to 204 in the figure.

Further, the waveform of the FSK modulation signal, which is the output signal of the modulation circuit, is indicated by 205. Waveforms 206 to 208 are enlarged waveforms of data signals DO to D2 in the preamble period P1, start delimiter period SD, and end limiter period 1iJED, respectively.

FIG. 3 is a diagram showing the correlation between the data signals DO to D2. During the period (period S) in which the modulated signal output is off, the data signals DO to D2 are all rHJ. Further, when the data signals DO and D1 are "L" and the data signal D2 is rHJ, this is special data, that is, non-data, and is indicated by rNJ. Two consecutive rNJs are set as IN and NJ,
In the case of rN and NJ, a modulated pulse waveform is obtained in which the pulse width becomes wider near the changing points of the data bit periods b1 and b2. This non-data N has a structure that always maintains pulse periodicity at 2 kebaa.

On the other hand, when data signals DO to D2 are all "L", it represents data rOJ, and 2 times within 1 bit period of the data signal.
Change the period. Furthermore, when the data signal DO is "H" and the data signals DI and D2 are "S", the data is "1".
represents one period of change within one bit period of the data signal.

Now, the configuration of the data signal is rN, N, 0. In the case of IJ, the modulated pulse waveform by the combination shown in Fig. 3 is 4 in Fig. 4.
It will look like 01. Therefore, by removing the high frequency components of this waveform 401 using a filter, an FSKl signal like waveform 402 is obtained.

Next, the modulation circuit shown in FIG. 1 that satisfies the above-mentioned pulse waveform conditions and pulse waveform operation conditions will be described.

That is, the oscillation circuit 102 oscillates at a frequency that determines the minimum pulse width of the modulated pulse waveform (waveform 401 in FIG. 4), that is, the number of divisions within one bit period of the data signal.

In this case, in order to stabilize the above frequency, the crystal oscillator 1
01 is used.

The pulse output from this oscillation circuit 102 is applied to a terminal CK of a counter 103 and frequency-divided by 1/8. Then, when the frequency division number is 1/21, from terminal A, 1/2"
(When [Bl, 1/23(7)), it is output from terminal C. These outputs from terminals A-C are temporally sequentially output from Y1 to Y8 in the decoder circuit 104,
It is sent to matrix circuit 105.

The matrix circuit 105 is formed by connecting diodes M1 to Mn, and generates a modulated pulse waveform of "0", "1", rN, NJ shown in FIG.
A modulated pulse pattern corresponding to data indicating J and data indicating a special form is output. Note that here, a matrix circuit configuration is used in which diodes M1 to Mn are used and the pulses of Y1 to Y8 in one bit are outputted via diodes M1 to Mn when they are rHJ, but for example, a 771 circuit, an AND gate circuit, etc. Can be configured.

“0”, “1”, r obtained by matrix circuit 105
The modulated pulse waveforms of N and NJ are each input to the gate circuit 10.
Added to 6. The gate circuit 106 switches the output of the matrix circuit 105 depending on data indicating "L" or rHJ of data and data indicating a special form, and also enables or disables the output of the matrix circuit 105 with data indicating whether modulation output is possible. shall be. In this way, the modulated pulse waveform (waveform 401 in FIG. 4) corresponding to the data signals DO to D2 output from the gate circuit 106 is output to the driver circuit 107. Here, flip 70 knob 11
0 to 112 are provided to eliminate irregular pulse output by synchronizing the changing points of the data signals D1 to D2 with the changing points of each data synchronization indicated by the modulated pulse waveform. In this case, the number of divisions of 1 bit of the data signal is 4.
Therefore, each of the flip-flops 110 to 112 is synchronized with the output of the terminal B of the counter 103.

Further, when the data signal Do-D2 arrives, a trigger circuit 109 is provided to initialize the counter 103 so that each signal at the terminals A-C of the counter 103 becomes IJ at the change point of the period of the data signal. Output pulse to counter 10
3 terminal CLR.

The driver circuit 107 power amplifies the modulated pulse waveform output from the gate circuit 106 to a required modulated output level. The output from the driver circuit 107 has a pulse waveform like the waveform 401 in FIG. 4 and contains many high frequency components, so the high frequency components are removed through the filter 108 and outputted to the terminal 116 as an analog signal.

The filter 108 is a low-pass filter or a band-pass filter composed of an inductance, a capacitor, etc., and its characteristics are determined by the amount of high-frequency component blocking and waveform response. The signal waveform outputted to the terminal 116 through this filter 108 is the waveform 40 in FIG.
It will be like 2.

As described above, according to this embodiment, the counter 103, the decoder circuit 104, the matrix circuit 105, and the gate circuit 1
06, the modulation waveform format of the data signal can be set freely and can be easily changed. Therefore, normal rHJ, “L
It is possible to obtain a modulated waveform of a data signal having a special pattern other than the J signal, thereby making it possible to configure a complex data format and cope with complex control of the receiving station.

In this embodiment, the number of divisions within one bit of the data signal was set to four, but the number of divisions of the counter, the configuration of the decoder,
By changing the configuration of the matrix circuit, a larger number of divisions can be provided. In addition, special data, that is, two consecutive non-data IN and NJ, are expressed in two waveform formats, but by combining these pulse waveforms, it is possible to create waveform formats that correspond to even more special data. Can be done.

[Effects of the Invention] As described above, according to the present invention, data signals can be changed i! 11
The waveform format can be freely set, and a modulated waveform of a data signal having a special pattern other than the normal rHJ and "L" signals can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of a modulation circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the data format of the embodiment, and FIG. 3 is a diagram showing three data signals in the embodiment. phaser! FIG. 4 is a diagram showing the modulated pulse waveform obtained in the same embodiment. FIG. 5 is a block diagram showing the circuit configuration of a conventional modulation circuit. FIG.
5 is a timing chart for explaining the operation shown in the figure. 101... Crystal resonator, 102... Oscillation circuit, 10
3...Counter, 104...Decoder circuit, 105
... Matrix circuit, 106 ... Gate circuit, 1
07... Driver circuit, 108... Filter, 10
9...Trigger circuit, 110-112...Flip-flop, 113-116...Terminal. Applicant's agent Patent attorney Takehiko Suzue No. 1 Figure 3 Figure 4 Figure 5 Figure 6 Procedural amendments Showa 6 History, 121/1

Claims (1)

[Claims] A first data signal indicating "L" or "H" of data;
A second data signal indicating whether modulation output is possible, a preensemble for determining synchronization when transmitting data, and a third data signal for creating a special format modulation signal indicating delimiters at the start and end of data. an oscillation circuit that oscillates a pulse signal that determines the period of the data signal; a counter that divides the pulse signal from the oscillation circuit by a predetermined frequency division number; a decoder that receives the output of this counter and creates a predetermined number of divided pulse trains within 1 bit of the data signal; and a modulated pulse corresponding to the first and third data signals based on the divided pulse train created by this decoder. a matrix circuit that forms a pattern; a gate circuit that switches the output of this matrix circuit according to the first and third data signals, and enables or disables the output of the matrix circuit according to the second data signal; 1. A modulation circuit comprising: a filter that removes high frequency components from the output of a gate circuit.