JPH0654922B2 - Modulation circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a modulation circuit used in a communication system for modulating a digital signal into an analog signal and transmitting the analog signal due to restrictions on the frequency band of a transmitter, a receiver or a transmission path. It is a thing.

[Prior art]

In the communication system as described above, a serial binary signal is modulated into an analog signal by the FSK modulation circuit.

FIG. 2 is a schematic circuit diagram showing an example of a conventional FSK modulation circuit. Reference numerals 21 and 22 denote low frequency ₁ and high frequency ₂ sine wave generators, respectively. The binary signal to be modulated is directly supplied to the low frequency ₁ sine wave generator 21 and to the high frequency ₂ sine wave generator 2.
2 are given to respective output enable terminals via an inverter 23. The outputs of both generators 21 and 22 are input to the mixer 24, and the mixed output is transmitted as a modulated analog signal.

When the input signal is "1", the low frequency ₁ sine wave generator 21 is enabled, and when the input signal is "0", the high frequency ₂ (= 2 ₁ ) sine wave generator 22 is operated by the inverter 23. is enabled, thus mixer 24 to the output _1,
An analog signal in which sine waves of frequencies ₂ and ₁ appear in sequence is obtained. The sine waves having the frequencies ₁ and ₂ are transmitted and demodulated by a receiver (not shown) so as to be assigned to "1" and "0" of the binary signal, respectively.
When such a modulation circuit is used, the outputs of the sine wave generators 21 and 22 that operate independently are changed to the input 2 that is asynchronous with these operations.
Since it is switched by the value signal, the continuity of the output signal is not guaranteed unlike the one shown in FIG.

Further, since the signal becomes discontinuous at the time of switching, it contains a harmonic component, which becomes noise during demodulation.

Further, the sine wave generators 21 and 22 include a CR circuit in the circuit for determining the output frequency, so that the accuracy of the output frequency is low, and the output frequency changes due to aging, so that the reliability is low. is there. Further, there is a drawback that it is difficult to change the output waveform.

FIG. 3 shows an example of another FSK modulation circuit. The binary signal is input to VCO (voltage controlled oscillator) 25, where "1",
Corresponding to "0", it is converted into triangular waves of frequencies ₁ and ₂ . Then, this triangular wave is input to the sine wave generator 26,
The corresponding frequency sine wave is output.

In the case of this modulation circuit, unlike the one in FIG. 2, the continuity of the VCO25 output is guaranteed because the oscillator (sine wave generator 21, 22) is not switched. Since it is asynchronous, the phase of the switching point between ₁ and ₂ is not fixed. Further, since the CR circuit is used to determine the frequencies ₁ and ₂ , it has the same drawbacks as those of FIG. 2 and the difficulty of changing the output waveform is also the same.

For the above reasons, in the conventional demodulation circuit,
In the frequency switching part, assuming that the signal is not guaranteed, a large integrating circuit is provided to remove the noise generated in that part, or one bit corresponds to a plurality of cycles, and a signal of the same frequency continues for a predetermined cycle. After that, it was decided to take measures such as confirming "1" and "0". Therefore, there is a problem that the transmission speed becomes low.

〔Purpose〕

The present invention has been made in order to solve the problems of the prior art, and by using a digital circuit configuration, continuity of the frequency switching portion is guaranteed and the phase of the switching portion is constant. Therefore, it is possible to express "1" and "0" with the minimum number of cycles, and it is possible to increase the transmission rate. Furthermore, there is no secular change, and high reliability is ensured for a long time. It is an object of the present invention to provide a modulation circuit that can easily change the output waveform.

〔Constitution〕

The modulation circuit according to the present invention is a modulation circuit for FSK-modulating a serial binary signal, in which the first low frequency ½ cycle starts from 0 and increases, the first high frequency 1 cycle starts, and 0 starts to decrease. A large number of time-series and discrete voltage level information representing patterns for the second low frequency ½ cycle and the second high frequency one cycle, and data representing whether the end portion of each pattern is increased or decreased. And a memory in which data representing the end of each pattern is stored, data representing whether the end portion of the pattern read immediately before from the memory is increased or decreased, and 1 bit of a binary signal to be modulated. And a latch circuit for giving the latch contents to the memory as a higher-order address signal for specifying the storage areas of the first and second low frequencies or the first and second high frequencies, and a baud rate. A clock signal of the same cycle is counted, and the count value is stored in the memory and a counter that is provided to the memory as a lower address signal that specifies each of the time-series voltage level information of the pattern. A timing circuit for applying a latch signal to the latch circuit and a clear signal to the counter according to the data indicating the end of each pattern, and a digital / analog for converting the voltage level information read from the memory into an analog signal. And a converter.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing an embodiment thereof. FIG. 1 is a block diagram showing the configuration of the circuit of the present invention. The ROM (read-only memory) 6 is shown in FIG.
Low frequency _{1 as} shown in (b), (c) and (d)
Positive half cycle, also negative half cycle, high frequency
Time series data PF ₁ (t ₀ ), PF ₁ (t ₁ ), PF ₁ (t that represents the voltage level change pattern of ₂ (= 2 ₁ ) positive and negative 1 cycle, and also negative and positive 1 cycle. ₂ )… PF ₁ (t _n ), NF ₁ (t ₀ ), N
F ₁ (t ₁ ), NF ₁ (t ₂ ) ... NF ₁ (t _n ), PF ₂ (t ₀ ), PF ₂ (t ₁ ), PF
₂ (t ₂ ) ... PF ₂ (t _n ), NF ₂ (t ₀ ), NF ₂ (t ₁ ), NF ₂ (t ₂ ) ... NF ₂ (t _n ).
Is stored.

The peak values of these four patterns are equal, and the gradation representing the level is also equal to 6 bits, for example. These four types of data are PF ₁ (t), NF ₁ (t), PF ₂ (t), NF ₂ (t)
Say

PF ₁ (t) shown in Fig. 4 (a) is the first low frequency that starts and decreases, and NF ₁ (t) shown in Fig. 4 (b) is the second low frequency that starts and decreases. is there.

PF ₂ (t) shown in FIG. 4 (c) corresponds to the above-mentioned first high frequency because it starts increasing and ends decreasing when paying attention to the first half cycle. Similarly, NF ₂ (t) shown in FIG. 4 (d) begins to decrease and ends to increase, and thus corresponds to the above-mentioned second high frequency.

The ROM 6 is given an address of the upper 2 bits from the latch circuit 5 and an address of the lower k bits from the address counter 4, and outputs the upper 2 bits.
Bit address AH, AL is (0,0), (0,1),
NF ₂ (t), NF for (1, 0) and (1, 1) respectively
_The areas storing ₁ (t), PF ₂ (t), and PF ₁ (t) are accessed, and the contents of the address counter 4, 0 to 2 ^k −1
Depending on (= n), the stored data in each area, eg PF
₁ (t ₀ ), PF ₁ (t ₁ ), PF ₁ (t ₂ ) ... PF ₁ (t _n ) are sequentially read and output to the D / A (digital / analog) converter 7, where analog The signal is converted into a signal and transmitted as a modulated signal.

The data stored in the ROM 6 is 8 bits, and the remaining 2 bits of the above 6-bit data are used as follows. First, 1 bit is the final data PF ₁ (t _n ), NF ₁ (t _n ), PF
Only used for ₂ (t _n ) and NF ₂ (t _n ) to indicate that it is the final data. The symbol Se = "1" representing this final data is given to the timing circuit 3.

The other 1 bit is a signal SM having the content indicating the direction of the pattern to be output in the next cycle. As will be apparent from a later description, when the pattern end portion decreases toward 0 as in PF ₁ (t) and NF ₂ (t), it is necessary to secure the continuity of the output signal, and the next read The pattern must be NF ₁ (t), NF ₂ (t) where the beginning of the pattern decreases from 0, and conversely the end of the pattern like NF ₁ (t), PF ₂ (t) When increasing toward 0, the next read pattern is PF ₁ (t), PF where the beginning of the pattern increases from 0.
Must be ₂ (t).

Therefore, PF ₁ (t) and NF ₂ (t) should be read next as NF ₁ (t) and NF.
₂ (t) AH value “0”, NF ₁ (t), PF ₂ (t) should be read next
The AH value “1” of PF ₁ (t) and PF ₂ (t) is written in this 1 bit. This 1-bit signal S _M is given to the latch circuit 5.

The oscillator 1 uses a crystal oscillator, emits a basic clock signal of this device, and an output pulse is given to the frequency dividing circuit 2. The frequency dividing circuit 2 has a variable frequency dividing ratio by turning on and off a plurality of external contacts 2a, and the frequency dividing ratio is set according to the baud rate. When the output frequency of the frequency dividing circuit 2 is kept high, the baud rate is high, and when the output frequency is kept low, the baud rate is low. The output of the frequency dividing circuit 2 is given to the address counter 4 as a clock signal for stepping.

The basic clock signal output from the oscillator 1 is given to the timing circuit 3. The timing signal 3 is a circuit for delaying the final data signal Se = "1" read from the ROM 6 by an appropriate number of basic clock signals, and the delayed signal Se = "1" is used as a latch signal for the latch circuit 5. Further, it is given to the address counter 4 as a reset signal.

The aforementioned signal S _M and the binary signal S _IN to be modulated are input to the latch circuit 5, which are latched by the latch signal and become the address signals AH and AL of the ROM 6, respectively.

[Action]

Next, the operation of the above circuit will be described with reference to FIG. In the initial state, the latch circuit 5 is forcibly latched with predetermined 2-bit data or the like to read out one of the patterns and set the signal S _M to "1" or "0" to start the operation. Let

Assume that binary signals are input in the order of 1, 0, 1, 0 and the pattern PF ₁ (t) is read as the data corresponding to the first “1” (see FIG. 1).

At this time, AH, AL latched in the latch circuit 5 is (1,1). The output of the oscillator 1 changes as shown in FIG. 5B when the frequency dividing circuit 2 shown in FIG.
Is stepping forward. PF ₁ as the content of the address counter 4 will be incremented _{(t 0), PF 1 (} t 1), PF 1 (t 2) ... so it is sequentially read and D / A converter 7 outputs the frequency ₁ Will output the positive half-wave of. The output data of the ROM 6 is settled a little later than the time when the address of FIG. 5C is settled, as shown in FIG. 5D. The timing circuit 3 compensates for this delay as described later. During this period, the ROM 6 outputs "0" as the signal S _M. When the content of the address counter 4 becomes 2 ^k −1 = n, the final data PF ₁ (t _n ) is read and Se =
It becomes "1" [Fig. 5 (e)]. As shown in FIG. 5 (f), the timing circuit 3 delays the time required for D / A conversion of PF ₁ (t _n ) and supplies it to the latch circuit 5. Then, since the next S _IN is “0”, the latch circuit 5 latches (S _M , S _IN ) = (0, 0) and gives it to the ROM 6 as AH, AL. FIG. 5 (g) shows that the output of the latch circuit 5 has changed. On the other hand, since the address counter 4 is also reset as shown in FIG. 5C, the pattern of NF ₂ (t) will be read next in accordance with the progress of the contents, and the D / A converter 7 Will output one cycle of frequency ₂ starting from the negative side. During this period, S _M = “0”.

When the reading of the pattern of NF ₂ (t) is completed in this way, S _IN = “1” next time, so that the latch circuit 5 (S _M , S
_IN ) = (0,1) is latched, so the pattern of NF ₁ (t) is then read. Therefore, the negative half-wave of frequency ₁ is D / A
It is output from the converter 7, and during this period, S _M = “1”.

When the reading of the pattern of NF ₁ (t) is completed, then S _IN = “0”
Therefore, the latch circuit 5 has (S _M , S _IN ) = (1,0)
, Which will read the PF ₂ (t) pattern.

Since the circuit of the present invention repeats such an operation, the output of the D / A converter 7 is regularly and smoothly continuous so that it becomes positive to negative and negative to positive at the zero point.

Although not specifically exemplified, when 1, 1 or 0, 0 is continuous, a continuous change waveform of positive, negative, positive, negative ... Is obtained by setting S _M as described above.

〔effect〕

As described above, in the case of the present invention, the signal smoothly continues even in the frequency switching portion. Therefore, in the demodulation circuit, there is no need to take noise countermeasures at this switching portion, and the switching phase becomes constant, so that it is possible to allocate a minimum half cycle or one cycle to 1-bit data, thus improving the transmission efficiency. Can be raised to the limit.

Further, since the output waveform is determined by the data to be stored in the ROM 6, it is possible to obtain not only a sine wave but also an arbitrary output waveform such as a triangular wave and also an arbitrary peak value by changing this. . Also, the number of cycles assigned to 1 bit can be arbitrarily changed by changing the data stored in the ROM 6. Further, since the output waveform has the same data in the ROM 6 and the output frequency of the oscillator 1 does not change, there is no secular change and high reliability can be secured for a long period of time.

Furthermore, in the above-described embodiment, since the frequency dividing circuit 2 having a variable frequency dividing ratio is provided, for example, ₁ = 1200 Hz, ₂ = 2400 Hz to ₁
The present invention has an excellent effect such that the baud rate can be easily changed to = 600 Hz and ₂ = 1200 Hz.

Although the signals S _M and Se and the pattern data PF ₁ (t) are simultaneously read in the above-mentioned embodiment, the signals S _M and
By storing Se and pattern data in different areas of the ROM 6 and switching the read area each time the address counter advances, the number of bits of the pattern data in the same memory capacity can be increased.

Further, the oscillator 1 may be externally synchronized.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit of the present invention, FIGS. 2 and 3 are block diagrams of a conventional modulation circuit, FIG. 4 is a conceptual diagram of data stored in a ROM of the present invention, and FIG. 5 is a circuit of the present invention. 3 is a time chart for explaining the operation of FIG. 1 ... Oscillator, 2 ... Divider circuit, 3 ... Timing circuit, 4 ...
Address counter, 5 ... Latch circuit, 6 ... ROM, 7 ... D
/ A converter

Continuation of front page (56) References JP-A-56-48746 (JP, A)

Claims (1)

[Claims] 1. A modulation circuit for FSK-modulating a serial binary signal, wherein a half cycle of a first low frequency starting from 0 and an increase of 1 cycle of a first high frequency and a second low frequency starting from 0. A large number of time-series and discrete voltage level information representing patterns of one half cycle of the high frequency and one cycle of the second high frequency, and the increase of the end portion of each pattern,
A memory in which data indicating the decrease and the data indicating the end of each pattern are stored, data indicating the increase or decrease of the end of the pattern read immediately before from the memory, and the data to be modulated. A latch circuit for latching one bit of a binary signal and giving the latch contents to the memory as a higher-order address signal for specifying a storage area of each of the first, second low frequency or first, second high frequency A counter for counting clock signals having a cycle corresponding to the baud rate, and giving the count value to the memory as a lower address signal for specifying each of the time-series voltage level information of the pattern; Timing of giving a latch signal to the latch circuit and a clear signal to the counter according to the data stored in the memory and indicating the end of each pattern. Road and, modulation circuit characterized by comprising a digital / analog converter for digital / analog conversion on the voltage level information read from the memory.