JPH0543641U - IQ signal generator for digital modulation - Google Patents

Abstract

(57) [Abstract] [Purpose] A digital modulation I capable of generating modulation schemes that are different in principle by the same circuit configuration.
It is to realize a Q signal generator. In a digital modulation IQ signal generator for sequentially calling data from waveform data stored in advance in a storage element to generate an I signal and a Q signal, a timing signal generator, a timing signal generator and input data are The output of the shift register, the timing signal generator, and the one or more storage elements is connected to the latch, the timing signal generator is connected to the address counter, and the output of the address counter and the latch is used as an address. Alternatively, it is connected to a plurality of storage elements. When using a plurality of storage elements, a storage element selection circuit is connected between the shift register and the plurality of storage elements.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a modulation signal generator of each digital modulation method used in digital mobile communication, and more particularly to a device for digitally generating an IQ signal to be applied to a quadrature modulator from an input digital data string.

[0002]

[Prior Art]

 Digital modulation methods used in digital mobile communications include linear modulation such as "π / 4 shift QPSK (Quadri Phase Shift Keying)" used in Japan and the US, and "GMSK (Gaussian) used in Europe. -Frequency / phase modulation such as "filtered Minimum Shift Keying)" is often used. An example of each modulation method is shown in FIGS. 5 (A) and 5 (B). In FIG. 5, 1 is a phase calculation IQ signal generator, 2a, 2b and 3 are digital filters, 4 is a phase calculator, and 5 is an IQ signal generator. The input data strings 100 and 100a are modulated into I (Inphase) signals 101 and 101a and Q (Quadrature) signals 102 and 102a by the modulators shown in FIGS. 5A and 5B, respectively. Since these I signal and Q signal 101, 101a, 102, 102a are digital signals, they are converted into analog signals by a D / A converter, and the carrier is quadrature-modulated by these analog signals to obtain a target modulation signal. FIG. 6 shows another example of the frequency / phase modulation method. The input data string 100b is latched by the latch 8b, and its output becomes the address input of the ROM 6 together with the output of the address counter 10b. The output of the ROM 6 is further processed by an adder or the like, and then becomes an address input of the ROM 6a, 6b. The outputs of the ROMs 6a and 6b are D / A converted and input to the quadrature modulator.

[0003]

[Problems to be solved by the device]

 However, the modulation methods of π / 4 shift QPSK and GMSK are completely different in principle in terms of the generation method of the modulation waveform, so there are few common parts when trying to realize equipment that supports both methods. Therefore, it is necessary to individually provide a circuit corresponding to each modulation method, which increases the circuit scale and the cost. For this reason, there was a problem that equipment compatible with both methods had no advantage over dedicated machines of each method. Therefore, an object of the present invention is to realize an IQ signal generator for digital modulation, which in principle can generate modulation systems having different generation systems with the same circuit configuration.

[0004]

[Means for Solving the Problems]

 In order to achieve such an object, a first aspect of the present invention is a digital modulation IQ signal generator for sequentially calling data from waveform data stored in advance in a storage element to generate an I signal and a Q signal. A timing signal generator, a shift register having a digital data string as a data input, a latch having the output of the shift register as a part of the input, an address counter having the output of the timing signal generator as a clock input, The address counter and the output of the latch are used as address inputs, and a part of the output serves as another part of the input of the latch. A second aspect of the present invention is an IQ signal generator for digital modulation for sequentially calling data from waveform data stored in advance in a storage element to generate an I signal and a Q signal, a timing signal generator and a digital data string. , A latch whose input is the output of this shift register, an address counter whose clock input is the output of the timing signal generator, and a selection to which the output of the shift register is connected. A circuit, and a plurality of storage elements that are output from the address counter and the latch as an address input, a part of the output becomes another part of the input to the latch, and are selected by the output of the selection circuit. It is characterized by that.

[0005]

[Action]

 The storage element is divided into multiple areas by all the bit patterns that can be obtained by the shift register, data of different modulation schemes is stored in each area, and the waveform is generated by the output of the address counter that increases with each timing signal. By generating, each modulation signal is generated by the same circuit configuration regardless of the generation principle of the modulation method.

[0006]

【Example】

 Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an IQ signal generator for digital modulation according to the present invention. In FIG. 1, the output of the shift register 7 is connected to the latch 8, and the output of the latch 8 and the output of the address counter 10 are connected to the storage element 9 as an address. The output of the storage element 9 is output as a digital IQ signal 107. Further, a part of the output of the storage element 9 is fed back to the input of the storage element 9 via the latch 8. The timing generator 11 generates timing signals 104, 105 and 106. The timing signal 104 is input to the latch 8 and the address counter 10, the timing signal 105 is input to the address counter 10, and the timing signal 106 is input to the clock input of the shift register 7.

The operation of the embodiment shown in FIG. 1 will be described with reference to the timing chart of FIG. The serial input data 103 input for each timing signal 106 is put together for each timing signal 104 by the latch 8 and made into a part of the address of the storage element 9 as parallel data. The output of the address counter 10 that increases with each timing signal 105 is also input to the storage element 9 as a part of the address. Here, the address counter 10 is reset by the timing signal 104. The data of the address designated by the outputs of the latch 8 and the address counter 10 is output from the storage element 9 as the digital IQ signal 107 for each timing signal 105. Therefore, the storage element 9 is assigned to a plurality of areas according to all bit patterns (addresses) that can be obtained by the shift register 7, and the data calculated by each modulation method is written in the assigned areas. Then, each modulation method is selected by the output of the shift register 7, the address counter 10 is incremented for each timing signal 105, and the data of the selected modulation method is read, so that the common circuit configuration can be used regardless of the generation principle. Waveforms with various modulation methods can be generated.

However, in modulation methods such as π / 4 shift QPSK and GMSK, the waveform to be output is not determined only by the bit pattern of the input data, but the following waveform is defined as the difference from the immediately preceding output waveform. It Therefore, a part of the output of the storage element 9 is fed back to the input of the storage element 9 via the latch 8 to control this difference.

Since the capacity of the storage element 9 in FIG. 1 depends on the output bit length of the shift register 7, if the output bit length of the shift register 7 is set to be long, the storage capacity becomes too large to realize. It is also possible. This case can be solved by replacing the memory element 9 with the configuration shown in FIG. In the storage element circuit 9a of FIG. 3, 12 is an address compressor, 14 is a storage element, and 13 is a data converter. Here, instead of directly inputting / outputting data from / to the storage element, common data in the storage element 14 can be transferred to different addresses by controlling, for example, code inversion, exchange of I signal and Q signal, and the like. Allocate for input. Therefore, it is possible to effectively use the storage element and prevent an increase in storage capacity. FIG. 4 shows a second embodiment of the IQ signal generator for digital modulation according to the present invention, in which the storage element 9 in FIG. 1 is divided into a plurality of storage elements and is constituted by a storage element having a small storage capacity. It is a configuration block diagram. 4, the shift register 7a, the latch 8a, the address counter 10a, the timing generator 11a, the serial input data 103a, and the timing signals 104a to 106a are the same as those in FIG. Instead of the storage element 9 in FIG. 1, it is divided into a plurality of storage elements 9b, 9c and 9d, and data of different modulation methods is stored in each storage element. In the case of FIG. 4, a storage element selection circuit 15 for selecting a plurality of storage elements 9b, 9c and 9d is added. Further, it is possible to divide the plurality of storage elements 9b, 9c and 9d for each of the I signal and the Q signal. Therefore, since it is composed of a storage element with a small storage capacity, if a storage element can be added using an IC socket, etc., it can be easily supported by adding a storage element that stores data of another modulation method. You can increase or change the method.

[0010]

[Effect of the device]

 As is clear from the above description, the present invention has the following effects. The storage element 9 is divided into a plurality of areas by all bit patterns (addresses) that can be obtained by the shift register 7, data of different modulation schemes are stored in each area, and the data is increased for each timing signal 105. By generating a waveform by the output of the address counter 10, each modulation signal can be generated by the same circuit configuration regardless of the generation principle of the modulation method. As a result, the versatility, downsizing, and cost reduction of the device can be realized.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing a first embodiment of an IQ signal generator for digital modulation according to the present invention.

2 is a timing diagram illustrating the operation of the generator of FIG.

FIG. 3 is a partial configuration diagram showing a specific example of a storage element section of the generator shown in FIG.

FIG. 4 is a configuration diagram showing a second embodiment of an IQ signal generator for digital modulation.

FIG. 5 is a configuration diagram showing an example of a conventional IQ signal generator for digital modulation.

FIG. 6 is a configuration diagram showing another example of a conventional IQ signal generator for digital modulation.

[Explanation of symbols]

 1 Phase Calculation IQ Signal Generator 2, 3 Digital Filter 4 Phase Calculator 5 IQ Signal Generator 6 ROM 7 Shift Register 8 Latch 9, 14 Storage Element 10 Address Counter 11 Timing Generator 12 Address Compressor 13 Data Converter 15 Storage Element selection circuit 100, 103 Input data 101 I signal 102 Q signal 104, 105, 106 Timing signal 107 I / Q signal 108 Quadrature modulator

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[Procedure amendment]

[Submission date] November 6, 1991

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

Claims (2)

[Scope of utility model registration request] 1. An IQ signal generator for digital modulation for sequentially calling data from waveform data stored in advance in a storage element to generate an I signal and a Q signal, wherein a timing signal generator and a digital data string are data. A shift register as an input, a latch having the output of this shift register as a part of the input, an address counter having the output of the timing signal generator as a clock input, and an output of this address counter and the latch as an address input , And a storage element, a part of the output of which is the other part of the input of the latch, and an IQ signal generator for digital modulation. 2. An IQ signal generator for digital modulation for sequentially calling data from waveform data stored in advance in a storage element to generate an I signal and a Q signal, wherein a timing signal generator and a digital data string are data. A shift register as an input, a latch having an output of the shift register as a part of an input, an address counter having an output of the timing signal generator as a clock input, and a selection circuit to which an output of the shift register is connected The address counter and the output of the latch are used as address inputs, a part of the output becomes another part of the input of the latch, and a plurality of storage elements selected by the output of the selection circuit are provided. And an IQ signal generator for digital modulation.