JP2503568Y2 - Phase modulation circuit - Google Patents

Description

[Detailed Description of the Invention] (Industrial field of application) The present invention relates to a phase modulation circuit, and more particularly to a DDS (Digital Dir
ect Synthesizer).

(Prior Art) Long-distance communication is used as a means for transmitting information over a long distance, and the method is carried by placing information to be transmitted on a carrier wave and transmitting the carrier wave. The means for putting this signal on the carrier wave is modulation. There are three types of modulation. Amplitude modulation is a method of changing the amplitude of a carrier wave in proportion to the amplitude of a signal to be transmitted, frequency modulation is a method of changing the frequency of a carrier wave in proportion to the amplitude of a signal, and phase modulation is the method of changing the phase of a carrier wave in a signal. This is a method of changing in proportion to the amplitude. Phase modulation is generally represented by the following equation.

f (t) = Asin {ωt + aV (t)} where A ... Carrier amplitude ω ... Carrier angular frequency a ... Modulation index V (t) ... Modulation signal Phase modulation is essentially the same as frequency modulation, Since the amplitude of the carrier wave is constant, it is resistant to noise.

(Problems to be Solved by the Invention) As a phase modulation method, a cerasoid modulator is used as an analog modulation method, but it is quite troublesome, and there is no simple method of performing it by a digital method.

The present invention has been made in view of the above points, and an object thereof is to realize a digital phase modulation circuit capable of relatively easily performing phase modulation.

(Means for Solving the Problems) The present invention for solving the above problems can output a phase-modulated signal by inputting frequency setting data of a carrier wave, frequency setting data of a modulated wave, and a modulation index. A phase modulation circuit capable of inputting the frequency setting data of the carrier, cumulatively adding the frequency setting data for each clock, and outputting a result of addition, a carrier setting gate array (11), and the frequency of the modulated wave. Input the setting data, cumulatively add the frequency setting data for each clock, and output the addition result. The modulation wave setting gate array (12) and the output of the modulation wave setting gate array (12) are used as addresses. A first sine wave memory (13) from which the stored sine wave data is read out at every clock, and output sine wave data of the first sine wave memory (13) and 1
A subtractor (14) for obtaining a difference from the sine wave data output before the clock, a multiplier (15) for obtaining a product of the modulation index and the output data of the subtractor (14), and the carrier setting device Adder (16) for adding and outputting the output of the gate array (11) and the output of the multiplier (15)
A second sine wave memory (17) that stores sine wave amplitude data that outputs a phase-modulated signal using the output of the adder (16) as a read address, and the second sine wave memory (17). And a DA converter (18) for converting the digital signal output from (17) to an analog signal and outputting the analog signal.

(Function) Input the frequency setting data to the DDS for modulating wave setting and
The differential form is calculated by subtracting from the output before the clock, multiplied by the modulation index, and the sine wave phase-modulated in addition to the sequence of multiples of the carrier frequency setting data is read from the second sine wave ROM and the digital phase Modulate.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. By the way, first, the DDS which is the basic circuit of the embodiment of the present invention will be explained. FIG. 2 is a block diagram of DDS. In the figure,
1, the frequency setting data D _S is input to the A terminal and the addition output is input to the B terminal, and D _S , 2D _S , 3 for each clock input.
A gate array 2 for outputting D _S ... Is a ROM in which data of amplitudes forming a sine wave is written in the order of each address. The output of the ROM 2 is converted into an analog signal in the DA converter 3 to output a sine wave as shown in FIG. The relationship between the frequency setting data and the output frequency will be described with reference to FIG. In the figure, the horizontal axis shows the address of ROM2, and the vertical axis shows the amplitude data stored at each address of ROM2.

Now, assuming that the frequency setting data is D _S , the gate array 1
Then, the cumulative addition value of the tolerance D _S is input to the ROM 2 and the data indicated by the black circles in FIG. 4 is output to the DA converter 3. At this time, the frequency of the output signal is determined by the frequency of the clock that operates the DDS and the frequency setting data. For example, if the DDS is operated at the clock frequency fc, the frequency setting data D _S has the clock cycle 1 / fc in the order of D _S , 2D _S , 3D _S ....
Since the address is specified in the ROM2, a signal having a frequency represented by (1 / fc) × n _D (n _D is the number of data for one period, 10 in the example of FIG. 4) is output. Here, since the frequency of the clock that operates the DDS is constant, N _D is changed to change the frequency. However, n _D is changed by changing the frequency setting data D _S. Fifth
In the figure, for both sine waves in (a) and (b), n _D is 10
Since the signals have the same frequency because they are individual, in the figure (a), the first black circle data starts from 0,
In the (b) diagram, a signal having a waveform that leads the waveform of the (b) diagram by D _α is output. When this D _α is changed periodically, a phase-modulated signal whose phase changes periodically appears at the output.

Next, the circuit of the embodiment shown in FIG. 1 will be described. In the figure,
Reference numeral 11 denotes a carrier setting gate array that operates similarly to the gate array 1 shown in FIG. 2, and outputs an address D _C for reading the frequency designated by the frequency setting data input for each clock. The frequency setting data input to the gate array 11 is data for setting the carrier frequency of the signal to be transmitted. Reference numeral 12 is a gate array for explaining the modulated wave, which similarly outputs the cumulative addition value of the frequency setting data for each clock and reads the sine wave amplitude data stored in the first sine wave ROM 13 to obtain the modulated wave. The first sine wave ROM 13 outputs the modulated wave D _n read by the address of the output of the modulated wave setting gate array 12. 14 is the output D _n of the first sine wave ROM 13 and 1
It is a subtracter that outputs a signal D _α that is the difference from the output D _n−1 read out before the clock.

Reference numeral 15 is a multiplier which outputs the product of the output D _α of the subtractor 14 and the set modulation index n, and the output nD _{α of which} is input to the adder 16. The adder 16 receives the output D _C of the carrier wave gate array 11 and the output nD _α of the multiplier 15 and adds them, and outputs the read address D _β of the second sine wave ROM 17. The second sine wave ROM 17 is read by the address D _β, and the modulated signal in which the carrier wave is phase-modulated is output. Reference numeral 18 is a DA converter for converting the digital signal output of the second sine wave ROM 17 into an analog signal, and 19 is a clock generator for generating a clock for the operation reference of the above-mentioned respective parts.

Next, the operation of the embodiment configured as described above will be described. The carrier frequency setting data is input to the carrier setting gate array 11. The carrier setting gate array 11 outputs D _C , which is the cumulative addition value of the frequency setting data, and the adder 16
To enter.

On the other hand, the modulated wave frequency setting data is input to the modulated wave setting gate array 12 and outputs an address for reading the modulated wave frequency signal, and the first sine wave ROM 13 outputs the sine wave data D _{n according} to the address. To do. D _n is a subtractor 14
The first sine wave ROM1 that was input to and output one clock before
The difference D _{α from} the output of 3 is obtained. D _α is expressed by the following equation.

Phase difference between θ ... D _n and D _{n-1 As} is clear from the equation (1), the output D _α of the subtractor 14 is the input
This is a signal that is the differentiated form of D _n .

This signal D _α is input to the multiplier 15 to output nD _{α which} is the product of the modulation index n, and the adder 16 receives the output D _C of the carrier gate array 11 and the output nD _{α of the} multiplier 15. It has been added, and outputs the read address D _beta of the second sine-wave ROM 17.

D _β = D _C + nD _α (2) The second sine wave ROM 17 outputs the amplitude data stored at the read address D _β . This read address D _β is obtained by adding the D _α shown in the equation (1), which changes according to the frequency setting data, to the address D _C of the carrier as shown in the equation (2), and the output of the second sine wave ROM 17 is the fifth. As shown in the figure, the carrier wave is a signal whose phase is modulated by a modulated wave, which is converted into an analog signal by the DA converter 18 and output. The modulation factor of this output signal is determined by the modulation index n.

As described above, according to the present embodiment, since it is a digital signal until it is output from the DA converter, a phase modulation circuit resistant to noise can be obtained, and since it is composed of a digital circuit, the circuit It is possible to realize a phase modulation circuit that does not cause a difference in performance due to variations in the elements forming the.

(Effect of the Invention) Various phase-modulated signals can be easily changed and output only by instructing the frequency setting data of the carrier wave, the frequency setting data of the modulated wave, and the modulation index.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a DDS used in the embodiment of the present invention, FIG. 3 is a diagram of an output signal of the DDS, and FIG. 4 is frequency setting data. FIG. 5 is a diagram showing the relationship with the output frequency, and FIG. 5 is an explanatory diagram of phase modulation by DDS. 1 ... Gate array, 2 ... ROM 3,18 ... DA converter 11 ... Carrier setting gate array 12 ... Modulation wave setting gate array 13 ... First sine wave ROM 14 ... Subtractor, 15 ... Multiplier 16 ... Adder , 17 ... Second sine wave ROM 19 ... Clock generator

Claims (1)

(57) [Scope of utility model registration request] 1. A phase modulation circuit capable of outputting a phase-modulated signal by inputting frequency setting data of a carrier wave, frequency setting data of a modulated wave, and a modulation index, the frequency setting data of the carrier wave. , And a gate array (11) for carrier setting that cumulatively adds the frequency setting data and outputs the addition result for each clock, and the frequency setting data of the modulated wave is input, and the frequency setting data is input for each clock. A modulation wave setting gate array (12) that cumulatively adds and outputs an addition result, and sine wave data that is stored with the output of the modulation setting gate array (12) as an address is read for each clock. A sine wave memory (13), and a subtractor (14) for obtaining a difference between the sine wave data output from the first sine wave memory (13) and the sine wave data output one clock before. A multiplier (15) for obtaining a product of the modulation index and the output data of the subtractor (14), and an output of the gate array (11) for setting the carrier wave and an output of the multiplier (15) Adder (16)
A second sine wave memory (17) that stores sine wave amplitude data that outputs a phase-modulated signal using the output of the adder (16) as a read address, and the second sine wave memory (17). And a DA converter (18) for converting the digital signal output from (17) to an analog signal and outputting the analog signal.