JPH01103097U - - Google Patents
Info
- Publication number
- JPH01103097U JPH01103097U JP19582887U JP19582887U JPH01103097U JP H01103097 U JPH01103097 U JP H01103097U JP 19582887 U JP19582887 U JP 19582887U JP 19582887 U JP19582887 U JP 19582887U JP H01103097 U JPH01103097 U JP H01103097U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flops
- series
- circuit
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
図は本考案の一実施例のシフトレジスタの構成
図である。 １…第１クロツク、２…第２クロツク、３…第
３クロツク、４…入力信号、１１〜１３，２１〜
２３，３１〜３３…フリツプフロツプ。
図である。 １…第１クロツク、２…第２クロツク、３…第
３クロツク、４…入力信号、１１〜１３，２１〜
２３，３１〜３３…フリツプフロツプ。
Claims (1)
- フリツプフロツプを使つたデイジタル回路にお
いて、Ｎ個のフリツプフロツプのデータ入出力を
直列に接続した回路とＮ個の各フリツプフロツプ
の後位に直列に接続した複数個のフリツプフロツ
プから成ることを特徴とするシフトレジスタ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19582887U JPH01103097U (ja) | 1987-12-25 | 1987-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19582887U JPH01103097U (ja) | 1987-12-25 | 1987-12-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01103097U true JPH01103097U (ja) | 1989-07-12 |
Family
ID=31486484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19582887U Pending JPH01103097U (ja) | 1987-12-25 | 1987-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01103097U (ja) |
-
1987
- 1987-12-25 JP JP19582887U patent/JPH01103097U/ja active Pending