JPH01103085A - Arithmetic mean calculation device - Google Patents

Abstract

PURPOSE:To always obtain the result of calculation from same data output terminal by shifting a final addition result toward a high-order bit by a prescribed bit number in response to the number of times of arithmetic operation and storing the result to a memory. CONSTITUTION:Suppose that 8-bit data addition is applied N times at maximum, then in applying the addition of M time less than the number N, the data outputted from a digital adder 1 while final addition is applied is shifted toward high-order by (log2N-log2M) bits and transferred to a frame memory 2. That is, if the circuit is constituted so as to apply addition of N times at maximum, the data outputted from the digital adder 1 has (8+log2N) bits. As the number of times of addition N (N>M) is increased, the shift quantity of the shift circuit 4 is decreased and in case of N time addition, the result is transferred to a frame memory 2 without data shift.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic averaging device that calculates an arithmetic average of augend data.

(Prior Art) Generally, it is well known that an averaging device is an important means in various signal processing techniques.

For example, by adding together multiple signals detected under conditions of
If the average value of the added values is used as a signal under that condition, an effect such as being able to remove unnecessary signals such as noise can be obtained.

FIG. 4 shows an example of a conventional averaging calculation device.

First, to explain the configuration, in the figure, 1 is a digital adder, 2 is a frame memory, and 3 is a microprocessor. An input terminal for manually inputting D(1) and a digital video signal R(1) stored in the frame memory 2 and read out for performing an addition operation with the digital video signal 0(1). and other input terminals, and frame the data of the addition result.
It is connected to output to memory 2. For example, one input terminal is connected to eight data signal lines to input the digital video signal D(1) consisting of 8-bit digital data, and the other input terminal is connected to the maximum number of addition operations n. (8 + log
, N ) data signal lines are connected so that data R(i) is supplied, and further (8+10g2N
) are connected to output the data of the addition result to the frame memory 2 by data signal lines. That is,
The frame memory 2 has a large number of storage addresses for storing a large number of data corresponding to each pixel of one frame, for example, and the storage bits assigned to each storage address are also (8+logzN) bits. The bit length is set so that the data from the digital adder 1 can be stored.

The microprocessor 3 receives the averaged data read out via (8+101hN) data signal lines, and performs various signal processing.

(Problems to be Solved by the Invention) However, such conventional addition and averaging calculation devices have the following problems. That is, when the addition operation is repeated, the data of the operation result gradually shifts to the higher bit side according to the number of additions, so when the microprocessor 3 reads from the frame memory 2, (8+log
The problem is which bit range of the 2 N ) bits should be read as true data. Conventionally, for example, when using an 8-bit microprocessor, (8
+log2N) bit data cannot be input in one read operation, so the same data is manually input to the internal arithmetic register by reading (8+log2N): 8 times, and then some program is input. The process was used to identify the true data. For this reason, there have been problems such as complicated processing and a significant delay in processing speed.

(Means for Solving the Problems) The present invention has been made in view of such conventional problems, and includes an adder that performs an addition operation on a pair of augend data, and an addend that performs an addition operation on a pair of augend data. and a storage device that stores the addition results of the addition device, and inputs new augend data to one input terminal of the addition device, and inputs data of each addition operation result output from the storage device to the other input terminal of the addition device. In an addition calculation averaging device configured to perform calculations on a plurality of augend data by repeating addition calculations, output is made to the adder by a number of addition operations M within a preset maximum number of additions N. The final data (log, N
The present invention is characterized in that it includes a shift means for shifting -1oN-1o bits to the upper bit side and transmitting the result to the storage device, thereby making it possible to always read the operation result from the same terminal of the storage device. .

(Embodiment) Hereinafter, one embodiment of the averaging device according to the present invention will be described as a first embodiment.
This will be explained based on the diagram. In addition, in the same figure, the same as Fig. 4.
Or corresponding parts are indicated by the same reference numerals.

To explain the different parts from FIG. 4, the digital adder 1
A shift circuit 4 is provided between the output of the frame memory 2 and the input of the frame memory 2. That is, when the final addition operation is performed, the shift circuit 4 shifts the (8 + 10g2 N ) bit operation result output from the digital adder 1 to the upper bit side by a predetermined number according to the number of addition operations. It has the function of shifting the data to the frame memory 2 and transferring it to the frame memory 2. For example, if the circuit is configured so that addition operations on 8-bit data can be performed a maximum of N times as shown in the figure, when performing addition operations M times less than the number N, the final The data output from the digital adder 1 after the addition operation is calculated as (log2N-10gz
M) Move up by one bit and transfer to frame memory 2. That is, if the circuit is configured to perform addition operations a maximum of N times, the data output from the digital adder l will be (8+tog2N) bits. Then, as the number of additions M (where N>ME) increases, the shift amount of the shift circuit 4 decreases, and when performing N addition operations, the data is transferred to the frame memory 2 without being shifted. Further, the above shift operation is performed only when the final addition operation is performed, and during the operation less than the predetermined number m, the data is transferred to the frame memory 2 without performing a shift operation.

FIG. 2 is a block diagram showing a specific example of the shift circuit 4. As shown in FIG. In the figure, 5 is a shift register that presets each bit data and serially transfers it to the upper side, and inputs corresponding to each internal bit to (8+log2M) data transfer lines from digital adder 1. Terminal ■. ~I
, -1 are connected, and the output terminals Q0 to Q, -1 corresponding to each internal bit are connected in parallel to the data input terminal of the frame 4 memory 2 to write data.

On the other hand, the data read from the frame memory 2 is fed back to one input terminal of the digital adder 1, and a data transfer line for transferring the upper 8 bits of the data is connected to the microprocessor 308 bits. data input terminal. -D, is connected. Note that the shift operation of the shift register 5 is performed by the clock signal S supplied to the terminal CK.
, is carried out in synchronization with .

The operation of such a circuit will now be explained. For example, D(0), D(
1), D(2), D(3), and D(4), and specifically assume that each data is “o”.
, o, o, o, o, skin 0.1'', and the maximum number of operations n is 8. In other words, the number of data transfer lines from the digital adder 1 to the frame memory 2 is 11 (=
8 + log28).

First, at the start of calculation, the first frame memory 2
Clear the data R(0) inside. Therefore, the data in frame memory 2 is R(0) = “o,
o, o, o, o, o, o, o, o, o
, o”.

In the first calculation, R (1) = R (0) + Q (0) = “O, O, 0
,0,O,0,0,O,0,0,1'', which is stored in the frame memory 2.

In the second operation, R(2)=R(1)+D(1)=”O,O,0,0,
0,0,0,0,0,1,O''.

In the third calculation, R(3) = R(2) 10 (2) = “0.0
．． 0.0.0.0.0.0.1.1'.

Similarly, in the fourth operation, R(3) +Q (3) = '“O,O,0,0,O
,O,0,1,0,0''.Here, the number of additions m=
4, shift register 5 is (logz N
log2M), that is, it is moved up by 1 bit and transferred to frame memory 2, so what is finally stored in frame memory 2 is ' R (4) = "0.0.0.0.0 .0.
0.1.0.0. O”.

Then, as mentioned above, the upper 8 of frame memory 2
Since the data signal line of the bit is connected to the data signal line of the microprocessor 3,
reads the calculation result from the frame memory 2 and directly calculates the calculation result of the addition average “0,0°0,0.O,O
, O, l" can be obtained.

As described above, according to this embodiment, the final calculation result is shifted to the upper bit side by a predetermined number of bits corresponding to the number of calculations and is stored in the memory, so that the calculation result can always be obtained from the same data output terminal. This is highly effective in simplifying processing using this signal.

In FIG. 3, instead of the shift register 5 shown in FIG.
A case is shown in which a plurality of multiplexer circuits 6 are used. That is, a data transfer line from the digital adder 1 to each multiplexer. .

I, , I, , I3 ~ are connected, and the on/off of the internal switching transistor group is controlled by the signal level of the channel switching control signals CH, -CH3, so that a desired number of bit shifts can be performed. According to this embodiment, the circuit configuration can be simplified.

(Effects of the Invention) As described above, according to the present invention, the present invention includes an adder that performs an addition operation on a pair of augend data, and a storage device that stores the addition result of the pair of augend data. By manually inputting new augend data to one input terminal of the adding device and data of each addition operation result outputted from the storage device to the other input terminal of the adding device, and repeating the addition operation, operations can be performed on multiple augend data. In an addition/average device configured to perform the above operations, the final addition operation result is shifted to the upper bit side by a predetermined number of bits depending on the number of operations and is stored in the memory, so that the operation is always performed from the same data output terminal. It is possible to obtain results, and it is highly effective in simplifying processing using this signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the averaging device according to the present invention, FIG. 2 is a block diagram illustrating the configuration of the shift circuit in FIG. 1, and FIG. 3 is an implementation of another shift circuit. Block Diagram Showing an Example FIG. 4 is a block diagram showing an example of a conventional arithmetic averaging device. 1: Digital adder 2; Frame memory 3: Shift circuit 5: Shift register 6: Multiplexer

Claims (1)

[Claims] The adder includes an adder that performs an addition operation on a pair of augend data, and a storage device that stores the addition result of the pair of augend data, and a new augend data,
In an addition calculation averaging device configured to perform calculations on a plurality of augend data by inputting data of each addition calculation result output from the storage device to the other input terminal and repeating the addition calculation, The final data output to the adder by the addition operation M times within the preset maximum number N of additions is (
What is claimed is: 1. An averaging arithmetic device comprising: a shift means for shifting log_2N-log_2M) bits toward higher-order bits and transferring the shifted data to the storage device.