JPH0833920B2 - Video signal arithmetic mean - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic mean calculating device for calculating an arithmetic mean of digital video signals.

(Prior Art) It is well known that an arithmetic mean device is generally an important means in various signal processing techniques. For example, when a plurality of signals detected under a certain condition are added and the average value of the added values is used as the signal under the condition, an unnecessary signal such as noise can be removed.

FIG. 4 shows an example of a conventional arithmetic mean calculation device. First, the configuration will be described. In the figure, 1 is a digital adder,
Reference numeral 2 is a frame memory, 3 is a microprocessor, and the digital adder 1 has an input terminal for inputting a digital video signal D (i) of a subject image photographed by, for example, a video camera, and a frame memory once. 2 and another input terminal for inputting the digital video signal R (i) read out for performing addition operation with the digital video signal D (i). -It is connected to output to the memory 2. For example, one input terminal is connected to eight data signal lines for inputting a digital video signal D (i) consisting of 8-bit digital data, and the other input terminal has the maximum number of addition operations n. (8 + log ₂ N) (where N = 2 ^a and a is an integer) data signal lines are connected so that the data R (i) is supplied. ₂ N) data signal lines are connected so as to output the data of the addition result to the frame memory 2. That is, the frame memory 2 has, for example, a large number of storage addresses for storing a large number of data corresponding to each pixel for one frame, and the storage bit assigned to each storage address is also (8 + log ₂ N ) Bits, and the bit length is set so that the data from the digital adder 1 can be stored.

The microprocessor 3 receives the data after the addition and averaging read through the (8 + log ₂ N) data signal lines, and performs various signal processing.

(Problems to be Solved by the Invention) However, such a conventional arithmetic mean calculation device has the following problems. That is, when the addition operation is repeated, the data of the operation result is gradually shifted to the higher-order bit side according to the number of times of addition, so that when the microprocessor 3 reads from the frame memory 2 (8 + log
_The problem is which bit range of ₂ N) bits is read as true data. Conventionally, for example, when using an 8-bit microprocessor, (8 + log ₂
Since it is not possible to input N) bit data in one read operation, the same data [[8 + log
₂ N) ÷ 8] times are input to the internal arithmetic register, and then true data is identified by some program processing. For this reason,
There is a problem that the processing becomes complicated and the processing speed is significantly delayed.

(Means for Solving the Problems) The present invention has been made in view of the above-mentioned conventional problems, and an adder for performing an addition operation of a pair of digital video signals and the pair of digital video signals. And a frame memory for storing the addition result of the addition device, and input a new digital video signal to one input terminal of the addition device and data of each addition operation result output from the frame memory to the other input terminal. in addition operation average unit configured comprising to perform operations on a plurality of digital video signals by repeating the addition operation, the maximum number of times of addition times within N M (but that is set in advance, b in M = 2 ^b multi pre transferring integer.) add operation by the final data output to the adder _{(log 2 N-log 2 M} ) bits by shifting to the upper bit side and to the frame memory of Characterized by comprising a support, thereby at all times that to be able to read the operation result from the same terminal of the frame memory.

(Example) Hereinafter, one example of an arithmetic mean calculation device according to the present invention will be described.
It will be described with reference to FIG. In the figure, parts that are the same as or correspond to those in FIG. 4 are denoted by the same symbols.

First, explaining the part different from FIG. 4, a shift circuit 4 is provided between the output of the digital adder 1 and the input of the frame memory 2.

That is, the shift circuit 4 outputs the operation result of (8 + log ₂ N) bits output from the digital adder 1 to the upper bit side by a predetermined number according to the number of addition operations when the final addition operation is performed. It has a function of shifting and transferring to the frame memory 2. For example, assuming that the circuit configuration is such that the addition operation of 8-bit data can be performed N times at the maximum as shown in the figure, when the addition operation is performed M times, which is less than N times, The data output from the digital adder 1 after the addition operation is performed (log ₂
Only N-log ₂ M) bits are moved up and transferred to the frame memory 2. That is, assuming that the circuit is configured to perform the addition operation at maximum N times, the data output from the digital adder 1 is (8 + log ₂ N) bits. And
As the number of additions M (where N> M) increases, the shift amount of the shift circuit 4 decreases, and when N addition operations are performed, data is transferred to the frame memory 2 without shifting. Further, the above shift operation is performed only when the final addition operation is performed, and during the operation less than the predetermined number of times m, the shift operation is performed so as to transfer to the frame memory 2 without performing the shift operation.

FIG. 2 is a block diagram showing a specific example of the shift circuit 4. In the figure, 5 is a shift register that presets each bit data and serially transfers it to the upper side, and corresponds to each bit inside (8 + log ₂ M) data transfer lines from the digital adder 1. Input terminals I _{0 to} I _b-1 are connected, and output terminals Q _{0 to} Q corresponding to the respective internal bits are connected.
_b-1 is connected in parallel to the data input terminal of the frame memory 2 to write data.

On the other hand, the data read from the frame memory 2 is fed back to one input terminal of the digital adder 1, and a data transfer line for transferring the upper 8 bits of the data is connected to the microprocessor 3. It is connected to 8-bit data input terminals D _{0 to} D ₇ . The shift register 5
The shift operation is performed in synchronization with the clock signal S _K supplied to the terminal CK.

 The operation of such a circuit will be described.

For example, D (0), D (1), D (2), D (3), D (4)
It is assumed that the arithmetic mean calculation is performed, specifically each data is "0,0,0,0,0,0,0,1", and the maximum number of calculations n is 8. That is, the data transfer line of the digital adder 1 to the frame memory 2 has a eleven _{(= 8 + log 2 8)} .

First, at the start of calculation, the data R (0) in the first frame memory 2 is cleared. Therefore,
The data in the frame memory 2 is R (0) = “0,0,0,0,0,0,0,0,0,0,0”.

In the first calculation, R (1) = R (0) + D (0) = “0,0,0,0,0,0,0,0,0,
0,1 ", which is stored in the frame memory 2.

In the second calculation, R (2) = R (1) + D (1) = “0,0,0,0,0,0,0,0,0,
It becomes 1,0 ".

In the third calculation, R (3) = R (2) + D (2) = “0,0,0,0,0,0,0,0,1,
1 ".

Similarly, in the fourth calculation, R (3) + D (3) = “0,0,0,0,0,0,0,1,0,0”.
Here, since the number of additions m = 4, the shift register 5 moves (log ₂ N−log ₂ M), that is, 1 bit to the upper side and transfers it to the frame memory 2. What is stored in 2 is R (4) = "0,0,0,0,0,0,0,1,0,0,0".

Then, as described above, since the upper 8-bit data signal line of the frame memory 2 is connected to the data signal line of the microprocessor 3, the microprocessor 3 can read the calculation result from the frame memory 2. Can directly obtain the arithmetic result “0,0,0,0,0,0,0,1”.

As described above, according to this embodiment, since the final operation result is shifted to the upper bit side by a predetermined number of bits according to the number of operations and stored in the memory, the operation result can always be obtained from the same data output terminal. Therefore, it is possible to exert a great effect on simplification of processing using this signal.

FIG. 3 shows a case where a plurality of multiplexer circuits 6 are used instead of the shift register 5 shown in FIG. That is, the data transfer lines I ₀ , I ₁ , I ₂ , I ₃ ... from the digital adder 1 are connected to the inputs of the respective multiplexers, and the internal signals are set according to the signal levels of the channel switching control signals CH ₁ -CH ₅ . The wiring is arranged so as to control the ON / OFF of the switching transistor group to perform a desired number of bit shifts. According to this embodiment, the circuit configuration can be processed easily and at high speed.

(Effect of the Invention) As described above, according to the present invention, it has only an adder that performs addition operation of a pair of digital video signals and a frame memory that stores the addition result of the pair of digital video signals ( That is, no additional storage circuit or register is needed.), A new digital video signal is input to one input terminal of the adder, and data of each addition operation result output from the frame memory to the other input terminal. In an addition arithmetic averaging device configured to perform arithmetic operations on a plurality of digital video signals by repeating input arithmetic operation, the final addition arithmetic result is a predetermined number of high-order bits according to the number of arithmetic operations. Since it is shifted to the side via the multiplexer and stored in the frame memory, the calculation result can always be obtained at high speed from the same data output terminal,
This has a great effect on simplification of video signal processing using this digital signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an arithmetic mean calculation device according to the present invention, FIG. 2 is a block diagram for explaining the configuration of the shift circuit in FIG. 1, and FIG.
A block diagram showing an embodiment of the present invention realized by a Plexer,
FIG. 4 is a block diagram showing an example of a conventional arithmetic mean calculation device having no shift circuit. 1: Digital adder 2: Frame memory 3: Shift circuit 5: Shift register 6: Multiplexer

Claims (1)

[Claims] 1. An adder for performing addition operation of a pair of digital video signals, and a frame memory for storing a result of addition of the pair of digital video signals, wherein a new digital signal is provided to one input terminal of the adder. Video signal addition, which is configured to perform arithmetic operations on a plurality of digital video signals by inputting the data of each addition operation result output from the frame memory to the other input terminal and repeating the addition operation In the arithmetic averaging device, the number of times M (N = 2 ^a , M = 2 ^b , a and b are integers) within a preset maximum number of times of addition N is added and output to the adder. The final data (log ₂ N
-Log ₂ M) bits are shifted to the upper bit side and transferred to the frame memory, and a video signal arithmetic mean device is provided.