JP7787696B2 - Power conversion device and control method for power conversion device - Google Patents

Description

The present invention relates to a power conversion device and a control method thereof, for example, a resonant power conversion device equipped with multiple switching elements, a capacitor, and a transformer, and a control method thereof.

Resonant power conversion devices are described, for example, in Patent Documents 1 and 2. Patent Documents 1 and 2 describe resonant power conversion devices that can detect or determine fluctuations in the resonant frequency.

JP 2017-184599 A JP 2019-201455 A

A resonant power converter comprises multiple switching elements, a capacitor, and a transformer with a primary winding connected in series with the capacitor. The inventors' investigations have revealed that when the load on the resonant power converter suddenly changes, for example to a high load, the resonant frequency of the series resonant circuit formed by the capacitor and primary winding deviates from the frequency at which the multiple switching elements turn on and off (off-resonance), causing current to flow through the switching elements and increasing surge voltage and noise. The inventors' investigations will be explained later using drawings.

The object of the present invention is to provide a power conversion device and a control method for a power conversion device that can suppress increases in surge voltage and noise when resonance is lost.

Other objects and novel features of the present invention will become apparent from the description and accompanying drawings of this specification.

A brief overview of representative embodiments disclosed in this application is as follows:

That is, the power conversion device includes a switching circuit having multiple switching elements, a capacitor, and a transformer with a primary winding connected in series with the capacitor; a gate drive circuit that outputs a gate drive current to the gates of the switching elements to control the on/off of the switching elements; a detection circuit that detects the current flowing through the switching circuit; and a judgment circuit that judges whether the polarity of the current detected by the detection circuit has been reversed. Here, the gate drive circuit includes a gate adjustment circuit that adjusts the gate drive current based on the result of the judgment by the judgment circuit.

To briefly explain the effect achieved by a representative embodiment of the invention disclosed in this application, it is possible to provide a power conversion device that can suppress increases in surge voltage and noise when off-resonance occurs.

1 is a circuit diagram showing a configuration of a power conversion device according to a first embodiment; 1 is a block diagram showing a configuration of a gate drive circuit according to a first embodiment; 1 is a circuit diagram showing a configuration of a gate output circuit according to a first embodiment; 4 is a flowchart for explaining a control method according to the first embodiment. 3 is a waveform diagram for explaining the operation of the power conversion device according to the first embodiment. FIG. 3 is a waveform diagram for explaining the operation of the power conversion device according to the first embodiment. FIG. 1 is a cross-sectional view showing the structure of a GaN-HEMT used in a power conversion device according to a first embodiment. FIG. 10 is a circuit diagram showing a configuration of a gate output circuit according to a second embodiment. FIG. 10 is a circuit diagram showing a configuration of a power conversion device according to a third embodiment. FIG. 10 is a circuit diagram showing a configuration of a power conversion device according to a fourth embodiment. FIG. 10 is a plan view showing a part of a semiconductor chip according to a fourth embodiment. FIG. 1 is a circuit diagram of a power conversion device for explaining the study by the present inventors.

Embodiments will be described with reference to the drawings. Note that the embodiments described below do not limit the invention as claimed, and not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the invention.

Before describing the embodiments of the present invention, we will explain the issues with the power conversion device that the inventors have investigated, with reference to Figure 12.

Figure 12 is a circuit diagram of a power conversion device used to explain the inventor's research. In the following, this specification will use as an example a highly efficient LLC resonant power conversion device that uses a transformer's leakage inductor and excitation inductor, and a capacitor coupled to the transformer.

In Figure 12, reference numeral 100 denotes a power conversion device (hereinafter also referred to as a DC/DC converter). The DC/DC converter 100 includes a gate drive circuit 2 and the primary and secondary circuits described below. It converts the voltage of a DC power source Vi supplied to the primary circuit and supplies the converted DC voltage to a load 4 connected to the secondary circuit. The primary circuit includes a half-bridge circuit 1 composed of switching elements Q1 and Q2, a resonant capacitor (current resonant capacitor) Cr, and a transformer Tr. The secondary circuit includes a rectifier circuit 3 composed of diodes D1 and D2 and a smoothing capacitor Co.

The two switching elements Q1 and Q2 that make up the half-bridge circuit 1 are driven by the gate drive circuit 2. That is, the gate drive circuit 2 alternately switches the switching elements Q1 and Q2 at a predetermined cycle, while providing a dead time (a time during which both switching elements are off). The value of the voltage output from the secondary circuit is adjusted by alternately switching the switching elements Q1 and Q2 at a predetermined cycle. In this case, the predetermined cycle for alternately switching the switching elements Q1 and Q2 is the operating cycle of the DC/DC converter 100 (in other words, the operating frequency of the DC/DC converter).

The LLC resonant DC/DC converter 100 uses a series resonant circuit composed of a resonant capacitor Cr and the leakage inductance (not shown) and magnetizing inductance included in the transformer Tr. Zero voltage (current) switching is performed to switch the switching elements Q1 and Q2 on and off when at least one of the voltages or currents of the switching elements Q1 and Q2 becomes zero ("0"). Zero voltage switching makes it possible to reduce power loss and switching noise when the switching elements are switched.

However, if the voltage value of the input-side DC power supply Vi or the output-side load 4 deviates from the design value, the resonant frequency of the series resonant circuit described above may fluctuate, causing the operating frequency of the DC/DC converter 100 to deviate from the resonant frequency. In this case, zero-voltage switching will no longer be possible, resulting in increased power loss, the generation of switching noise, and damage to the switching elements. In the following explanation, the deviation of the operating frequency of the DC/DC converter from the resonant frequency of the series resonant circuit will also be referred to as "off-resonance."

Technologies for dealing with fluctuations in the resonant frequency of a series resonant circuit are described in Patent Documents 1 and 2. For example, Patent Document 1 provides a current detection circuit that detects the value of the current flowing through a switching element, and if the value detected by the current detection circuit is greater than zero at the timing when a control signal to turn on the switching element is output, it is determined that the resonant frequency has fluctuated and an abnormality has occurred. Furthermore, Patent Document 2 detects current values at two or more points within the same resonant cycle that are symmetrical with respect to a half-cycle of the resonant cycle as the midpoint, and if the current values differ by more than a predetermined value, it is determined that the resonant frequency has fluctuated and an abnormality has occurred.

The technologies described in Patent Documents 1 and 2 detect the occurrence of an abnormality, and when an abnormality is detected, it is possible to avoid off-resonance by, for example, forcibly turning off a switching element and increasing the operating frequency of the DC/DC converter.

However, in this case, the switching element must be forcibly turned off continuously during the period when resonance is lost, i.e., the period when the voltage of the DC power supply Vi and the output-side load 4 remain high, and during this period the DC/DC converter cannot perform proper power conversion.

If a configuration that forcibly turns off switching elements is not adopted to avoid out-of-resonance, increased power loss occurs. In other words, when out-of-resonance occurs in a DC/DC converter, the current flowing through one of the on switching elements (e.g., Q1) reverses from positive to negative. After this reversal, the switching element (Q1) turns off, causing the switching element (Q1) to enter a reverse conduction state. When the other switching element (Q2) is turned on after the dead time has elapsed, a recovery current flows through switching elements Q1 and Q2, resulting in large power loss and potentially damaging the switching elements.

By using a switching element with a small recovery current during reverse conduction, it is possible to suppress increases in power loss when resonance is lost and prevent breakdown of the switching element. Examples of switching elements with a small recovery current during reverse conduction include fast-recovery metal-oxide-semiconductor field-effect transistors (MOSFETs) and high-electron mobility transistors (HEMTs) made from gallium nitride (GaN)-based materials. Hereinafter, HEMTs made from GaN-based materials will be referred to as GaN-HEMTs.

In particular, GaN-HEMTs do not include a body diode inside the device, so in principle the recovery current is zero. Therefore, in a DC/DC converter that uses a GaN-HEMT as a switching element, even if resonance goes out, no loss due to recovery current occurs, and the risk of breakdown of the switching element can be reduced, making it possible to operate the DC/DC converter even when the voltage value of the DC power supply Vi or the load on the output side is high.

Using a GaN-HEMT as a switching element can eliminate the aforementioned effects of the body diode, but GaN-HEMTs, like MOSFETs, have output capacitance, so there is an effect from the GaN-HEMT's output capacitance. In other words, when an out-of-resonance condition occurs and one of the switching elements (e.g., Q1) enters a reverse conduction state, the output capacitance of the switching element (Q1) is discharged, and when the other switching element (Q2) is turned on, the output capacitance of the switching element (Q1) is recharged. At this time, a current flows through the switching elements (Q2) and (Q1) to recharge the output capacitance.

The output capacitance of GaN-HEMTs is small, and the amount of stored charge is small compared to the recovery current, so there is little risk of increased power loss or damage to the switching element. However, because power conversion devices that use GaN-HEMTs as switching elements are often operated at high frequencies, the amount of change in current over time due to the recharging of the output capacitance (dI/dt: I is the current flowing through the output capacitance during recharging) becomes large. This large amount of change in current over time (dI/dr) can cause surge voltages and increased noise, interfering with the normal operation of power conversion equipment.

Patent Documents 1 and 2 neither describe nor acknowledge the surge voltage or increased noise caused by changes over time in the current that recharges the output capacitance of the switching element when resonance is lost.

In order to solve the above-mentioned problems, the inventors conducted extensive research and came up with the configuration of this embodiment. This embodiment will be described below with reference to the drawings.

(Embodiment 1)
<Overall configuration of power conversion device>
Fig. 1 is a circuit diagram showing the configuration of a power conversion device according to embodiment 1. In Fig. 1, reference numeral 101 denotes the power conversion device. The power conversion device 101 is a DC/DC converter of an LLC resonant type, including a half-bridge circuit 1 using two switching elements.

The power conversion device 101 includes a half-bridge circuit 1, a gate drive circuit 2, a current detection circuit (hereinafter also referred to as the detection circuit) 5, a current polarity reversal determination circuit (hereinafter also referred to as the determination circuit) 6, a resonant capacitor Cr, a transformer Tr composed of a primary winding Tr1 and secondary windings Tr2-1 and Tr2-2, and a rectifier circuit 3 composed of diodes D1 and D2 and a smoothing capacitor Co. In FIG. 1, T1 and T2 indicate input terminals of the power conversion device 101, and T3 and T4 indicate output terminals of the power conversion device 101. As shown in FIG. 1, an external DC power source Vi is connected to the input terminals T1 and T2 of the power conversion device 101, and a load 4 is connected to the output terminals T3 and T4. The DC power source Vi is, for example, a battery, an AC/DC (alternating current/direct current) converter, etc.

As shown in Figure 1, half-bridge circuit 1 is connected between both terminals of DC power supply Vi. Half-bridge circuit 1 includes switching elements Q1 and Q2 connected in series between both terminals of DC power supply Vi (between input terminals T1 and T2). Although not limited to this, switching elements Q1 and Q2 are composed of GaN-HEMTs formed on the silicon substrate of a single semiconductor chip (the same semiconductor chip).

In Figure 1, Cp1 and Cp2, indicated by dashed lines, represent the parasitic capacitors of switching elements Q1 and Q2. One terminal of parasitic capacitor Cp1 is connected to the source terminal of switching element Q1, and the other terminal is connected to the drain terminal of switching element Q1. This parasitic capacitor Cp1 corresponds to the output capacitance of switching element Q1. Similarly, parasitic capacitor Cp2 is connected between the source terminal and drain terminal of switching element Q2, and corresponds to the output capacitance of switching element Q2. Hereinafter, parasitic capacitors Cp1 and Cp2 are also referred to as output capacitances Cp1 and Cp2.

In the half-bridge circuit 1, the drain terminal of switching element Q1 is connected to a DC power supply Vi via input terminal T1. The source terminal of switching element Q1 is connected to the drain terminal of switching element Q2. The source terminal of switching element Q2 is connected to the DC power supply Vi via input terminal T2. The gate terminals of switching elements Q1 and Q2 are connected to gate drive circuit 2. A detection circuit 5, a resonant capacitor Cr, and the primary winding Tr1 of a transformer Tr are connected in series between the node connecting the source terminal of switching element Q1 and the drain terminal of switching element Q2 and the source terminal of switching element Q2. The secondary side of the transformer Tr is composed of secondary windings Tr2-1 and Tr2-2. Although not particularly limited, the secondary windings Tr2-1 and Tr2-2 have the same number of turns and are connected in series so that they are wound in the same direction. Note that the ● mark in Figure 1 indicates the polarity of the transformer Tr.

The rectifier circuit 3 is composed of diodes D1 and D2 and a smoothing capacitor Co, with the cathode terminals of diodes D1 and D2 connected to one terminal of the smoothing capacitor Co. The other terminal of the smoothing capacitor Co is connected to the node where one terminal of the secondary windings Tr2-1 and Tr2-2 of the transformer Tr is connected to each other. The other terminals of the secondary windings Tr1 and Tr2-2 of the transformer Tr are connected to the anode terminals of diodes D1 and D2, respectively. The terminals of the smoothing capacitor Co are connected to the load 4 via output terminals T3 and T4.

The detection circuit 5 is composed of a current sensor. The current sensor is composed of, for example, a shunt resistor, a Hall element, or a Rogowski coil. The detection circuit 5 detects the current value of the current I1 flowing through the resonant switching circuit RSC (hereinafter simply referred to as the switching circuit) which includes switching elements Q1 and Q2, a resonant capacitor Cr, and a primary winding Tr1 of a transformer Tr. The current value detected by the detection circuit 5 is output as an analog value to the determination circuit 6. In embodiment 1, the detection circuit 5 is also provided in the resonant switching circuit RSC to detect the current value of the current I1.

The judgment circuit 6 is not particularly limited, but is composed of a comparator and an edge detector (not shown). The comparator is composed of, for example, a comparator, and the edge detector is composed of, for example, an edge detection circuit formed by combining logic circuits or an edge detector using a microprocessor. The comparator receives the input (analog current value) from the detection circuit 5 and a reference value corresponding to a current value of "0 (zero)." The comparator compares the analog current value with the reference value and outputs the comparison result as a digital value to the edge detector. The edge detector detects changes in the input digital value as rising and falling edges of a signal, and outputs this to the gate drive circuit 2 as a judgment signal indicating the polarity (current polarity) of the current I1 of the resonant switching circuit flowing through the detection circuit 5.

For example, if the analog current value from detection circuit 5 drops from a high current value to below the reference value, the comparator in judgment circuit 6 changes the digital value from "1" to "0." The edge detector in judgment circuit 6 recognizes the change from digital value "1" to "0" as a falling edge of the signal and outputs a judgment signal indicating that the polarity of current I1 in resonant switching circuit RSC has reversed from positive to negative. In contrast, if the analog current value from detection circuit 5 rises from a value lower than the reference value to exceed the reference value, the comparator in judgment circuit 6 changes the digital value from "0" to "1." The edge detector in judgment circuit 6 recognizes the change from digital value "0" to "1" as a rising edge of the signal and outputs a judgment signal indicating that the polarity of current I1 in resonant switching circuit RSC has reversed from negative to positive.

A Schmitt trigger or low-pass filter may be provided on the input side of the comparator in the judgment circuit 6. This Schmitt trigger or low-pass filter can remove noise contained in the output from the detection circuit 5.

The gate drive circuit 2 drives the switching elements Q1 and Q2 to alternately turn on and off in an operating cycle determined by the operating frequency of the power conversion device 101. When driving the switching elements Q1 and Q2, the gate drive circuit 2 adjusts the drive capacity based on a determination signal from the determination circuit 6. The gate drive circuit 2 will be described in detail below with reference to the drawings.

<<Configuration of the gate drive circuit>>
Fig. 2 is a block diagram showing the configuration of the gate drive circuit according to embodiment 1. As shown in Fig. 2, the gate drive circuit 2 includes a control circuit 21 and two gate output circuits 22 corresponding to the switching elements Q1 and Q2.

Control circuit 21 is composed of, for example, a microprocessor or a programmable gate array (e.g., a so-called FPGA), and generates the gate signals required to alternately turn on and off switching elements Q1 and Q2 at the operating frequency of power conversion device 101. Control circuit 21 also receives the determination signals (current inversion positive/negative and current inversion negative/positive) output from determination circuit 6 via input terminals T21 and T22, and generates output switching signals for switching the gate drive currents of switching elements Q1 and Q2. Because the gate drive currents of switching elements Q1 and Q2 are adjusted by switching the gate drive currents, control circuit 21, which generates the output switching signals, can be considered a gate adjustment circuit.

A gate output circuit 22 is provided for each switching element Q1 and Q2, and outputs a gate output signal corresponding to the gate signal and output switching signal input from the control circuit 21. The gate output signal output from the gate output circuit 22 is supplied to the gate terminals of the switching elements Q1 and Q2 via output terminals T23 and T24. In FIG. 2, reference numeral 22-1 denotes the gate output circuit that supplies gate output signal 1 to the gate terminal of switching element Q1, and reference numeral 22-2 denotes the gate output circuit that supplies gate output signal 2 to the gate terminal of switching element Q2.

<<<Gate output circuit configuration>>>
Next, the configuration of the gate output circuit will be described with reference to the drawings. The gate output circuit 22-1 corresponding to the switching element Q1 and the gate output circuit 22-2 corresponding to the switching element Q2 have similar configurations, and therefore will be described below as the gate output circuit 22.

Figure 3 is a circuit diagram showing the configuration of a gate output circuit according to embodiment 1.

The gate output circuit 22 includes P-channel field-effect (PMOS) transistors PTr1 and PTr2, N-channel field-effect (NMOS) transistor NTr, resistors Rgon1, Rgon2, and Rgoff, inverter gates inv1 and inv2, and OR gates or1 and or2. The electrical resistance of resistor Rgon2 is set to be greater than that of resistor Rgon1.

The source terminals of PMOS transistors PTr1 and PTr2 are connected to a voltage line Vgon. The voltage (Vg, on) applied to the voltage line Vgon is a predetermined voltage applied to the gate terminals of switching elements Q1 and Q2 to turn them on. The source terminal of NMOS transistor NTr is connected to a voltage line Vgoff. The voltage (Vg, off) applied to the voltage line Vgoff is a voltage applied to the gate terminals of switching elements Q1 and Q2 to turn them off. The voltages (Vg, on) and (Vg, off) are generated by the DC power supply Vi shown in Figure 1, although there is no particular limitation.

The drain terminals of PMOS transistors PTr1 and PTr2 are connected to one terminal of resistor elements Rgon1 and Rgon2, respectively, and the other terminals of resistor elements Rgon1 and Rgon2 are connected to output terminal T223. The drain terminal of NMOS transistor NTr is connected to one terminal of resistor element Rgoff, and the other terminal of resistor element Rgoff is connected to output terminal T223.

The gate signal output from the control circuit 21 is supplied to the input of inverter gate inv2 via input terminal T222. The output of inverter gate inv2 is connected to one input of OR gates or1 and or2, and also to the gate terminal of NMOS transistor NTr. The output switching signal output from the control circuit 21 is connected to the other input of OR gate or1 via input terminal T221, and also to the other input of OR gate or2 via inverter gate inv1. The outputs of OR gates or1 and or2 are connected to the gate terminals of PMOS transistors PTr1 and PTr2, respectively.

Therefore, while the gate signal is low level ("0"), PMOS transistors PTr1 and PTr2 are turned off. Meanwhile, during this period, NMOS transistor NTr is turned on. In this case, resistive element Rgoff is connected between voltage line Vgoff and the gate terminal of switching element Q1 or Q2 via NMOS transistor NTr and output terminal T223. In other words, resistive element Rgoff corresponds to the gate resistance of the switching element, and the voltage (Vg,off) across the gate resistance (resistive element Rgoff) is applied to switching element Q1 or Q2 as a gate-off voltage, turning switching element Q1 or Q2 off.

On the other hand, when the gate signal is high level ("1"), the NMOS transistor NTr is off. During this period, when the output switching signal is low level ("0"), the PMOS transistor PTr1 is on, and when the output switching signal is high level ("1"), the PMOS transistor PTr2 is on. Therefore, when the gate signal is high level and the output switching signal is low level, the resistive element Rgon1 corresponds to the gate resistance of the switching element, and a voltage (Vg,on) is applied to the switching element Q1 or Q2 via the gate resistance (resistive element Rgon1) as a gate-on voltage, turning the switching element Q1 or Q2 on. At this time, in the on-state switching element Q1 or Q2, a drain current corresponding to the current of the gate output signal (high-level gate drive current) supplied to the gate terminal of the switching element Q1 or Q2 flows via the gate resistance (resistive element Rgon1).

Furthermore, when the output switching signal is high level ("1") while the gate signal is high level ("1"), resistive element Rgon2 corresponds to the gate resistance of the switching element, and the voltage (Vg, on) via the gate resistance (resistive element Rgon2) is applied to switching element Q1 or Q2 as the gate-on voltage. In this case, switching element Q1 or Q2 is also turned on. However, at this time, the current of the gate output signal (gate drive current) supplied to the gate terminal of switching element Q1 or Q2 is the gate output signal current (low-level gate drive current) determined by resistive element Rgon2, because resistive element Rgon2 functions as a gate resistor. Therefore, at this time, a drain current corresponding to the gate drive current determined by resistive element Rgon2 flows in switching element Q1 or Q2 that is turned on.

In the gate output circuit 22 according to the first embodiment, the gate resistance of the switching elements Q1 and Q2 that are turned on can be switched by an output switching signal. By switching the gate resistance, a gate drive current determined by the switched gate resistance is supplied to the gate terminals of the switching elements Q1 and Q2, and a drain current corresponding to the gate drive current flows through the switching elements that are turned on. That is, a gate drive current of a level corresponding to the resistance element Rgon1 or Rgon2, which corresponds to the gate resistance, is supplied to the gate terminals of the switching elements, and a drain current corresponding to the gate drive current is output from the switching elements. As described above, since the electrical resistance of resistance element Rgon2 is greater than the electrical resistance of resistance element Rgon1, when the output switching signal is high, the gate output circuit 22 outputs a low-level gate drive current to the gate terminals of the switching elements Q1 and Q2, thereby switching the drain current of the switching elements Q1 and Q2 to a low level.

When the gate signal is at a high level, the inverter gate inv1, OR gates or1 and or2, and PMOS transistors PTr1 and PTr2 can be considered to form a switching circuit that selects a resistor element from resistor elements Rgon1 and Rgon2 according to the output signal. In this case, the selected resistor element is connected between a predetermined voltage (Vg, on) and the gate terminal of the switching element.

<Operation of the power conversion device>
First, a control method executed in the power conversion device according to the first embodiment will be described with reference to the drawings. Fig. 4 is a flowchart for explaining the control method according to the first embodiment.

In step S1, the control circuit 21 shown in FIG. 2 outputs gate output signal 1 and gate output signal 2, turning on and off the switching elements Q1 and Q2 shown in FIG. 1. Next, steps S2, S3, and S4 are executed sequentially, and steps S2 to S4 are performed while switching element Q1 or Q2 is in the on state.

Step S2 is a current detection process in which the detection circuit 5 in Figure 1 detects the current I1 flowing through the resonant switching circuit RSC.

In step S3, the determination circuit 6 determines the polarity of the current I1 based on the current I1 detected in step S2, and supplies the determination result to the control circuit 21 as a determination signal. In other words, step S3 is the polarity determination process.

If it is determined in step S3 that the polarity is reversed (Y), the control circuit 21 generates an output switching signal and switches the gate drive current of the switching element. This switching of the gate drive current adjusts the gate drive current, so step S4 is a drive current adjustment process.

If it is determined in step S3 that the polarity has not been reversed (N) and step S4 is completed, step S1 is executed again. In other words, steps S1 to S3 are repeated.

In the power conversion device according to embodiment 1, if it is determined in step S3 that the polarity is reversed, processing is performed assuming that an off-resonance condition has occurred. In contrast, if it is determined in step S3 that the polarity is not reversed, processing is performed assuming that an off-resonance condition has not occurred.

Although not particularly limited, step S4 (adjustment step) according to embodiment 1 includes two steps. That is, step S4 includes a step of adjusting (switching) the gate drive current to a low level when it is determined that the polarity has reversed. It also includes a step of adjusting (switching) the gate drive current to a level higher than the low level after a predetermined period (output switching period) has elapsed since the gate drive current was switched to the low level.

Next, we will explain what happens when resonance is not occurring and what happens when resonance is occurring.

<<When off-resonance occurs>>
First, a case will be described in which the load on the power conversion device 101 is not high and no off-resonance occurs. Fig. 5 is a waveform diagram for explaining the operation of the power conversion device according to embodiment 1. The following description will be given with reference to Figs. 1 to 3 and 5.

Figure 5 shows the waveforms of gate output signal 1 and gate output signal 2 output by gate drive circuit 2 to control half-bridge circuit 1, and the waveform of current I1 flowing through resonant switching circuit RSC, including primary winding Tr1 of transformer Tr, detected by detection circuit 5. Figure 5 also shows the waveforms of voltages Vds1 and Vds2 applied between the drain and source terminals of switching elements Q1 and Q2, and the waveforms of currents Id1 and Id2 flowing from the drain terminals to the source terminals of switching elements Q1 and Q2 (drain currents). Note that voltage Vds1 and current Id1 are the voltage and current of switching element Q1, and voltage Vds2 and current Id2 are the voltage and current of switching element Q2.

Detection circuit 5 detects current with positive (+) polarity flowing from left to right, as indicated by the arrow in Figure 1. Gate output signal 1 output from gate drive circuit 2 controls the on/off state of switching element Q1, and gate output signal 2 controls the on/off state of switching element Q2. Control circuit 21, which constitutes gate drive circuit 2, generates gate signals to complementarily drive switching elements Q1 and Q2, including dead times td1 and td2. Dead times td1 and td2 are periods during which both switching elements Q1 and Q2 are in the off state.

First, at time t1, when the gate output signal turns on switching element Q1 while switching element Q2 is off, a positive (+) current I1 flows through the resonant switching circuit RSC, which includes the DC power supply Vi, switching element Q1, detection circuit 5, resonant capacitor Cr, and primary winding Tr1 of the transformer Tr.

At time t2, when switching element Q1 is turned off and dead time td1 begins, switching element Q2 enters reverse conduction and the current flowing through the primary winding Tr1 of the transformer Tr is commutated to switching element Q2. Switching element Q2 is then turned on in a reverse conduction state, performing so-called zero-voltage switching, in which switching is performed while the voltage applied between the source and drain terminals of switching element Q2 is almost zero. Then, due to LC resonance caused by the inductance included in the transformer Tr and the capacitance of the resonant capacitor Cr, the polarity of current I1 flowing through the resonant switching circuit RSC, which includes the primary winding Tr1 of the transformer Tr, reverses from positive (+) to negative (-).

Next, at time t3, when switching element Q2 is turned off and dead time td2 begins, switching element Q1 becomes reverse conductive and the current flowing in the primary winding Tr1 of the transformer Tr is commutated to switching element Q1. Then, by turning switching element Q1 on in the reverse conductive state, zero voltage switching is performed, and then, due to LC resonance, current I1 flowing in the resonant switching circuit RSC, which includes the primary winding Tr1 of the transformer Tr, reverses from negative (-) to positive (+).

The gate output signal described above is generated periodically at a cycle determined by the operating frequency of the power conversion device 101, so the operation from time t1 to time t3 described above is repeated. In response to changes in the current I1 flowing through the primary winding Tr1 of the transformer Tr, a current is generated in the secondary winding Tr2-1 or Tr2-2, which is converted to direct current by the rectifier circuit 3 and supplied to the load 4.

<<When resonance is off>>
Fig. 6 is a waveform diagram for explaining the operation of the power conversion device according to embodiment 1. Fig. 6 is similar to Fig. 5, and like Fig. 5, Fig. 6 also shows gate output signal 1 and gate output signal 2, current I1 flowing through resonant switching circuit RSC, voltages Vds1 and Vds2 between the drain and source terminals of switching elements Q1 and Q2, and drain currents Id1 and Id2 of switching elements Q1 and Q2. Fig. 6 differs from Fig. 5 in that Fig. 6 illustrates a case where load 4 suddenly changes to a high load during the period in which power conversion device 101 is operating, causing off-resonance.

Under heavy load conditions, during the period (times t1 to t2) when switching element Q1 is in the on state, at a certain time (for example, time t12), due to LC resonance caused by the inductance included in transformer Tr and the capacitance of resonant capacitor Cr, the polarity of the current flowing through resonant switching circuit RSC, which includes primary winding Tr1 of transformer Tr, reverses from positive to negative, as shown in Figure 6, causing switching element Q1 to enter a reverse conduction state. After that, when switching element Q1 is turned off and dead time td1 begins, switching element Q2 is off and no current flows, but switching element Q1 continues to conduct current, remaining in a reverse conduction state. At this time, output capacitance Cp1 (Figure 1) of switching element Q1 enters a discharged state.

At a later time t2, when switching element Q2 is changed (transitioned) to the on state, the current flowing through switching element Q1 is commutated to switching element Q2, at which time the output capacitance Cp1 of switching element Q1 is recharged. Because output capacitance Cp1 is a capacitor connected between the source and drain terminals of switching element Q1, during the recharge period in which output capacitance Cp1 is being recharged, current (current to recharge output capacitance Cp1) flows between the drain and source terminals of switching element Q1. At this time, switching element Q2 transitions to the on state, causing a through current to flow through switching elements Q1 and Q2.

Since this through-current flows through switching elements Q1 and Q2, the change in the through-current value over time is determined by the speed at which switching element Q2 transitions to the on state.

Next, the operation of turning switching element Q2 off and then turning switching element Q1 on after the dead time td2 has elapsed is complementary to the above. That is, at time t23 before switching element Q2 transitions to the off state, the polarity of current I1 flowing through the resonant switching circuit RSC, including the primary winding Tr1 of the transformer Tr, reverses from negative to positive due to the LC resonance described above. In this case, switching element Q2 enters a reverse conduction state, discharging the output capacitance Cp2 of switching element Q2. When switching element Q1 transitions to the on state, output capacitance Cp2 is recharged. Therefore, when switching element Q1 transitions to the on state, a through current flows through switching elements Q1 and Q2. The change in the value of this through current over time is also determined by the speed at which switching element Q1 transitions to the on state.

In embodiment 1, the control circuit 21 constituting the gate drive circuit 2 executes steps S2 to S4 shown in FIG. 4 during the ON period of the switching element Q1. That is, when the control circuit 21 receives a determination signal from the determination circuit 6 indicating a polarity reversal of the current I1 (in this case, a reversal from positive to negative), the control circuit 21 outputs an output switching signal to the gate output circuit 22-2 connected to the switching element Q2 to transition to the ON state. When the output switching signal is input, the gate output circuit 22-2 switches the gate resistance used when driving the switching element Q2 to the ON state from resistor Rgon1 to resistor Rgon2, increasing the gate resistance value. As a result, the gate drive current for the switching element Q2 decreases, the drain current of the switching element Q2 also decreases, and the drive current of the switching element Q2 is adjusted to decrease.

This adjustment reduces the drain current, thereby slowing down the speed at which switching element Q2 transitions to the ON state. Therefore, even if load 4 becomes heavily loaded while switching element Q1 is in the ON state, the amount of time change in the through current that occurs when switching element Q2 transitions to the ON state is reduced, making it possible to suppress the generation of surge voltages and noise.

The control circuit 21 also executes steps S2 to S4 shown in FIG. 4 while switching element Q2 is on. That is, when a determination signal indicating a polarity reversal of current I1 (in this case, a reversal from negative to positive) is input to the control circuit 21, it outputs an output switching signal to the gate output circuit 22-1 connected to switching element Q1. When the output switching signal is input, the gate output circuit 22-1 switches the gate resistance used when driving switching element Q1 to the on state from resistor Rgon1 to resistor Rgon2, increasing the gate resistance value. As a result, the gate drive current for switching element Q1 decreases, and the drain current of switching element Q1 also decreases, adjusting the drive current of switching element Q1 to decrease.

By reducing the drain current through this adjustment, the speed at which switching element Q1 transitions to the ON state slows down. Therefore, even if load 4 becomes heavily loaded while switching element Q2 is in the ON state, the amount of change over time in the through current that occurs when switching element Q1 transitions to the ON state is reduced, making it possible to suppress the generation of surge voltages and noise.

In FIG. 6, the drain current change Id_1 indicated by the dashed line represents the change in drain current when resistor Rgon1 is used as the gate resistor without switching resistor elements, and the drain current change Id_2 indicated by the solid line represents the change in drain current when the gate resistor is switched to resistor Rgon2 in accordance with embodiment 1. Furthermore, the voltage change Vsg_1 indicated by the dashed line represents the change in voltages Vds1 and Vds2 when resistor Rgon1 is used as the gate resistor without switching resistor elements, and the voltage change Vsg_2 indicated by the solid line represents the change in voltages Vds1 and Vds2 when the gate resistor is switched to resistor Rgon2 in accordance with embodiment 1. These voltage changes Vsg_1 and Vsg_2 become surge voltages and noise.

According to embodiment 1, the time during which the drain current change occurs is longer, but the peak value can be reduced. As a result, as shown in FIG. 6, the voltage change Vsg_2 is smaller than the voltage change Vsg_1, making it possible to suppress the surge voltage and noise that occur.

In the control circuit 21 according to the first embodiment, a period (output switching period) during which an output switching signal is output to the gate output circuit 22 (22-1, 22-2) is preset. During this set output switching period, the gate output circuit 22 uses the resistive element Rgon as a gate resistor and outputs a low gate drive current. In the first embodiment, the output switching period is set to be longer than the time from when the polarity reversal of the current I1 is determined to when the switching elements Q1 and Q2 are turned on and off, and shorter than half the cycle (half period) during which the switching elements Q1 and Q2 are turned on and off.

Using Figure 6 as an example, the output switching period is set to be longer than the time from time t12 to time t2, but shorter than the time from time t1 to time t2. By setting the output switching period, during the period in which a high load on load 4 is detected as a polarity reversal of current I1, the gate drive current output from the output circuit is suppressed to a low value (low level) when the switching element is transitioned to the on state. Next, when the switching element is turned on or off, resistor element Rgon1 is used as the gate resistor, raising the gate drive current to a high level and enabling high-speed switching.

<<Switching element structure>>
In the first embodiment, as described above, GaN-HEMTs are used as the switching elements Q1 and Q2. An example of a GaN-HEMT will now be described. Fig. 7 is a cross-sectional view showing the structure of a GaN-HEMT used in the power conversion device according to the first embodiment.

In Figure 7, 500 denotes a GaN-HEMT. The GaN-HEMT comprises a substrate 501, a buffer layer 502 formed on the substrate 501, a gallium nitride (GaN) layer 503 formed on the buffer layer 502, an aluminum gallium nitride (AlGaN) layer 504 formed on the gallium nitride layer 503, a gate electrode 507 formed at a predetermined position on the aluminum gallium nitride layer 504 via a p-type gallium nitride (p-GaN) layer 505, and a source electrode 506 and a drain electrode 508 formed on the aluminum gallium nitride layer 504 at positions separated from the gate electrode 507.

The gate electrode 507 corresponds to the gate terminal of the switching elements Q1 and Q2, and the source electrode 506 and drain electrode 508 correspond to the source terminal and drain terminal of the switching elements Q1 and Q2. The output capacitance (Cp1) of a switching element (e.g., Q1) is a parasitic capacitor with the source electrode 506 as one terminal and the drain electrode 508 as the other terminal. In other words, the output capacitance (Cp1) is connected between the source terminal and drain terminal of the switching element (Q1).

As shown in Figure 7, a GaN-HEMT does not form a body diode, making it possible to prevent losses due to the recovery current flowing through the body diode. Therefore, according to embodiment 1, even if the load 4 becomes high and off-resonance occurs, losses due to the recovery current do not occur, reducing the possibility of the element (GaN-HEMT) being destroyed.

According to embodiment 1, even if the load 4 is in a high load state and resonance is lost, the time change dI/dt of the current flowing through the switching elements Q1 and Q2 that make up the half-bridge circuit 1 can be suppressed, thereby suppressing increases in surge voltage and noise. This enables stable operation of the power conversion device 101.

In embodiment 1, a configuration using a field-effect transistor as the gate output circuit 22 as shown in Figure 3 was described, but GaN-HEMTs may also be used instead of field-effect transistors, as with the switching elements.

Furthermore, the GaN-HEMTs that make up the switching elements Q1 and Q2 and the detection circuit 5 may be formed on the semiconductor substrate of the same semiconductor chip.

(Embodiment 2)
In the second embodiment, the gate output circuit 22 shown in Fig. 2 is modified. Fig. 8 is a circuit diagram showing the configuration of the gate output circuit according to the second embodiment. The power conversion device according to the second embodiment differs from the power conversion device according to the first embodiment in that the configuration of the gate output circuit is changed from that shown in Fig. 3 to that shown in Fig. 8. Therefore, hereinafter, only the gate output circuit will be described unless otherwise necessary for the explanation.

The gate output circuit of embodiment 2 differs from embodiment 1 in that it uses a current mirror circuit to switch the gate drive current.

In Figure 8, 22a denotes the gate output circuit. The gate output circuit 22a includes a PMOS transistor PTr1, a current mirror circuit CM composed of PMOS transistors PTr-CM1 and PTr-CM2, a voltage generation circuit Vref that outputs a voltage value according to the input, an operational amplifier OPref, NMOS transistors NTr and NTr-ref, resistor elements Rref and Rgoff, and an inverter gate inv.

The source terminals of PMOS transistors PTr-CM1 and PTr-CM2, which make up current mirror circuit CM, are connected to voltage line Vgon. The voltage applied to voltage line Vgon is the voltage applied to the gate terminals of switching elements Q1 and Q2 (Figure 1) to turn them on. The gate terminals of PMOS transistors PTr-CM1 and PTr-CM2 are connected to each other and to the drain terminal of PMOS transistor PTr-CM1. The drain terminal of PMOS transistor PTr-CM1 is connected to the drain terminal of PMOS transistor NTr-ref. The drain terminal of PMOS transistor PTr-CM2 is connected to output terminal T223.

The source terminal of PMOS transistor PTr1 is connected to voltage line Vgon, and its drain terminal is connected to the drain terminal of NMOS transistor NTr-ref. The source terminal of NMOS transistor NTr is connected to voltage line Vgoff. The voltage applied to voltage line Vgoff is the voltage applied to the gate terminals of switching elements Q1 and Q2 to turn them off. The drain terminal of NMOS transistor NTr is connected to one terminal of resistor element Rgoff, and the other terminal of resistor element Rgoff is connected to output terminal T223.

The output of the voltage generation circuit Vref is connected to the non-inverting input terminal (+) of the operational amplifier OPref. The inverting input terminal (-) of the operational amplifier OPref is connected to the source terminal of the NMOS transistor NTr-ref, and its output terminal is connected to the gate terminal of the NMOS transistor NTr-ref. The source terminal of the NMOS transistor NTr-ref is connected to one terminal of the resistor element Rref, and the other terminal of the resistor element Rref is connected to the voltage line Vgoff. Therefore, the current flowing from the drain terminal to the source terminal of the NMOS transistor NTr-ref is equal to the ratio of the output voltage of the voltage generation circuit Vref to the resistance value of the resistor element Rref (output voltage/Rref). Because the resistance value of the resistor element Rref is fixed, the current flowing from the drain terminal to the source terminal of the NMOS transistor NTr-ref is proportional to the output voltage of the voltage generation circuit Vref.

The gate signal output from the control circuit 21 (Figure 2) is supplied to the gate terminal of PMOS transistor PTr1 via input terminal T222, and also to the input of inverter gate inv. The output of inverter gate inv is connected to the gate terminal of NMOS transistor NTr. The output switching signal output from the control circuit 21 is supplied as an input to the voltage generation circuit Vref via input terminal T221. Because the output switching signal is supplied as an input, the voltage generation circuit Vref operates to output a lower voltage when the output switching signal is high level ("1") compared to when the output switching signal is low level ("0").

When the gate signal output from the control circuit 21 (Figure 2) is low level ("0"), PMOS transistor PTr1 is on, and the voltage between the drain and source terminals of PMOS transistor PTr-CM1 is almost zero. Because the drain and gate terminals of PMOS transistor PTr-CM1 are connected, PMOS transistor PTr-CM1 is off, and no current flows between the source and drain terminals of PMOS transistor PTr-CM2, which constitutes the current mirror circuit CM. At this time, the output of inverter gate inv is high level ("1"), and NMOS transistor NTr is on. Therefore, resistor Rgoff functions as a gate resistor, and a gate-off voltage is output to switching element Q1 or Q2, turning it off.

On the other hand, when the gate signal output from the control circuit 21 is high level ("1"), the output of the inverter gate inv is low level ("0"), turning off the NMOS transistor NTr. At this time, the high-level gate signal turns off the PMOS transistor PTr, causing the current mirror circuit CM to operate, and a current proportional to the current flowing from the source terminal to the drain terminal of the PMOS transistor PTr-CM1 flows from the source terminal to the drain terminal of the PMOS transistor PTr-CM2. Because the PMOS transistor PTr-CM1 and the NMOS transistor NTr-ref are connected in series, the current flowing from the source terminal to the drain terminal of the PMOS transistor PTr-CM1 is equal to the current flowing from the drain terminal to the source terminal of the NMOS transistor NTr-ref. Therefore, a current proportional to the output voltage of the voltage generation circuit Vref is output to the gate terminal of the switching element Q1 or Q2 via the output terminal T223. When the output switching signal is high level ("1"), the output voltage of the voltage generation circuit Vref is lower than when the output switching signal is low level ("0"), and therefore the output of the gate drive current output from the gate drive circuit 2 (Figure 2) equipped with the gate output circuit 22a according to embodiment 2 is switched to a low level.

In Figure 8, the voltage generation circuit Vref, operational amplifier OPref, NMOS transistor NTr-ref, and resistor element Rref can be considered to constitute a current circuit that outputs a current according to the level of the output switching signal supplied to input terminal T221. In this case, a current proportional to the current output from the current circuit is output from current mirror circuit CM to the gate terminal of switching element Q1 or Q2 as gate drive current.

According to embodiment 2, the level of the gate drive current output from gate output circuit 22a can be switched in response to an output switching signal. As with embodiment 1, when an off-resonance state occurs in the power conversion device, control circuit 21 of gate drive circuit 2 generates an output switching signal in response to the output of determination circuit 6 (Figure 1), thereby suppressing the amount of change in the through current over time and making it possible to suppress the generation of surge voltages and noise. Furthermore, according to embodiment 2, resistance elements corresponding to resistance elements Rgon1 and Rgon2 shown in Figure 3 are no longer necessary, making it possible to reduce power loss in these resistance elements.

Furthermore, when the number of levels of gate drive current output from the gate output circuit is increased beyond two, the gate output circuit 22 shown in FIG. 3 requires an increase in the number of PMOS transistors (corresponding to PTr1 and PTr2 in FIG. 3) that drive the output when the gate is on, resistive elements (corresponding to Rgon1 and Rgon2), and OR gates (corresponding to or1 and or2) that control the gates of the PMOS transistors, depending on the number of gate drive current levels. In contrast, according to the second embodiment, it is only necessary to set the output voltage of the voltage generation circuit Vref to multiple levels (three or more), thereby enabling a simple configuration. Furthermore, the output of the gate drive current can be quickly switched in response to an output switching signal, enabling the power conversion device to operate at a high operating frequency. Note that, even in the second embodiment, the transistors that make up the gate output circuit 22a are not limited to field-effect transistors and may be, for example, GaN-HEMTs.

(Embodiment 3)
Fig. 9 is a circuit diagram showing the configuration of a power conversion device according to embodiment 3. Fig. 9 is similar to Fig. 1, so differences will be mainly described. The main difference is that the power conversion device shown in Fig. 9 uses a full-bridge circuit instead of a half-bridge circuit.

In FIG. 9, reference numeral 101a denotes a power conversion device according to embodiment 3. Power conversion device 101a includes a full-bridge circuit 7 instead of half-bridge circuit 1 (FIG. 1). That is, power conversion device 101a includes full-bridge circuit 7, gate drive circuit 2, detection circuit 5, determination circuit 6, resonance capacitor Cr, transformer Tr configured with primary winding Tr1 and secondary windings Tr2-1 and Tr2-2, and rectifier circuit 3 configured with diodes D1 and D2 and smoothing capacitor Co. An external DC power supply Vi is connected to input terminals T1 and T2, and a load 4 is connected to output terminals T3 and T4. In embodiment 3 as well, DC power supply Vi is a device that supplies DC power, such as a battery or AC/DC converter.

A full-bridge circuit 7 is connected between both terminals of the DC power supply Vi via input terminals T1 and T2. In the full-bridge circuit 7, switching elements Q1 and Q2 are connected in series, and switching elements Q3 and Q4 are connected in series. Switching elements Q1 to Q4 are composed of, for example, GaN-HEMTs formed on the silicon substrate of a semiconductor chip. In the full-bridge circuit 7, the drain terminals of switching elements Q1 and Q3 are connected to the DC power supply Vi via input terminal T1. The source terminal of switching element Q1 is connected to the drain terminal of switching element Q2, and the source terminal of switching element Q3 is connected to the drain terminal of switching element Q4. The source terminals of switching elements Q2 and Q4 are connected to the DC power supply Vi via input terminal T2.

The gate terminals of switching elements Q1 and Q4 are connected to one gate output of gate drive circuit 2, for example, T23 in Figure 2. The gate terminals of switching elements Q2 and Q3 are connected to the other gate output of gate drive circuit 2 (T24 in Figure 2). Furthermore, detection circuit 5, resonant capacitor Cr, and primary winding Tr1 of transformer Tr are connected in series between the node connecting the source terminal of switching element Q1 and the drain terminal of switching element Q2, and the node connecting the source terminal of switching element Q3 and the drain terminal of switching element Q4. Therefore, in full-bridge circuit 7, diagonally positioned switching elements (switching element pair) Q1 and Q4 are simultaneously turned on and off, and similarly, diagonally positioned switching elements (switching element pair) Q2 and Q3 are simultaneously turned on and off.

When switching elements Q1 and Q4 are on, the voltage between the drain and source terminals of switching element Q4 is almost zero, so the operation is equivalent to that of a circuit using half-bridge circuit 1 in embodiment 1, and the same operation as in embodiment 1 is performed. That is, current I1 flows through a resonant switching circuit including DC power supply Vi, switching elements Q1 and Q4, detection circuit 5, resonant capacitor Cr, and primary winding Tr1 of transformer Tr.

On the other hand, unlike in embodiment 1, operation during the period when switching elements Q2 and Q3 are on involves the DC power supply Vi being included in the path of current I2 flowing through the resonant switching circuit including the primary winding Tr1 of the transformer Tr. Therefore, according to embodiment 3 using full bridge circuit 7, current is supplied from DC power supply Vi not only during the period when switching elements Q1 and Q4 are on, but also during the period when switching elements Q2 and Q3 are on. This increases the current that can be output from power conversion device 101a compared to when the same amount of current is passed through switching elements Q1 to Q4 as in embodiment 1. This enables operation suitable for a power conversion device that outputs a large current.

In the third embodiment, as in the first embodiment, when the load 4 becomes high, for example, it is possible to suppress the amount of change over time in the through current flowing between switching elements Q1 and Q4 and between switching elements Q3 and Q2, thereby suppressing the generation of surge voltages and noise.

In addition, in embodiment 3, the gate output circuit may also adopt the configuration described in embodiment 2.

(Fourth embodiment)
Fig. 10 is a circuit diagram showing the configuration of a power conversion device according to embodiment 4. Fig. 10 is similar to Fig. 1, so the differences will be mainly described below. The main differences are that in Fig. 10, two sense elements are added, two sense circuits corresponding to the sense elements are provided as sense circuits, and outputs of the two sense circuits are supplied to a determination circuit.

In Figure 10, 101b indicates a power conversion device according to embodiment 4. The power conversion device 101b includes a half-bridge circuit 1a, a gate drive circuit 2, two detection circuits 5-1 and 5-2, a determination circuit 6a, a resonance capacitor Cr, a transformer Tr formed by a primary winding Tr1 and secondary windings Tr2-1 and Tr2-2, and a rectifier circuit 3 formed by diodes D1 and D2 and a smoothing capacitor Co. An external DC power supply Vi is connected to input terminals T1 and T2, and a load 4 is connected to output terminals T3 and T4.

The half-bridge circuit 1a includes switching elements Q1a and Q2a connected in series. The switching elements Q1a and Q2a are composed of, for example, GaN-HEMTs formed on the silicon substrate of a semiconductor chip. The switching elements Q1a and Q2a include switching elements (main switching elements) Q1a-f and Q2a-f that pass the main current, and switching elements (sensing switching elements) Q1a-s and Q2a-s that split the current flowing through the switching elements Q1a and Q2a and pass it.

The drain terminals of switching elements Q1a-f and Q1a-s are connected to each other, and the gate terminals of switching elements Q1a-f and Q1a-s are also connected to each other. Similarly, the drain terminals of switching elements Q2a-f and Q2a-s are connected to each other, and the gate terminals of switching elements Q2a-f and Q2a-s are also connected to each other.

The main switching element and sense switching element used in embodiment 4 are formed on the semiconductor substrate (silicon substrate) of the same semiconductor chip. Figure 11 is a plan view showing a portion of a semiconductor chip according to embodiment 4. Figure 11 shows the portion of switching element Q1a formed on the semiconductor substrate (silicon substrate) of the semiconductor chip.

The switching elements Q1a-f and Q1a-s included in switching element Q1a are integrated on the same substrate. In Figure 11, the symbol Q1a-Td indicates the common drain terminal of switching elements Q1a-f and Q1a-s. The symbol Q1a-Tg indicates the common gate terminal of switching elements Q1a-f and Q1a-s. The symbol Q1a-Ts-f indicates the source terminal of switching element Q1a-f, and the symbol Q1a-Ts-s indicates the source terminal of switching element Q1a-s. The drain and gate terminals of switching elements Q1a-f and Q1a-s are connected to each other, connecting switching elements Q1a-f and Q1a-s in parallel and operating them in parallel. This diverts a portion of the current flowing through switching element Q1a to switching element Q1a-s, allowing switching element Q1a-s to be used as a sense element.

As shown in Figure 11, the device area of switching element Q1a-s is smaller than the device area of switching element Q1a-f. While only switching element Q1a is shown in Figure 11, switching element Q2a is configured in the same way as switching element Q1a. Furthermore, in embodiment 4, switching elements Q1a and Q2a are formed on the same semiconductor substrate.

Referring back to Figure 10, the source terminals of switching elements Q1a-f are connected to the drain terminal of switching element Q2a. The source terminals of switching elements Q2a-f are connected to DC power supply Vi via input terminal T2. The gate terminals of switching elements Q1a and Q2a are connected to gate drive circuit 2. Resonant capacitor Cr and primary winding Tr1 of transformer Tr are connected in series between the node connecting the source terminals of switching elements Q1a-f and the drain terminal of switching element Q2a and the source terminal of switching element Q2a-f.

Detection circuit 5-1 is connected between the source terminals of switching elements Q1a-f and Q1a-s, and detection circuit 5-2 is connected between the source terminals of switching elements Q2a-f and Q2a-s. Detection circuits 5-1 and 5-2 are current sensors that use, for example, shunt resistors, Hall elements, Rogowski coils, etc. Detection circuits 5-1 and 5-2 detect the current values of the currents flowing through switching elements Q1a-s and Q2a-s, respectively. The current values detected by detection circuits 5-1 and 5-2 are output as analog values to judgment circuit 6a.

The judgment circuit 6a is composed of a comparator, for example, and an edge detector using an edge detection circuit or microprocessor, for example. The comparator compares the input from the current detection circuits 5-1 and 5-2 with the detected value when the current value is zero, and outputs the result as a digital value. The signal output from the comparator is input to the edge detector, which outputs a signal corresponding to the falling edge of the signal from the comparator to the gate drive circuit 2.

Since the switching elements Q1 and Q2 described in embodiment 1 correspond to the switching elements Q1a and Q2a in embodiment 4, the currents output from detection circuits 5-1 and 5-2 correspond to the currents Id1 and Id2 shown in FIGS. 5 and 6. Therefore, the current output from detection circuit 5-1 is used as a determination signal when the polarity of current I1 flowing through primary winding Tr1 of transformer Tr reverses from positive to negative. In other words, when the current output from detection circuit 5-1 reverses from positive to negative, determination circuit 6a outputs a determination signal indicating that the polarity of current I1 has reversed from positive to negative.

On the other hand, the current output from detection circuit 5-2 is used as a determination signal when the polarity of current I1 flowing through primary winding Tr1 of transformer Tr reverses from negative to positive. That is, when the current output from detection circuit 5-2 reverses from positive to negative, determination circuit 6a outputs a determination signal indicating that the polarity of current I1 has reversed from negative to positive. Based on the determination signal from determination circuit 6a, gate drive circuit 2 performs the same operation as in embodiment 1.

In embodiment 4, the currents diverted from the currents flowing through switching elements Q1a and Q2a are detected by detection circuits 5-1 and 5-2, respectively, so the absolute value of the detected currents is smaller than the absolute value of current I1 flowing through primary winding Tr1 of transformer Tr. This makes it possible to reduce the size of detection circuits 5-1 and 5-2.

Furthermore, according to embodiment 4, the detection circuits 5-1 and 5-2 are provided in a location separate from the resonant switching circuit including the primary winding Tr1 of the transformer Tr, which is the path through which a large current flows, thereby making it possible to reduce the parasitic inductance of the resonant switching circuit.

In addition, when using a switching element with an integrated sense element, the current sense ratio generally fluctuates due to factors such as temperature distribution within the element. However, according to embodiment 4, the sense element is only used to determine the reversal of the current polarity (positive/negative), so fluctuations in the current ratio (current sense ratio) detected by the sense element do not affect the operation of the power conversion device, making it possible to use an integrated sense element.

The detection circuit 5-1 shown in FIG. 10 may be formed on the same semiconductor substrate as the switching element Q1a, and the detection circuit 5-2 may also be formed on the same semiconductor substrate as the switching element Q2a.

Note that in embodiment 4, an example based on the power conversion device described in embodiment 1 has been described, but this is not limited to this. In other words, it may also be based on the power conversion devices described in embodiments 2 and 3.

The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention.

1 Half-bridge circuit 2 Gate drive circuit 3 Rectifier circuit 4 Load 5, 5-1, 5-2 Detection circuit 6 Determination circuit 7 Full-bridge circuit 100, 101, 101a, 101b Power conversion devices Cp1, Cp2 Output capacitance Q1, Q2, Q3, Q4, Q1a, Q2a Switching element RSC Switching circuit

Claims (12)

a switching circuit including a transformer having a plurality of switching elements, a capacitor, and a primary winding connected in series with the capacitor;
a gate drive circuit that outputs a gate drive current to the gate of the switching element to control the on/off of the switching element;
a detection circuit for detecting a current flowing through the switching circuit;
a determination circuit for determining whether the polarity of the current detected by the detection circuit is reversed;
Equipped with
the gate drive circuit includes a gate adjustment circuit that adjusts the gate drive current based on the result of the determination by the determination circuit;
the gate adjustment circuit outputs an output switching signal for switching the gate drive current between at least two levels in both of which a current flows;
the gate adjustment circuit outputs the output switching signal for switching the gate drive current output by the gate drive circuit to a low level when the polarity reversal is determined by the determination circuit.
Power conversion device. The power conversion device according to claim 1,
the gate adjustment circuit outputs the output switching signal for switching the gate drive current to a high level after a predetermined period of time has elapsed since the gate drive current was switched to a low level;
Power conversion device. The power conversion device according to claim 2,
the gate drive circuit includes a plurality of gate resistors having different resistance values, and a switch circuit that selects a gate resistor from the plurality of gate resistors in accordance with the output switching signal and connects the selected gate resistor between a predetermined voltage and the gate terminal of the switching element.
Power conversion device. The power conversion device according to claim 2,
The gate drive circuit includes a current circuit whose current value changes in response to the output switching signal, and a current mirror circuit that outputs a current proportional to the current flowing through the current circuit.
Power conversion device. The power conversion device according to any one of claims 1 to 4,
the plurality of switching elements includes two switching elements,
the gate adjustment circuit adjusts the gate drive current of one of the two switching elements to a low level when the other switching element is in an on state;
Power conversion device. The power conversion device according to any one of claims 1 to 4,
the plurality of switching elements include two pairs of switching elements positioned diagonally opposite each other;
the gate adjustment circuit adjusts the gate drive current of one switching element of the pair of switching elements to a low level when the other switching element is in an on state;
Power conversion device. 7. The power conversion device according to claim 1,
At least one of the plurality of switching elements includes a main switching element that supplies current to the capacitor and a primary winding connected in series with the capacitor when in an on state, and a sense element that shunts a part of the current flowing through the one switching element,
the detection circuit detects a current flowing through the sense element;
The main switching element and the sense element are formed on the same semiconductor chip.
Power conversion device. The power conversion device according to claim 7,
the detection circuit is formed on the same semiconductor chip as at least one of the plurality of switching elements;
Power conversion device. The power conversion device according to any one of claims 1 to 8,
At least one switching element among the plurality of switching elements uses a gallium nitride-based material.
Power conversion device. a switching circuit including a transformer having a plurality of switching elements, a capacitor, and a primary winding connected in series with the capacitor;
a gate drive circuit that outputs a gate drive current to a gate terminal of the switching element to control the on/off of the switching element;
A power conversion device comprising:
the gate drive circuit includes a gate adjustment circuit that outputs an output switching signal for switching the gate drive current between at least two levels, both of which are in a state where a current flows;
Detecting a current flowing through the switching circuit;
determining whether the polarity of the detected current has reversed;
When it is determined that the polarity has been reversed, the gate adjustment circuit outputs the output switching signal that switches the gate drive current output by the gate drive circuit to a low level.
A method for controlling a power conversion device. The method for controlling a power conversion device according to claim 10,
the gate adjustment circuit outputs the output switching signal for switching the gate drive current to a high level after a predetermined period of time has elapsed since the gate drive current was switched to a low level;
A method for controlling a power conversion device. The method for controlling a power conversion device according to claim 11,
the predetermined period is longer than the time from when it is determined that the polarity has reversed until the on/off state of the switching element is switched, and is shorter than half the on/off cycle of the switching element.
A method for controlling a power conversion device.