JP7753975B2 - 信号伝送デバイス - Google Patents

信号伝送デバイス

Info

Publication number
JP7753975B2
JP7753975B2 JP2022078433A JP2022078433A JP7753975B2 JP 7753975 B2 JP7753975 B2 JP 7753975B2 JP 2022078433 A JP2022078433 A JP 2022078433A JP 2022078433 A JP2022078433 A JP 2022078433A JP 7753975 B2 JP7753975 B2 JP 7753975B2
Authority
JP
Japan
Prior art keywords
insulating film
upper electrode
signal transmission
transmission device
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022078433A
Other languages
English (en)
Japanese (ja)
Other versions
JP2023167331A (ja
JP2023167331A5 (enExample
Inventor
修治 淺野
公一 八▲高▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2022078433A priority Critical patent/JP7753975B2/ja
Priority to PCT/JP2023/016316 priority patent/WO2023218947A1/ja
Publication of JP2023167331A publication Critical patent/JP2023167331A/ja
Publication of JP2023167331A5 publication Critical patent/JP2023167331A5/ja
Priority to US18/939,129 priority patent/US20250062256A1/en
Application granted granted Critical
Publication of JP7753975B2 publication Critical patent/JP7753975B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0219—Material of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2022078433A 2022-05-11 2022-05-11 信号伝送デバイス Active JP7753975B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2022078433A JP7753975B2 (ja) 2022-05-11 2022-05-11 信号伝送デバイス
PCT/JP2023/016316 WO2023218947A1 (ja) 2022-05-11 2023-04-25 信号伝送デバイス
US18/939,129 US20250062256A1 (en) 2022-05-11 2024-11-06 Signal transmission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2022078433A JP7753975B2 (ja) 2022-05-11 2022-05-11 信号伝送デバイス

Publications (3)

Publication Number Publication Date
JP2023167331A JP2023167331A (ja) 2023-11-24
JP2023167331A5 JP2023167331A5 (enExample) 2024-05-16
JP7753975B2 true JP7753975B2 (ja) 2025-10-15

Family

ID=88730334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022078433A Active JP7753975B2 (ja) 2022-05-11 2022-05-11 信号伝送デバイス

Country Status (3)

Country Link
US (1) US20250062256A1 (enExample)
JP (1) JP7753975B2 (enExample)
WO (1) WO2023218947A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2025012426A (ja) * 2023-07-13 2025-01-24 株式会社デンソー 信号伝送デバイス
JP2025012425A (ja) * 2023-07-13 2025-01-24 株式会社デンソー 信号伝送デバイス

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311299A (ja) 2004-03-26 2005-11-04 Hitachi Ltd 半導体装置及びその製造方法
US20170098604A1 (en) 2015-10-01 2017-04-06 Avago Technologies General Ip (Singapore) Pte. Ltd Isolation device
JP2017130671A (ja) 2017-02-27 2017-07-27 ローム株式会社 チップ部品
JP2020129657A (ja) 2019-01-23 2020-08-27 エックス−ファブ ドレスデン ゲゼルシャフト ミット ベシュレンクテル ハフツング ウント コンパニー コマンディット ゲゼルシャフト 高電圧デバイス
JP2021509540A (ja) 2017-12-29 2021-03-25 日本テキサス・インスツルメンツ合同会社 高電圧絶縁構造及び方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311299A (ja) 2004-03-26 2005-11-04 Hitachi Ltd 半導体装置及びその製造方法
US20170098604A1 (en) 2015-10-01 2017-04-06 Avago Technologies General Ip (Singapore) Pte. Ltd Isolation device
JP2017130671A (ja) 2017-02-27 2017-07-27 ローム株式会社 チップ部品
JP2021509540A (ja) 2017-12-29 2021-03-25 日本テキサス・インスツルメンツ合同会社 高電圧絶縁構造及び方法
JP2020129657A (ja) 2019-01-23 2020-08-27 エックス−ファブ ドレスデン ゲゼルシャフト ミット ベシュレンクテル ハフツング ウント コンパニー コマンディット ゲゼルシャフト 高電圧デバイス

Also Published As

Publication number Publication date
US20250062256A1 (en) 2025-02-20
JP2023167331A (ja) 2023-11-24
WO2023218947A1 (ja) 2023-11-16

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