JP7716052B2 - データバス信号調整器及びレベルシフタ - Google Patents

データバス信号調整器及びレベルシフタ

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Publication number
JP7716052B2
JP7716052B2 JP2022548828A JP2022548828A JP7716052B2 JP 7716052 B2 JP7716052 B2 JP 7716052B2 JP 2022548828 A JP2022548828 A JP 2022548828A JP 2022548828 A JP2022548828 A JP 2022548828A JP 7716052 B2 JP7716052 B2 JP 7716052B2
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JP
Japan
Prior art keywords
circuitry
signal
bus
circuit
data rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP2022548828A
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English (en)
Japanese (ja)
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JP2023515383A (ja
JP2023515383A5 (https=
Inventor
ナイング マウング ウィン
クマール シンガレディ バラス
ポール ソウミ
ガルグ マヤンク
マリー ヴァイニング スザンヌ
Original Assignee
テキサス インスツルメンツ インコーポレイテッド
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Application filed by テキサス インスツルメンツ インコーポレイテッド filed Critical テキサス インスツルメンツ インコーポレイテッド
Publication of JP2023515383A publication Critical patent/JP2023515383A/ja
Publication of JP2023515383A5 publication Critical patent/JP2023515383A5/ja
Application granted granted Critical
Publication of JP7716052B2 publication Critical patent/JP7716052B2/ja
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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • G06F13/4072Drivers or receivers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/02Details
    • H04B3/36Repeater circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0272Arrangements for coupling to multiple lines, e.g. for differential transmission
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033Correction by delay
    • H04L7/0041Delay of data signal
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
JP2022548828A 2020-02-12 2021-02-12 データバス信号調整器及びレベルシフタ Active JP7716052B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202062975227P 2020-02-12 2020-02-12
US62/975,227 2020-02-12
US17/174,119 US11309892B2 (en) 2020-02-12 2021-02-11 Data bus signal conditioner and level shifter
US17/174,119 2021-02-11
PCT/US2021/017776 WO2021163422A1 (en) 2020-02-12 2021-02-12 Data bus signal conditioner and level shifter

Publications (3)

Publication Number Publication Date
JP2023515383A JP2023515383A (ja) 2023-04-13
JP2023515383A5 JP2023515383A5 (https=) 2024-02-16
JP7716052B2 true JP7716052B2 (ja) 2025-07-31

Family

ID=77177992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022548828A Active JP7716052B2 (ja) 2020-02-12 2021-02-12 データバス信号調整器及びレベルシフタ

Country Status (5)

Country Link
US (3) US11309892B2 (https=)
EP (1) EP4104061A4 (https=)
JP (1) JP7716052B2 (https=)
CN (1) CN115039087A (https=)
WO (1) WO2021163422A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11309892B2 (en) * 2020-02-12 2022-04-19 Texas Instruments Incorporated Data bus signal conditioner and level shifter
JP7754485B2 (ja) * 2021-11-12 2025-10-15 Necプラットフォームズ株式会社 信号波形設定装置
CN115498718A (zh) * 2022-08-04 2022-12-20 深圳市海能达通信有限公司 一种通信接口电路及电子装置
US12449878B2 (en) * 2023-09-01 2025-10-21 Parade Technologies, Ltd. Exiting of low power modes of redrivers and retimers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006309794A (ja) 1998-03-09 2006-11-09 Samsung Electronics Co Ltd データトランシーバー及びそれを有するバスインターフェース
JP2014523556A (ja) 2011-05-25 2014-09-11 ザ シラナ グループ プロプライエタリー リミテッド Usb2.0高速モードを有するusbアイソレータ集積回路および自動速度検出
JP2016511568A (ja) 2013-01-24 2016-04-14 日本テキサス・インスツルメンツ株式会社 信号コンディショナー

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170949B2 (en) * 2002-03-14 2007-01-30 Intel Corporation Methods and apparatus for signaling on a differential link
US20140149609A1 (en) * 2012-11-29 2014-05-29 Kok Hong Chan Detecting device disconnect in a repeater
US10237087B2 (en) 2013-09-02 2019-03-19 Samsung Electronics Co., Ltd. Method for controlling transmission speed and electronic device thereof
US9606955B2 (en) 2014-02-10 2017-03-28 Intel Corporation Embedded universal serial bus solutions
US10042807B2 (en) * 2016-04-05 2018-08-07 Infineon Technologies Ag Differential bus receiver with four-quadrant input circuit
US10057090B2 (en) 2016-09-26 2018-08-21 Qualcomm Incorporated Apparatus and method for transmitting data signal based on various transmission modes
US10887075B2 (en) * 2017-03-28 2021-01-05 Intel Corporation Method and system for adaptive link training mechanism to calibrate an embedded universal serial bus redriver clock
US20190280679A1 (en) 2018-03-08 2019-09-12 Microchip Technology Incorporated Rise and Fall Time Mismatch Adjustment Circuit for USB-On-The-Go Modules
US10425124B1 (en) * 2018-03-14 2019-09-24 Pericom Semiconductor Corporation Repeaters with fast transitions from low-power standby to low-frequency signal transmission
JP2019175308A (ja) * 2018-03-29 2019-10-10 セイコーエプソン株式会社 回路装置、電子機器及びケーブルハーネス
US11309892B2 (en) * 2020-02-12 2022-04-19 Texas Instruments Incorporated Data bus signal conditioner and level shifter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006309794A (ja) 1998-03-09 2006-11-09 Samsung Electronics Co Ltd データトランシーバー及びそれを有するバスインターフェース
JP2014523556A (ja) 2011-05-25 2014-09-11 ザ シラナ グループ プロプライエタリー リミテッド Usb2.0高速モードを有するusbアイソレータ集積回路および自動速度検出
JP2016511568A (ja) 2013-01-24 2016-04-14 日本テキサス・インスツルメンツ株式会社 信号コンディショナー

Also Published As

Publication number Publication date
US20240396554A1 (en) 2024-11-28
EP4104061A4 (en) 2023-12-06
WO2021163422A1 (en) 2021-08-19
EP4104061A1 (en) 2022-12-21
JP2023515383A (ja) 2023-04-13
CN115039087A (zh) 2022-09-09
US12088293B2 (en) 2024-09-10
US20210250026A1 (en) 2021-08-12
US11309892B2 (en) 2022-04-19
US20220224335A1 (en) 2022-07-14

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