JP7524175B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7524175B2 JP7524175B2 JP2021524493A JP2021524493A JP7524175B2 JP 7524175 B2 JP7524175 B2 JP 7524175B2 JP 2021524493 A JP2021524493 A JP 2021524493A JP 2021524493 A JP2021524493 A JP 2021524493A JP 7524175 B2 JP7524175 B2 JP 7524175B2
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- transistor
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- memory cell
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- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
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- H—ELECTRICITY
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Description
図2は、半導体装置の構成例を示す図である。
図3は、半導体装置の構成例を示す図である。
図4A、図4Bは、半導体装置の構成例を示す図である。
図5は、半導体装置の構成例を示す図である。
図6は、半導体装置の構成例を示す図である。
図7A、図7Bは、半導体装置の構成例を示す図である。
図8は、半導体装置の構成例を示す図である。
図9A、図9Bは、半導体装置の構成例を示す図である。
図10は、半導体装置の構成例を示す図である。
図11は、半導体装置の構成例を示す図である。
図12は、半導体装置の構成例を示す図である。
図13は、半導体装置の構成例を示す断面模式図である。
図14は、半導体装置の構成例を示す断面模式図である。
図15AはIGZOの結晶構造の分類を説明する図である。図15BはCAAC-IGZO膜のXRDスペクトルを説明する図である。図15CはCAAC-IGZO膜の極微電子線回折パターンを説明する図である。
図16は、半導体装置の構成例を説明するブロック図である。
図17は、半導体装置の構成例を示す概念図である。
図18A、図18Bは、電子部品の一例を説明する模式図である。
図19は、電子機器の例を示す図である。
本発明の一態様である半導体装置の構成例について、図1乃至図11を参照して説明する。
本実施の形態では、上記実施の形態1で説明した半導体装置に適用可能な回路の変形例について、図12を参照して説明する。
以下では、本発明の一態様に係る記憶装置として機能する半導体装置の一例について説明する。
本実施の形態では、上記の実施の形態で説明したOSトランジスタに用いることができる金属酸化物(以下、酸化物半導体ともいう。)について説明する。
まず、酸化物半導体における、結晶構造の分類について、図15Aを用いて説明を行う。図15Aは、酸化物半導体、代表的にはIGZO(Inと、Gaと、Znと、を含む金属酸化物)の結晶構造の分類を説明する図である。
なお、酸化物半導体は、結晶構造に着目した場合、図15Aとは異なる分類となる場合がある。例えば、酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、上述のCAAC-OS、及びnc-OSがある。また、非単結晶酸化物半導体には、多結晶酸化物半導体、擬似非晶質酸化物半導体(a-like OS:amorphous-like oxide semiconductor)、非晶質酸化物半導体、などが含まれる。
CAAC-OSは、複数の結晶領域を有し、当該複数の結晶領域はc軸が特定の方向に配向している酸化物半導体である。なお、特定の方向とは、CAAC-OS膜の厚さ方向、CAAC-OS膜の被形成面の法線方向、またはCAAC-OS膜の表面の法線方向である。また、結晶領域とは、原子配列に周期性を有する領域である。なお、原子配列を格子配列とみなすと、結晶領域とは、格子配列の揃った領域でもある。さらに、CAAC-OSは、a-b面方向において複数の結晶領域が連結する領域を有し、当該領域は歪みを有する場合がある。なお、歪みとは、複数の結晶領域が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。つまり、CAAC-OSは、c軸配向し、a-b面方向には明らかな配向をしていない酸化物半導体である。
nc-OSは、微小な領域(例えば、1nm以上10nm以下の領域、特に1nm以上3nm以下の領域)において原子配列に周期性を有する。別言すると、nc-OSは、微小な結晶を有する。なお、当該微小な結晶の大きさは、例えば、1nm以上10nm以下、特に1nm以上3nm以下であることから、当該微小な結晶をナノ結晶ともいう。また、nc-OSは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、nc-OSは、分析方法によっては、a-like OSや非晶質酸化物半導体と区別が付かない場合がある。例えば、nc-OS膜に対し、XRD装置を用いて構造解析を行うと、θ/2θスキャンを用いたOut-of-plane XRD測定では、結晶性を示すピークが検出されない。また、nc-OS膜に対し、ナノ結晶よりも大きいプローブ径(例えば50nm以上)の電子線を用いる電子線回折(制限視野電子線回折ともいう。)を行うと、ハローパターンのような回折パターンが観測される。一方、nc-OS膜に対し、ナノ結晶の大きさと近いかナノ結晶より小さいプローブ径(例えば1nm以上30nm以下)の電子線を用いる電子線回折(ナノビーム電子線回折ともいう。)を行うと、ダイレクトスポットを中心とするリング状の領域内に複数のスポットが観測される電子線回折パターンが取得される場合がある。
a-like OSは、nc-OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。a-like OSは、鬆又は低密度領域を有する。即ち、a-like OSは、nc-OS及びCAAC-OSと比べて、結晶性が低い。また、a-like OSは、nc-OS及びCAAC-OSと比べて、膜中の水素濃度が高い。
次に、上述のCAC-OSの詳細について、説明を行う。なお、CAC-OSは材料構成に関する。
CAC-OSとは、例えば、金属酸化物を構成する元素が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つまたは複数の金属元素が偏在し、該金属元素を有する領域が、0.5nm以上10nm以下、好ましくは、1nm以上3nm以下、またはその近傍のサイズで混合した状態をモザイク状、またはパッチ状ともいう。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
本実施の形態では、実施の形態1に記載の半導体装置10におけるメモリセル51を含むメモリセルアレイおよび当該メモリセルアレイを駆動するための回路を有する周辺回路20の詳細について説明する。
本実施の形態は、上記実施の形態に示す半導体装置などが組み込まれた電子部品および電子機器の一例を示す。
まず、半導体装置10等が組み込まれた電子部品の例を、図18Aおよび図18Bを用いて説明を行う。
次に、上記電子部品を備えた電子機器の例について図19を用いて説明を行う。
以上の実施の形態、および実施の形態における各構成の説明について、以下に付記する。
Claims (6)
- 第1回路を有するシリコン基板と、
第2回路を有する第1素子層と、
第3回路を有する第2素子層と、を有し、
前記第1回路は、第1トランジスタを有し、
前記第2回路は、第2トランジスタを有し、
前記第3回路は、メモリセルを有し、
前記メモリセルは、第3トランジスタと、キャパシタと、で構成され、
前記第1トランジスタは、チャネル形成領域にシリコンを有し、
前記第2トランジスタ及び前記第3トランジスタは、それぞれチャネル形成領域に金属酸化物を有する半導体層を有し、
前記第1素子層及び前記第2素子層は、前記シリコン基板の表面に対して垂直方向又は概略垂直方向に積層して設けられる積層ブロックを構成し、
前記積層ブロックは、前記シリコン基板の表面に対して垂直方向又は概略垂直方向に積層して複数設けられ、
複数の前記積層ブロックはそれぞれ、前記シリコン基板の表面に対して垂直方向又は概略垂直方向に設けられた第1配線を有し、
前記第1配線は、前記第1素子層及び前記第2素子層を貫通する孔の中に配置され、
複数の前記積層ブロック同士は、当該第1配線が電気的に接続されており、
前記第1回路は、前記第1配線に前記メモリセルの駆動するための信号及び前記メモリセルに書き込むデータを出力する機能、及び前記メモリセルから前記第1配線に読み出されるデータを増幅する機能、を有し、
前記第2回路は、前記メモリセルに電気的に接続された第2配線の電位を増幅して前記第1配線に伝える機能、及び前記第1配線の電位を前記第2配線に伝える機能、を有する、半導体装置。 - 第1回路を有するシリコン基板と、
第2回路を有する第1素子層と、
第3回路を有する第2素子層を複数と、を有し、
前記第1回路は、第1トランジスタを有し、
前記第2回路は、第2トランジスタを有し、
前記第3回路は、メモリセルを有し、
前記メモリセルは、第3トランジスタと、キャパシタと、で構成され、
前記第1トランジスタは、チャネル形成領域にシリコンを有し、
前記第2トランジスタ及び前記第3トランジスタは、それぞれチャネル形成領域に金属酸化物を有する半導体層を有し、
前記第1素子層及び複数の前記第2素子層は、前記シリコン基板の表面に対して垂直方向又は概略垂直方向に積層して設けられる積層ブロックを構成し、
前記積層ブロックは、前記シリコン基板の表面に対して垂直方向又は概略垂直方向に積層して複数設けられ、
複数の前記積層ブロックはそれぞれ、前記シリコン基板の表面に対して垂直方向又は概略垂直方向に設けられた第1配線を有し、
前記第1配線は、前記第1素子層及び複数の前記第2素子層を貫通する孔の中に配置され、
複数の前記積層ブロック同士は、当該第1配線が電気的に接続されており、
前記第1回路は、前記第1配線に前記メモリセルの駆動するための信号及び前記メモリセルに書き込むデータを出力する機能、及び前記メモリセルから前記第1配線に読み出されるデータを増幅する機能、を有し、
前記第2回路は、前記メモリセルに電気的に接続された第2配線の電位を増幅して前記第1配線に伝える機能、及び前記第1配線の電位を前記第2配線に伝える機能、を有する、半導体装置。 - 請求項1又は請求項2において、
前記金属酸化物は、Inと、Gaと、Znと、を含む、半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記第2素子層は、前記第3トランジスタを有する層と、前記キャパシタを有する層と、を有する、半導体装置。 - 請求項4において、
前記キャパシタを有する層は、前記第3トランジスタを有する層の上方に設けられる、半導体装置。 - 請求項4又は請求項5において、
前記キャパシタを有する層は、複数のキャパシタが積層して設けられる、半導体装置。
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