JP7420468B2 - 集積回路基板と生産方法 - Google Patents
集積回路基板と生産方法 Download PDFInfo
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- JP7420468B2 JP7420468B2 JP2018157185A JP2018157185A JP7420468B2 JP 7420468 B2 JP7420468 B2 JP 7420468B2 JP 2018157185 A JP2018157185 A JP 2018157185A JP 2018157185 A JP2018157185 A JP 2018157185A JP 7420468 B2 JP7420468 B2 JP 7420468B2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- C—CHEMISTRY; METALLURGY
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- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Electroplating And Plating Baths Therefor (AREA)
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- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
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Description
図6は基板121を形成する方法200を示す概略図である。動作202において、誘電体レイヤ210上に、電気めっき銅トレースとビアのシードレイヤとして機能する電気メッキ銅レイヤが形成される。幾つかの実施形態では、シードレイヤはスパッタリングされてもよい。操作208において、誘電体レイヤ210上にシードレイヤ204がデポジションされた後、シードレイヤ上に感光性のドライフィルムレジストが形成される。これはリソグラフィプロセスを用いてシードレイヤ204上に開口を確成するようにパターニングされる。幾つかの実施形態では、DFR部206A-206Dは、他の幾つかのプロセスにより、積層され、デポジションされ、エッチングされ、及び/又は形成されてもよい。幾つかの実施形態では、DFR部206A-206Dは、シードレイヤ204上に積層され、次いでマスクされ感光されてもよい。パッド114A、ビア116及びトレース114B-114CがDFR開口に形成されてもよい。実施形態では、パッド、ビア及びトレースは、電解メッキなどのメッキプロセスにより形成されてもよい。実施形態では、パッド114A、ビア116及びトレース114B-114Cは銅から形成されてもよい。幾つかの実施形態では、パッド114A、ビア116及びトレース114B-114Cは、シードレイヤ204と同じ材料から形成されても、異なる材料から形成されてもよい。
追加的実施形態
集積回路の基板であって、
誘電体レイヤと、
xまたはy方向に延在し、前記誘電体レイヤに少なくとも部分的に埋め込まれた導電性レイヤとを有し、前記導電性レイヤは、
第1端と、対向する第2端とを有するビアであって、Z方向の第1の高さと、前記第1端と前記第2端との間に一定の断面形状とを有するビアと、
前記ビアに隣接し、異なるZ方向の前記第1の高さと第2の高さを有するトレースとを有する、基板である。
実施形態14が提供するものは、前記ビアは実質的に一定の幅を有する、実施形態1ないし13いずれか一項に記載の基板である。
集積回路の基板であって、
誘電体レイヤと、
金属伝送ラインであって、
xまたはy方向の第1の幅と、z方向の第1の高さとを有する第1の領域と、
xまたはy方向の第2の幅と、z方向の第2の高さとを有する第2の領域とを有し、
前記第1の高さは前記第2の高さより大きく、前記第1の領域はz方向で一定の断面形状を有する、基板である。
基板を形成する方法であって、
第1のパターン領域を電解銅組成物とコンタクトすることであって、前記電解銅組成物は、銅塩と、速度制御剤とを含む、ことと、
第2のパターン領域を電解銅組成物とコンタクトすることであって、前記電解銅組成物は、銅塩と、速度制御剤とを含む、ことと、
前記第1の領域の速度制御剤の第1の量は前記第2の領域の速度制御剤の第2の量とは異なり、前記第1と第2の領域は複数のドライフィルムレジスト要素により確成され、第1のペアの隣接するドライフィルムレジスト要素間の第1の領域のxまたはy方向の第1の距離は、第2のペアの隣接するドライフィルムレジスト要素間の第2の領域のxまたはy方向の第2の距離より大きく、
前記電解銅組成物に電圧をかけて前記パターン領域の銅レイヤにめっきすることと、
前記ドライフィルムレジスト要素を除去することと、
前記銅レイヤに第2の誘電体レイヤを積層することとを有する、方法である。
Claims (16)
- 集積回路の基板であって、
誘電体レイヤと、
xまたはy方向に延在し、前記誘電体レイヤに少なくとも部分的に埋め込まれた導電性レイヤとを有し、前記導電性レイヤは、
第1端と、対向する第2端とを有するビアであって、Z方向の第1の高さと、前記第1端と前記第2端との間に一定の断面形状とを有し、Z方向でほぼテーパーのないプロフィールを有するビアと、
前記ビアに隣接し、前記第1の高さとは異なるZ方向の第2の高さを有するトレースとを有し、前記トレースは、前記ビアを定める第1領域と、電気信号をxまたはy方向に搬送する第2領域とを含む、
基板。 - 前記誘電体レイヤはエポキシラミネート、ポリテトラフルオロエチレン、フェノールコットンペーパー、織りガラス、またはそれらの混合物である、請求項1に記載の基板。
- 前記導電性レイヤは銅を含む、請求項1に記載の基板。
- 前記ビアは実質的に一定の幅を有する、請求項1に記載の基板。
- 前記第1の高さは前記第2の高さより1.5倍ないし4倍大きい範囲にある、
請求項1に記載の基板。 - 前記ビアの幅は前記トレースの幅より1.5倍ないし4倍大きい範囲にある、
請求項1に記載の基板。 - 集積回路の基板であって、
誘電体レイヤと、
金属伝送ラインであって、
xまたはy方向の第1の幅と、z方向の第1の高さとを有する第1の領域と、
xまたはy方向の第2の幅と、z方向の第2の高さとを有する第2の領域とを有し、
前記第1の高さは前記第2の高さより大きく、前記第1の領域はz方向で一定の断面形状を有し、前記第1の領域はビアを定め、前記第2の領域は電気信号を搬送し、前記ビアはZ方向でほぼテーパーのないプロフィールを有する、
基板。 - 前記誘電体レイヤはエポキシラミネート、ポリテトラフルオロエチレン、フェノールコットンペーパー、織りガラス、またはそれらの混合物である、
請求項7に記載の基板。 - 前記誘電体レイヤは誘電体材料の複数の個別レイヤを含む、
請求項8に記載の基板。 - 前記誘電体レイヤは異なる誘電体材料を含む、
請求項7に記載の基板。 - 誘電体材料の個別レイヤは同じ誘電体材料を含む、
請求項7に記載の基板。 - 前記金属伝送ラインは銅を含む、
請求項7に記載の基板。 - 前記一定の断面形状は、円、楕円、三角形、正方形、長方形、五角形、六角形、七角形、及び八角形から選択される、
請求項7に記載の基板。 - 前記第1の高さは前記第2の高さより1.5倍ないし4倍大きい範囲にある、
請求項7に記載の基板。 - 前記第1の領域の幅は前記第2の領域の幅より1.5倍ないし4倍大きい範囲にある、請求項7に記載の基板。
- 前記第1の領域はビアであり、前記第2の領域はトレースである、
請求項7に記載の基板。
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US11942334B2 (en) * | 2018-12-21 | 2024-03-26 | Intel Corporation | Microelectronic assemblies having conductive structures with different thicknesses |
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