JP7355148B2 - Light source driving device, light source driving method, and liquid crystal display device - Google Patents

Description

The present invention relates to a light source driving device, a light source driving method, and a display device.

2. Description of the Related Art Analog drive methods and digital drive methods are known as drive methods for driving liquid crystal display elements used in liquid crystal display devices. The analog drive method is a drive method in which the voltage value applied to the pixel is a continuous analog value. In the digital drive method, the magnitude of the voltage applied to the pixel is binary, and by changing the time width of the applied voltage according to the brightness (gradation) of the image, the effective voltage value applied to the pixel of the liquid crystal can be adjusted. This is a control drive method. The digital drive method is characterized in that the information applied to the pixel is either "0" or "1" and is therefore less susceptible to external factors such as noise.

In the digital drive system, a technique is known in which one frame of a video signal is time-divisionally controlled to obtain intermediate gradations. For example, Patent Document 1 discloses that one frame period of a video signal is equally divided to form a plurality of subframes, and the subframes are appropriately selected and displayed according to the gradation of the video signal to be displayed. A technique for expressing intermediate gradations using the visual integral effect has been disclosed.

JP2013-092548A

Incidentally, it is known that human reactions to gradations are not linear, and that people react more sensitively to lower gradations (darker images). On the other hand, in the above-mentioned driving method using gradation control using subframes, the illuminance at each gradation is the sum of the illuminances of subframes selected at that gradation. The relationship between voltage application time and transmittance for liquid crystals is not linear, and is similar to the human reaction to gradation, but the deviation becomes large in areas with low gradation, resulting in visually unnatural images. There was a problem with this.

The present invention has been made in view of the above, and an object of the present invention is to improve display quality when a liquid crystal display element is driven by a digital drive method.

In order to solve the above-mentioned problems and achieve the objects, the present invention includes a division period creation unit that creates division periods by dividing the frame period of a video signal, and a division period generation unit that creates division periods by dividing the frame period of a video signal, and a light source control section that drives a light source that irradiates light to a display element whose on and off are controlled for each pixel according to a video signal, and the light source control section has a light source control section that drives a light source that irradiates light to a display element whose on and off are controlled for each pixel according to a video signal; The first light amount in one division period is set to be lower than the second light amount in a second division period other than the first division period, and the first light amount is set in all gradations except black display. In all gradations except black display, the minimum resolution of each gradation is smaller than 1 when the first light amount and the second light amount are the same, and it becomes smaller as the gradation becomes smaller. The present invention is characterized in that it is possible to change the monotonically decreasing curve in the gradation direction by controlling the first light quantity to form a monotonically decreasing curve.

According to the present invention, it is possible to improve display quality when driving a liquid crystal display element using a digital drive method.

FIG. 1 is a diagram showing the configuration of an example of a display system applicable to each embodiment. FIG. 2 is a block diagram schematically showing the configuration of an example of the projection device according to the first embodiment. FIG. 3 is a diagram illustrating an example of the relationship between gradation values, subframes, and pixel on/off control according to the first embodiment. FIG. 4 is a diagram showing a comparison between a gamma curve of γ=2.2 and an example of input/output characteristics of the projection section. FIG. 5 is a time chart for explaining light source control according to the first embodiment. FIG. 6 is a diagram showing an example of each pixel of the display element. FIG. 7 is a diagram illustrating an example of the relationship between on/off control of each pixel in a display element and light amount control of a light source, according to the first embodiment. FIG. 8 is a diagram for explaining the effect when performing light source control according to the first embodiment. FIG. 9 is a diagram illustrating an example of a change in minimum resolution for each gradation value n according to the first embodiment. FIG. 10 is a diagram illustrating an example of controlling a light source according to a modification of the first embodiment. FIG. 11 is a diagram showing the configuration of an example of a projection device according to the second embodiment. FIG. 12 is a diagram illustrating a configuration example of a display element in a cross section in a direction parallel to the incident direction of light. FIG. 13 is a diagram showing an example of characteristics of a display element. FIG. 14 is a block diagram showing an example of the configuration of the video processing/drive section and the pixel electrode section according to the second embodiment. FIG. 15 is a block diagram showing the configuration of an example of a pixel circuit according to the second embodiment. FIG. 16 is a diagram for explaining the flow of processing in the signal conversion section, error diffusion section, frame rate control section, and subframe data creation section according to the second embodiment. FIG. 17 shows an example of a frame rate control table according to the second embodiment. FIG. 18 is a diagram showing an example of a drive gradation table applicable to the second embodiment. FIG. 19 is a time chart showing an example of control according to the second embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a light source driving device, a display device, and a light source driving method will be described in detail below with reference to the accompanying drawings. The specific numerical values and external configurations shown in the embodiments are merely illustrative to facilitate understanding of the present invention, and do not limit the present invention unless otherwise specified. Note that detailed explanations and illustrations of elements not directly related to the present invention are omitted.

FIG. 1 shows the configuration of an example of a display system applicable to each embodiment. In FIG. 1, a projection device 100 as a display device includes a light source and a display element. The projection device 100 modulates the light emitted from the light source using a display element based on the video signal supplied from the video output device 101, and outputs the modulated light as projection light according to the video signal. Projection light emitted from the projection device 100 is projected onto a projection medium 102 such as a screen, and is displayed on the projection medium 102 as a projected image according to a video signal.
(First embodiment)
A projection device according to a first embodiment will be described. FIG. 2 schematically shows the configuration of an example of the projection device according to the first embodiment. In FIG. 2, a projection device 100a corresponding to the projection device 100 in FIG. Control unit 113 and projection unit 122
Equipped with. Further, the projection section 122 includes a light source 120 and a display element 121. Here, the configuration including the subframe creation section 112 and the light source control section 113 is referred to as a light source driving device.

A video signal is input to the video processing section 110. Here, it is assumed that the video signal is a digital video signal for displaying a moving image in which frame images are updated at a predetermined frame period (for example, 60 frames/second). The present invention is not limited to this, and an analog video signal may be converted into a digital video signal in the video processing unit 110, for example. Furthermore, for the sake of explanation, it is assumed that the video signal can express 13 gradations from gradation value "0" to gradation value "12" for each pixel. Here, the gradation value "0" and the gradation value "12" correspond to black display and white display, respectively, and the gradation value "1" to "11" correspond to the brightness according to the gradation value. Compatible with halftone display.

The video processing unit 110 extracts a frame synchronization signal Vsync indicating the beginning of the frame and gradation information Grad for each pixel from the input video signal. The gradation information Grad includes the gradation value (luminance value) of the pixel. The video processing unit 110 transmits the extracted gradation information Grad to the driving unit 11.
Supply to 1. Further, the video processing unit 110 supplies the extracted frame synchronization signal Vsync to the subframe creation unit 112.

The subframe creation unit 112 receives a frame synchronization signal Vs supplied from the video processing unit 110.
A divided period is created by dividing one frame period from ync. Subframe creation section 112
For example, one frame period is divided by the number of divisions corresponding to the number of gradations of the video signal to create division periods. This division period is hereinafter referred to as a subframe.

In this example where the video signal can express 13 gradations, the subframe creation unit 112 divides one frame period into 12 subframes SF1, SF2, . . . , SF12, which is one less than the number of gradations. This is because, as will be described in detail later, at tone value "0" or tone value "12", the off state or on state of the pixel is maintained within one frame period.

For example, the subframe creation unit 112 creates each divided subframe SF1, SF2,...
A subframe synchronization signal SFsync indicating the timing of SF12 is generated, and the generated subframe synchronization signal SFsync is output together with the frame synchronization signal Vsync. The frame synchronization signal Vsync and subframe synchronization signal SFsync output from the subframe creation section 112 are supplied to the drive section 111 and the light source control section 113, respectively.

The light source control unit 113 generates a light source control signal for controlling light emission of the light source 120 based on the frame synchronization signal Vsync and subframe synchronization signal SFsync supplied from the subframe generation unit 112. The light source 120 is, for example, a semiconductor laser, and the emission of laser light is controlled according to a light source control signal supplied from the light source control section 113. For example, at least the intensity (brightness) of the emitted laser light of the light source 120 is controlled according to the light source control signal. Furthermore, the light emission timing of the light source 120 can be controlled at least in units of the above-mentioned subframes according to the light source control signal. Details of the light emission control of the light source 120 by the light source control unit 113 will be described later.

Note that the light source 120 may be any other type of light source as long as the light emission intensity can be controlled according to the light source control signal and the light emission timing can be controlled in subframe units. For example, an LED (Light Emitting Diode) may be used as a light source, or a UHP (Ultra High Perf)
It is also possible to use a lamp (ormance).

On the other hand, the driving unit 111 controls the display element 121 based on the gradation information Grad for each pixel supplied from the video processing unit 110 and the frame synchronization signal Vsync and subframe synchronization signal SFsync supplied from the subframe creation unit 112. Generates a drive signal to drive the. The drive signal is supplied to the display element 121.

The display element 121 has pixels arranged in a matrix, and modulates and emits light incident from the light source 120 for each pixel according to a drive signal based on a video signal supplied from the drive unit 111. In the first embodiment, a liquid crystal display element using the characteristics of liquid crystal is used as the display element 121. In a liquid crystal display element, a liquid crystal is sandwiched between a pixel electrode for each pixel and a common electrode common to each pixel, and a voltage is applied to each pixel by the pixel electrode according to a video signal, so that light in a specific polarization direction is generated. Images are displayed by changing the transmittance of the liquid crystal.

In the first embodiment, a reflective liquid crystal display element is used as the display element 121. In a reflective liquid crystal display element, the irradiated light passes through the liquid crystal layer from the incident surface and is irradiated onto the reflective surface.
The light is reflected by the reflective surface, passes through the liquid crystal layer again, and is emitted to the outside from the incident surface. A reflective liquid crystal display element changes the polarization state of incident light before emitting it, so a polarization beam splitter or the like is used to separate the incident light and the output light.

In the projection device 100a, the projection unit 12 includes a light source 120 and a display element 121.
2 is configured. The projected image projected onto the projection medium 102 has characteristics that are a combination of the characteristics of the light source 120 included in the projection section 122 and the characteristics of the display element 121. Hereinafter, the characteristics obtained by integrating the characteristics of the light source 120 and the characteristics of the display element 121 will be defined as the characteristics of the projection section 122. Furthermore, the drive signal input to the display element 121 is input to the projection section 122, and the light emitted from the light source 120 via the display element 121 is output from the projection section 122.

Next, the digital drive method according to the first embodiment will be explained in more detail. In the first embodiment, the drive unit 111 drives the display element 121 using a digital drive method. In the digital drive method according to the first embodiment, the drive unit 111 controls the pixels in two states: an on state and an off state. Note that the on state is, for example, a state in which the transmittance of the liquid crystal is the highest, and a state in which a substantially white display (white display) occurs when white light is incident on the liquid crystal.
Further, the off state is, for example, a state in which the transmittance of the liquid crystal is the lowest, and when white light is incident on the liquid crystal, a substantially black display (black display) is obtained. Further, the driving unit 111 controls a certain pixel to be in an on state in a number of subframes according to the gradation value of the pixel among subframes within one frame period, and in an off state in other subframes. By controlling, gradation is expressed in the pixel.

FIG. 3 shows an example of the relationship between tone values, subframes, and pixel on/off control according to the first embodiment. In FIG. 3, each column includes subframes SF1, SF2,
..., SF12. Among these, subframe SF1 is the first subframe of the frame period, and subframe SF12 is the last subframe of the frame period. Further, in FIG. 3, the gradation value of each row increases from 0 to 1 from top to bottom. Gradation value “0”
" is the lowest (dark) gradation, and gradation value "12" is the highest (bright) gradation.

In the first embodiment, the driving unit 111 selects a number of subframes corresponding to the gradation value of a pixel in order from the beginning of the frame period, and controls the pixel to be in an on state in the selected subframe. In FIG. 3, a hatched cell with a value of "1" indicates that a pixel is controlled to be in an on state, and a cell with a value of "0" indicates that a pixel is controlled to be in an off state.

For example, when the tone value of a certain pixel is "3", the driving unit 111 drives three subframes (subframes SF1, SF2, and
Select 3). Then, the driving unit 111 controls the pixel to turn on in the selected subframe. Further, in the other nine subframes (subframes SF4 to SF12), the driving unit 111 controls the pixels to be in the off state.

Further, for example, when the gradation value of a certain pixel is "12", the driving unit 111 selects 12 subframes (subframes SF1 to SF12) from the first subframe SF1 of the frame period.
). Then, the driving unit 111 controls the pixel to turn on in the selected subframe. In this case, there is no subframe to be controlled to the off state.

Further, for example, when the gradation value of a certain pixel is "0", the driving unit 111 controls the pixel to be in an OFF state in all subframes (subframes SF1 to SF12) within one frame period. In this case, there is no subframe to be controlled to be in the on state.

In this manner, in the first embodiment, subframes for performing on and off control are allocated in advance for each gradation. Further, at a gradation value of "0", the pixel is maintained in an off state within the frame period, and at a gradation value of "12", the pixel is maintained in an on state within the frame period. In this way, the gradations of gradation value "0" and gradation value "12" can be achieved by controlling all subframes within a frame period to the off state and on state. Twelve subframes are sufficient.

Here, the characteristics of the projection section 122 will be explained. Generally, the input/output characteristics of a display are not linear, and the output is expressed by a downwardly convex curve relative to the input. Therefore, video signal processing is also performed according to this input/output characteristic. As a curve representing the input/output characteristics of a display, a gamma curve with a gamma value γ=2.2, for example, is generally used. The gamma curve is
When the input value is VIN and the output value is VOUT, it is expressed as VOUT=VINγ.

For example, by supplying a video signal corrected according to a gamma curve with a gamma value of 1/γ to a display whose input/output characteristics have a gamma value of γ, linear gradation expression can be obtained. For example, the video signal output from the video output device 101 generally has a linear gradation characteristic, but has a gradation characteristic that is corrected based on a gamma curve with a gamma value of 1/γ≈0.455.

The input/output characteristics of the projection unit 122 including the display element 121 using liquid crystal are also not linear, but are expressed by a curve in which the output is convex downward relative to the input, similar to the input/output characteristics of a display. For example, the input to the projection unit 122 corresponds to the gradation value of the video signal. In the first embodiment,
As explained using FIG. 3, the gradation value corresponds to the voltage application time to the liquid crystal layer. Furthermore, the output of the projection unit 122 is based on the amount of light from the light source 120 and the transmittance of the liquid crystal. More specifically, the output of the projection unit 122 is that light from the light source 120 is transmitted to the projection medium 1 via the display element 121.
This corresponds to the brightness on the projection medium 102 when projected at 02.

FIG. 4 shows a comparison between the reference characteristic and an example of the input/output characteristic of the projection unit 122, using the input/output characteristic according to the gamma curve of γ=2.2 as the reference characteristic. In FIG. 4(a), the horizontal axis shows the input, that is, the video signal, with the maximum value normalized to 1. In the above example, the input value "1" corresponds to the gradation value "12". Further, in FIG. 4(a), the vertical axis shows the output, that is, the brightness, with the maximum value normalized to 1. Note that the brightness is the brightness on the projection medium 102 when light from the light source 120 is projected onto the projection medium 102 via the display element 121, as described above. Furthermore, in the example of FIG. 4(a), it is assumed that the amount of light from the light source 120 is controlled to be constant.

FIG. 4(b) is an example in which the portion indicated by range A in FIG. 4(a) is enlarged. Figure 4 (a
) and FIG. 4B, a characteristic line 140 represents a reference characteristic (a characteristic according to a gamma curve with γ=2.2), and a characteristic line 141 represents an input/output characteristic of the display element 121, respectively.

As shown in FIG. 4(a), in the range of high input values such as input value ≧0.5 (gradation value "7" or more), the characteristic line 140 and the characteristic line 141 substantially match, and the projection part It can be considered that the input/output characteristics of No. 122 are substantially equal to the reference characteristics.

On the other hand, in a low input value range such as input value <0.5 (gradation value "6" or less), the characteristic line 140 and the characteristic line 141 do not overlap, and the input/output characteristics of the projection section 122 match the reference characteristics. On the other hand, it is shifted toward the higher output (brightness) side. Even in the range A including the lowest input value in FIG. 4(a), the input/output characteristics of the projection section 122 are shifted toward the higher output (brightness) side with respect to the reference characteristics, as shown in FIG. 4(b). There is.

When the projection unit 122 is driven with the input/output characteristics according to the characteristic line 141, the image is generated by the video signal of the input value in the range of high gradation values, that is, in the range where the characteristic line 141 and the characteristic line 140 substantially match. Regarding the display, it is thought that the display will be approximately as intended. On the other hand, when displaying an image using a video signal with an input value in a range of low gradation values, that is, in a range where the characteristic line 141 deviates to the high output side with respect to the characteristic line 140, the image is displayed brighter than the intended image. will be done. This can be a factor in deteriorating the display quality of dark video areas in the video of the video signal.

Therefore, in the first embodiment, by controlling the light amount of the light source 120 within one frame period, the input/output characteristics of the projection section 122 are brought close to, for example, the reference characteristics. More specifically, in the first embodiment, the light amount of the light source 120 is controlled in subframe units, and the light amount of the light source 120 is controlled to display black (gradation value "0") included in each subframe SF1 to SF12. The first light amount in the first sub-frame corresponding to the lowest gradation excluding the first sub-frame is controlled to be lower than the second light amount in the second sub-frame other than the first sub-frame.

The light source control according to the first embodiment will be described in more detail using the time chart of FIG. 5. In FIG. 5, time progresses toward the right. FIG. 5(a) shows an example of a frame synchronization signal Vsync representing a frame period. The period from a rising edge of a signal to the next rising edge is defined as one frame period.

FIG. 5(b) shows an example of the subframe synchronization signal SFsync representing the subframe period. Similar to the frame synchronization signal Vsync, the subframe synchronization signal SFsync also has one subframe period from the rising edge of the signal to the next rising edge. Figure 5
In the example of (b), corresponding to FIG. 3 described above, one frame period is divided into 12 subframes SF1 to SF12 in the time axis direction.

FIG. 5(d) shows an example of light amount control of the light source 120 using existing technology. In the existing technology, the light amount of the light source 120 is controlled to be uniform in all subframes SF1 to SF12, as indicated by diagonal lines in FIG. 5(d). Each subframe SF at this time
The light intensity of the light source 120 in SF1 to SF12 is set to 100%. The characteristic line 141 in FIG. 4 described above corresponds to this existing technology.

FIG. 5C shows an example of light amount control of the light source 120 according to the first embodiment. In the first embodiment, the light source control unit 113 controls the light source 1 in the first subframe SF1 of the frame period.
Control is performed to reduce the light intensity of 20 at a reduction rate of 50%, for example, and
At F2 to SF12, the light intensity of the light source 120 is controlled to 100%. subframe SF
1 is a subframe in which pixels are controlled to be turned on at the lowest gradation except for black display (gradation value "0"), as shown in FIG. 3 above. Therefore, in this subframe SF1,
Pixels are controlled to be turned on in common for each gradation except for the gradation with the gradation value "0".

Control of the projection unit 122 according to the first embodiment will be described in more detail using FIGS. 6 and 7. FIG. 6 shows an example of each pixel of the display element 121. Here, for explanation,
It is assumed that the display element 121 includes 5 pixels x 5 pixels, and each pixel is indicated by coordinates (xn, yn). The numerical values in each square in FIG. 6 indicate an example of the gradation value of each pixel according to the video signal.

FIG. 7 shows on/off control of each pixel in the display element 121 according to the first embodiment, and
An example of the relationship with light amount control of the light source 120 is shown. Note that in FIG. 7, time progresses toward the right.

FIG. 7A shows an on period 130 in which five pixels at coordinates (x0, y0) to (x4, y0) are controlled to be in the on state in the example of FIG. Referring to FIG. 6, the drive unit 112 is
For pixel (x0, y0), subframes SF1 to SF3 are set to ON interval 130 for gradation value "3", and for pixel (x1, y0), subframes are set for gradation value "1". Only the frame SF1 is set as the ON period 130. Further, the driving unit 112 causes the pixel (x2, y0) to have a gradation value of "
0'', the ON section 130 is not provided. Further, the driving unit 112 drives the pixel (x3, y0)
Since the gradation values are "5" and "9" for pixels (x4, y0), respectively, subframes SF1 to SF5 and subframes SF1 to SF9 are set to ON period 13.
It is set to 0.

FIG. 7B shows an example of light amount control of the light source 120. In this example, similar to FIG. 5(c),
The light source control unit 113 controls the light source 120 to reduce the light amount at a reduction rate of 50% in the subframe SF1, and controls the light amount to 100% in the other subframes SF2 to SF12. Therefore, each pixel (x0, y0), (x1, y0), (x3, y0) and (x4, y
0), the brightness (light amount) is 50% in subframe SF1. And each pixel (x0,
y0), (x3, y0), and (x4, y0) have 100% luminance (light amount) from subframe SF2 onwards.

Therefore, each pixel (x0, y0), (x1, y0), (x3, y0) except the black display pixel (x2, y0)
0) and (x4, y0) are the light intensity of the light source 120 shown in FIG. 5(d) for all subframes SF1.
~Compared to the case where the light amount is controlled to be uniform in SF12, the brightness (light amount) is lowered by reducing the light amount in subframe SF1 at a reduction ratio of 50%.

For example, it is assumed that the brightness when the light amount of the light source 120 is 100% is normalized as "1", and in each pixel, the light amount of the light source 120 in each subframe is simply added. In this case, according to the light source control according to the first embodiment, each pixel (x0, y0), (x1, y0), (x3, y
0) and (x4, y0) are "2.5", "0.5", "4.5", and "8.5", respectively. On the other hand, in the case of existing technology that makes the light intensity of the light source uniform in each subframe SF1 to SF12, each pixel (x0, y0), (x1, y0), (x3, y0) and
The brightness (light amount) of (x4, y0) is "3", "1", "5", and "9", respectively.

Comparing the luminance (light amount) of each pixel when the light amount control according to the first embodiment is performed and the existing technology, it can be seen that the lower the gradation, the larger the ratio between the two, except for black display.

The effects of the light source control according to the first embodiment will be described using FIG. 8.
Note that in FIG. 8, parts common to those in FIG. 4 described above are denoted by the same reference numerals, and detailed description thereof will be omitted. FIGS. 8(a) and 8(b) show the input and output of the projection unit 122 when the light source control according to the first embodiment is performed with respect to FIGS. 4(a) and 4(b) described above. A characteristic line 142 indicating an example of the characteristic is added.

In the example of FIG. 8, the light amount of the light source 120 is controlled to 50% in subframe SF1 and 100% in each of the other subframes SF2 to SF12. By controlling in this way, the characteristic line 142 according to the first embodiment is changed from the characteristic line 141 according to the existing technology in the range of low input values, for example, input value < 0.5 (gradation value "6" or less). Compared to the characteristic line 140
In other words, it can be seen that the characteristics are close to the reference characteristics. On the other hand, in a range of high input values such as input value≧0.5 (gradation value "7" or more), the characteristic line 142 substantially coincides with the characteristic line, as in the existing technology.

Therefore, by performing the light source control according to the first embodiment, the display of the video using the video signal of the input value in the low gradation range becomes closer to the intended video compared to the existing technology, and compared to the existing technology. display quality can be improved.

The minimum resolution of the output value can be expressed by the output value at unit input value. Figure 8 (
As shown in b), at a certain input value p, the minimum resolution L in the existing technology and the first
Let us consider the minimum resolution L' when the light quantity control according to the embodiment is performed. In this case, when the light amount a of subframe SF1 is set to "0≦a≦1" and the light amount b of the other subframes SF2 to SF12 is set to "1", the minimum resolution L' is L'=a×L. can do.

Here, when "0≦a/b≦1", the minimum resolution L'(n) at tone value n is expressed by the following equation (1). Note that in equation (1), n>0. Further, the value n indicating the order of the subframes SF corresponds to the gradation value.

FIG. 9 shows an example of a change in the minimum resolution calculated according to equation (1) for each gradation value n, according to the first embodiment. In FIG. 9, the vertical axis shows the ratio L'/L between the minimum resolution L' according to the first embodiment and the minimum resolution L according to the existing technology, and the horizontal axis shows the gradation value n. Further, the characteristic line 150 is an example for the case of "a=0.5, b=1", the characteristic line 151 is an example for the case of "a=0.3, b=1", and the characteristic line 152 is an example for the case of "a=0". .7, b=1'' are shown below.

As shown in FIG. 9, as the gradation value n increases, the value of the ratio L'/L approaches "1",
As the gradation value n becomes smaller, the value of the ratio L'/L becomes smaller. Also, if the gradation value n is below a certain value (
For example, at gradation values "4" to "5" or less), the degree of change in the value of the ratio L'/L to the gradation value n becomes large. Therefore, the value of the gradation value n is in a range below a certain value, for example, "1≦n≦4~
In the range of 5'', the minimum resolution becomes smaller, and the display quality in dark video areas can be improved.

Also, as shown in characteristic lines 150, 151 and 152, the ratio L'
The degree of change in /L is different. Therefore, in the light source control unit 113, for example, by fixing the light amount b to "1" and adjusting the light amount a between 0≦a≦1, it is possible to perform more appropriate control. For example, it is possible to change the value a depending on the characteristics of the light source 120 and the display element 121.
(Modified example of the first embodiment)
Next, a modification of the first embodiment will be described. In the first embodiment described above, among the subframes SF1 to SF12 obtained by dividing the frame period, the light source is only used in one subframe SF1 corresponding to the lowest gradation value excluding black display (gradation value "0"). 120 was controlled to reduce the amount of light. On the other hand, in a modification of the first embodiment, the amount of light from the light source 120 is reduced in a plurality of subframes SF.

FIG. 10 shows an example of controlling the light source 120 according to a modification of the first embodiment. In the example of FIG. 10, the light source control unit 113 selects the subframe SF1 corresponding to the lowest gradation value excluding black display among the subframes SF1 to SF12 obtained by dividing the frame period, and this subframe SF1.
Control is performed to reduce the amount of light from the light source 120 in three subframes SF, ie, subframes SF2 and SF3, which are temporally consecutive to SF1.

The degree of reduction in the amount of light in each subframe SF1 to SF3 is determined so that the input/output characteristics of the projection section 122 approach the reference characteristics. In the example of FIG. 10, the light amount of the light source 120 is controlled to be uniformly reduced at a reduction ratio of 25% in each subframe SF1 to SF3, but this is not limited to this example. For example, the reduction ratio of the light amount of the light source 120 is not limited to 25%. Further, for example, the light amount of the light source 120 may be reduced at different reduction ratios in each of the subframes SF1 to SF3.

Further, in the above description, the subframe creation unit 112 creates each subframe SF by equally dividing the frame period, but this is not limited to this example. That is, the subframe creation unit 112 may vary the length of each subframe SF.
(Second embodiment)
Next, a second embodiment will be described. FIG. 11 shows the configuration of an example of a projection device 100b corresponding to the projection device 100 of FIG. 1 according to the second embodiment. Projection device 100b includes an image processing/driving section 200 and a projection section 240. Further, the projection unit 240 includes a light source 210, an illumination optical system 211, a light separator 212, a projection optical system 213, and a display element 220.

The video processing/driving unit 200 generates a light source control signal for controlling the light source 210 and a drive signal for driving the display element 220, based on the video signal supplied from the video output device 101, for example.

The light source 210 corresponds to the light source 120 in FIG. 2, and uses, for example, a semiconductor laser. light source 2
The light emitted from 10 is incident on a light separator 212 via an illumination optical system 211. The light that enters the light separator 212 from the illumination optical system 211 is light that includes P-polarized light and S-polarized light.

The light separator 212 includes a polarization separation surface that separates P-polarized light and S-polarized light included in the light, and allows the P-polarized light to pass through the polarization separation surface and reflects the S-polarized light. A polarizing beam splitter can be used as the optical separator 212. The light incident on the light separator 212 from the illumination optical system 211 is separated into P-polarized light and S-polarized light by the polarization separation surface, and the P-polarized light is transmitted through the polarization separation surface.
The S-polarized light is reflected by the polarization separation surface and irradiated onto the display element 220.

The display element 220 corresponds to the display element 121 in FIG. 2, and is, for example, a reflective liquid crystal display element. FIG. 12 shows an example of the configuration of the display element 220 in a cross section taken in a direction parallel to the direction of light incidence.
The display element 220 includes a counter electrode 2201, a pixel electrode section 2203 including a pixel electrode and a pixel circuit that drives the pixel electrode, and a liquid crystal layer 2202. It is configured with a layer 2202 in between. The display element 220 has a liquid crystal layer 2202 between a pixel electrode and a counter electrode 2201 according to a drive signal supplied to the pixel circuit.
A voltage is applied to the

The S-polarized light incident on the display element 220 is incident on the pixel electrode portion 2203 from the counter electrode 2201 via the liquid crystal layer 2202, is reflected by the pixel electrode portion 2203, and then passes through the liquid crystal layer 2202 and the counter electrode 2201 again for display. The light is emitted from the element 220. At this time, the liquid crystal layer 22
02 modulates incident and reflected S-polarized light in accordance with a voltage applied between the counter electrode 2201 and the pixel electrode of the pixel electrode portion 2203 in accordance with a drive signal. The S-polarized light incident on the counter electrode 2201 is modulated in the process of being reflected by the pixel electrode portion 2203 and emitted from the counter electrode 2201, and is emitted from the counter electrode 2201 as light consisting of P-polarized light and S-polarized light.

FIG. 13 shows an example of the characteristics of the display element 220. In FIG. 13, the horizontal axis indicates the applied voltage applied to the liquid crystal layer 2202 by the pixel electrode and the counter electrode 2201. The vertical axis is the liquid crystal layer 2
202 is shown. The intensity of light emitted from the display element 220 depends on this transmittance. The transmittance of the liquid crystal layer 2202 is approximately 0% when the applied voltage is 0 V, and is in an off state. The transmittance gradually increases as the applied voltage increases, and when it exceeds the threshold voltage Vth,
This will be a rapid increase. The transmittance is saturated at the saturation voltage Vw. This saturation voltage Vw is the white level voltage. The display element 220 performs display using a transmittance between 0V and the saturation voltage Vw, for example.

Returning to FIG. 12, the light including P-polarized light and S-polarized light emitted from the display element 220 is incident on the light splitter 212, where the S-polarized light is reflected at the polarization separation surface and the P-polarized light is transmitted. The transmitted P-polarized light is emitted from the light separator 212, enters the projection optical system 213, and is emitted from the projection device 100b as projection light. The projection light emitted from the projection device 110b is projected onto the projection medium 102, and a projected image is displayed on the projection medium 102.

Note that in the second embodiment as well, the input/output characteristics of the projection section 240 are as shown by the characteristic line 141 in FIG. 4, similar to the input/output characteristics of the projection section 122 in the first embodiment described above. It is assumed that the characteristics are shifted toward the high luminance side in the low gradation range with respect to the reference characteristics.

FIG. 14 shows an image processing/driving unit 200 included in a projection device 100b according to the second embodiment.
An example of the configuration of the pixel electrode portion 2203 is also shown. Projection device 100 according to this second embodiment
Similar to the projection device 100a according to the first embodiment described above, b divides the frame period of the video signal to create divided periods, that is, sub-frames SF, and calculates the tone value of each pixel for each pixel of the video signal. A digital driving method is applied that expresses gradation by controlling the ON state in a number of subframes SF corresponding to the number of subframes SF. In the following, as in the first embodiment described above, the gradation is expressed by 13 gradations from gradation values "0" to "12", and the frame period is set to 12 which is one less than the number of gradations.
It is assumed that 12 subframes SF1 to SF12 are created by dividing the frame into equal division periods.

In FIG. 14, the video processing/drive section 200 includes a signal conversion section 21, an error diffusion section 23,
Frame rate control section 24, limiter section 25, and subframe data creation section 2
6, a drive gradation table 27, a memory control section 28, a frame buffer 29, a data transfer section 30, a drive control section 31, a voltage control section 32, and a light source control section 230.

Further, the pixel electrode section 2203 includes a source driver 33, a gate driver 34, and each pixel circuit 2210, 2210, . . . . Note that the source driver 33 and the gate driver 34 may be provided outside the pixel electrode section 2203.

In the pixel electrode section 2203, the pixel circuits 2210, 2210, ... are arranged in a matrix, connected in the column direction by column data lines D0, D1, ..., Dn, and connected in the row direction by row selection lines W0, W1, ... ..., respectively connected by Wm. The column data lines D0, D1,..., Dn are
Each is connected to a source driver 33. Further, row selection lines W0, W1, . . . , Wm are connected to gate drivers 34, respectively.

The memory control unit 28 receives a frame synchronization signal V from a subframe data creation unit 26, which will be described later.
sync and a subframe synchronization signal SFsync are supplied. In addition, the memory control unit 2
8 stores the subframe data (described later) of each subframe SF created by the subframe data creation unit 26 in the frame buffer 29 divided into each subframe SF according to the subframe synchronization signal SFsync. The frame buffer 29 has a double buffer structure including two frame buffers, and while storing video signal data in one frame buffer, the memory control unit 28 stores subframe data from the other frame buffer. Can be read.

The drive control unit 31 is supplied with the frame synchronization signal Vsync and the subframe synchronization signal SFsync from the subframe data creation unit 26, and controls the timing of processing for each subframe SF. The drive control unit 31 issues a transfer instruction to the data transfer unit 30 and controls the source driver 33 and gate driver 34 based on these synchronization signals. More specifically, the drive control unit 31 controls the frame synchronization signal Vsync and the subframe synchronization signal S.
Based on Fsync, a vertical start signal VST and a vertical shift clock signal VCK;
A horizontal start signal HST and a horizontal shift clock signal HCK are generated.

The vertical start signal VST and the horizontal start signal HST are each subframe SF.
Specify the start timing and the line start timing. Vertical shift clock signal V
CK specifies row selection lines W0, W1, . . . , Wm. In addition, the horizontal shift clock signal HCK
specifies the column data lines D0, D1, . . . , Dn. Vertical start signal VST and vertical shift clock signal VCK are supplied to gate driver 34. Further, the horizontal start signal HST and the horizontal shift clock signal HCK are supplied to the source driver 33.

The data transfer section 30 instructs the memory control section 28 to read the subframe data of the designated subframe SF from the frame buffer 29 under the control of the drive control section 31 . The data transfer unit 30 receives the subframe data read from the frame buffer 29 from the memory control unit 28, and transfers the received subframe data to the drive control unit 28.
1, the data is transferred to the source driver 33 in units of lines, for example.

Every time the source driver 33 receives one line of subframe data from the data transfer unit 30, the source driver 33 transfers the column data lines D0, D1, . . . to the corresponding pixel circuits 2210, 2210, .
, Dn. Further, the gate driver 34 has row selection lines W0, W1, . . .
Of Wm, the row selection line of the row designated by the vertical start signal VST and vertical shift clock signal VCK supplied from the drive control section 31 is activated. As a result, subframe data for each pixel is transferred to the pixel circuits 2210 in all columns of the specified row.

The drive control unit 31 further generates a voltage timing signal based on the frame synchronization signal Vsync and the subframe synchronization signal SFsync. The voltage timing signal is supplied to the voltage control section 32. Further, the voltage control unit 32 is supplied with a zero voltage Vzero having a voltage value of 0V and a saturation voltage Vw. The voltage control unit 32 applies a voltage based on the zero voltage Vzero and the saturation voltage Vw to each pixel circuit 2210, 2210, . . . at the timing indicated by the voltage timing signal. It is supplied as a voltage V1. The voltage control unit 32 also controls a common voltage Vcom to be supplied to the counter electrode 2201.
Output. Note that the blanking voltage and the driving voltage correspond to voltages that control a pixel to be in an off state and an on state, respectively.

FIG. 15 shows an example configuration of a pixel circuit 2210 according to the second embodiment. Pixel circuit 22
10 includes a sample/hold unit 16 and a voltage selection circuit 17, and the output of the voltage selection circuit 17 is supplied to the pixel electrode 2204. Note that the common voltage Vcom is supplied to the counter electrode 2201 that faces the pixel electrode 2204 with the liquid crystal layer 2202 in between. The sample/hold unit 16 is composed of a flip-flop having an SRAM (Static Random Access Memory) structure. The sample/hold section 16 receives signals from the column data line D and the row selection line W, and its output is supplied to the voltage selection circuit 17 . The voltage selection circuit 17 receives the voltage V from the voltage control section 32.
0 and voltage V1 are supplied.

Next, the operation of the video processing/driving section 200 will be explained. A digital video signal is supplied to the signal converter 21 . The signal conversion unit 21 extracts a frame synchronization signal Vsync from the supplied video signal, converts the video signal into video signal data of a predetermined number of bits, and outputs the video signal data. The signal conversion section 21 supplies the extracted frame synchronization signal Vsync to the error diffusion section 23, the frame rate control section 24, the limiter section 25, and the subframe data creation section 26, respectively.

Further, the video signal data output from the signal converter 21 is subjected to predetermined signal processing by an error diffusion section 23, a frame rate control section 24, and a limiter section 25, respectively, and is supplied to a subframe data creation section 26.

The flow of processing in the signal conversion section 21, error diffusion section 23, frame rate control section 24, and subframe data creation section 26 according to the second embodiment will be explained using FIG. 16. Here, the description will be made assuming that the video signal input to the signal converter 21 is video signal data having 8 bits.

The signal converter 21 converts the input N-bit video signal data into a signal with a larger number of bits (
Convert to data having the number of bits (M+F+D) bits. Here, the value M is subframe S
When the F number is expressed as a binary number, the value D represents the number of bits interpolated by the error diffusion section 23, and the value F represents the number of bits interpolated by the frame rate control section 24. Note that the value N, the value M, the value F, and the value D are each integers of 1 or more. In the example of FIG. 16, the value N
=8, value D=4, value F=2, and value M=4.

The signal conversion unit 21 performs bit number conversion processing using, for example, a lookup table.
Here, as described above, a display generally has input/output characteristics that follow a gamma curve with a gamma value γ=2.2. Therefore, the video signal output from the video output device 101 is generally corrected using a gamma curve based on a gamma value that is the reciprocal of the gamma value of the display so that linear gradation expression can be obtained when displayed on a display. It is a signal that has been set.

The signal conversion unit 21 sets the input/output characteristics of the projection unit 240 to a reference characteristic, that is, a gamma value γ=2.
Using a lookup table adjusted in advance to approximate the characteristics of the gamma curve of 2,
Converts input video signal data. This conversion process is called calibration.
At this time, the signal converter 21 converts the N-bit video signal data into (M+F+D)-bit video signal data using the lookup table and outputs the converted data. Value N=8, value D=4,
In this example where the value F=2 and the value M=4, the signal converter 21 converts 8-bit video signal data into 10-bit video signal data and outputs the converted signal data.

The video signal data converted into (M+F+D) bits by the signal conversion unit 21 is converted into (M+F) bit data by the error diffusion unit 23 diffusing lower D bit information to surrounding pixels. In this example with value N=8, value D=4, value F=2, value M=4,
For each pixel, the error diffusion section 23 diffuses the lower 4 bits of information to surrounding pixels and quantizes the 10-bit video signal data outputted from the signal conversion section 21 into the upper 6 bits of data.

The error diffusion method is a method of compensating for insufficient gradation by diffusing an error (display error) between a video signal to be displayed and an actual display value to surrounding pixels. In the second embodiment, the lower 4 bits of the video signal to be displayed are the display error, 7/16 of the display error is applied to the pixel to the right of the pixel of interest, 3/16 of the display error is applied to the lower left pixel, and so on. 5/16 of the display error is added to the pixel immediately below, and 1/16 of the display error is added to the pixel at the lower right. This process is performed, for example, for each pixel from left to right within one frame of video, and this process is further performed for each line from top to bottom within one frame of video.

The operation of the error diffusion section 23 will be explained in more detail. The pixel of interest diffuses the error as described above, and the error diffused by the immediately previous pixel of interest is added. Error diffusion section 23
First, the error diffused by the previous pixel of interest is read out from the error buffer and added to the pixel of interest of the input 10-bit video signal data. The error diffusion unit 23 divides the 10-bit pixel of interest to which the value of the error buffer has been added into upper 6 bits and lower 4 bits.

The value of the divided lower 4 bits is as follows, when (lower 4 bits, display error).
(0000, 0)
(0001,+1)
(0010,+2)
(0011,+3)
(0100,+4)
(0101,+5)
(0110,+6)
(0111,+7)
(1000,-7)
(1001, -6)
(1010, -5)
(1011,-4)
(1100, -3)
(1101,-2)
(1110,-1)
(1111, 0)
The display error corresponding to the divided lower 4-bit value is added to the error buffer and stored. Further, a threshold value comparison is performed on the divided lower 4 bit values, and if the value is larger than "1000" in binary notation, "1" is added to the upper 6 bit value. Then, the upper 6 bits of data are output from the error diffusion section 23.

The video signal data converted into (M+F) bits by the error diffusion section 23 is input to the frame rate control section 24. The frame rate control unit 24 controls the display element 22
For the display of one pixel of 0, one period is m frames (m is an integer of 2 or more), on-display is performed for n (n is an integer of m>n>0) frames of that period, and the remaining (m -n) Frame control processing is performed to artificially display gradation by off-displaying the frame.

In other words, the frame rate control process is a process that uses screen rewriting and retinal afterimage effects to create a pseudo intermediate gradation. For example, by rewriting a certain pixel alternately with a gradation value of "0" and a gradation value of "1" every frame, the human eye can see that the pixel has a gradation value of "0" and a gradation value of "1". This will appear as a pixel with an intermediate gradation value of 1. and,
By controlling such alternating rewriting of gradation value "0" and gradation value "1" as one set of 4 frames, for example, the gradation value "0" and gradation value "1" can be changed. In between, three levels of gradation can be simulated.

The frame rate control unit 24 includes a frame rate control table shown in FIG. 17. The frame rate control unit 24 further includes a frame counter that counts frames based on, for example, a frame synchronization signal Vsync. In the example of FIG. 17, the frame rate control table consists of a 4x4 matrix (referred to as a small matrix) in which the value "0" or "1" is specified in each square, and a 4x4 matrix (larger matrix). They are arranged in a matrix (called a matrix).

Each column of the large matrix is designated by the value of the lower two bits of the counter value of the frame counter. Further, each row of the large matrix is specified by the value of the lower two bits of the 6-bit video signal data input to the frame rate control section 24. Further, each column and each row of each small matrix is specified based on position information of the pixel within the display area, that is, the coordinates of the pixel. More specifically, each column of each small matrix is specified by the value of the lower two bits of the X coordinate of the pixel, and each row is specified by the value of the lower two bits of the Y coordinate of the pixel.

The frame rate control unit 24 specifies the position in the frame rate control table from the value of the lower F bit of the supplied (M+F) bit video signal data, the pixel position information, and the frame count information, and determines the position in the frame rate control table. Value at position (value “0” or value “
1'') is added to the upper M bits. As a result, (M+F) bits of video signal data are converted into M
Convert to bit data.

In this example where the value F=2 and the value M=4, the 6-bit video signal data output by the error diffusion section 23 is input to the frame rate control section 24. The frame rate control unit 24 acquires the value "0" or the value "1" from the frame rate control table based on the information on the lower two bits of this video signal data, the position information in the display area, and the frame counter information. , the obtained value is added to the value of the upper 4 bits separated from the 6 bits of the input video signal data.

More specifically, the frame rate control unit 24 divides the input 6-bit video signal data (pixel data) into upper 4-bit data and lower 2-bit data. The frame rate control unit 24 uses the lower 2 bits of data obtained by dividing, the lower 2 bits of the X coordinate and the lower 2 bits of the Y coordinate in the display area of the pixel, and the lower 2 bits of the count value of the frame counter. Using a total of 8 bits of values, specify the position in the large matrix and small matrix of the frame rate control table in FIG.
Obtain the value "0" or the value "1" specified by the specified position. The frame rate control unit 24 adds the acquired value "0" or "1" to the upper 4 bits of data separated from the input video signal data, and outputs the result as 4-bit video signal data.

In this way, the frame rate control unit 24 controls pixel on/off for each gradation in units of pixel blocks. Thereby, it is possible to express an additional gradation in a pseudo manner between two consecutive gradations.

Referring to FIG. 14, 4-bit video signal data output from frame rate control section 24 is supplied to limiter section 25. The limiter section 25 limits the maximum value of the gradation value of the supplied video signal data to "12". The maximum value of the gradation value in the limiter section 25 is "12"
The video signal data limited to 1 is supplied to the subframe data creation section 26. The subframe data creation unit 26 uses the drive gradation table 27 to convert the supplied video signal data into 12-bit data.

Further, the subframe data generation unit 26 generates a subframe synchronization signal SFsync based on the supplied frame synchronization signal Vsync. The subframe data creation unit 26
The frame synchronization signal Vsync and the subframe synchronization signal SFsync are supplied to the memory control section 28 and the drive control section 31, as well as to the light source control section 230.

FIG. 18 shows an example of the drive gradation table 27 applicable to the second embodiment. In FIG. 18, similarly to FIG. 3 described above, each column has subframes SF1, SF2,
..., SF12. Among these, subframe SF1 is the first subframe of the frame period, and subframe SF12 is the last subframe of the frame period. Furthermore, in FIG. 18, the gradation value of each row increases from 0 to 1 from top to bottom. Gradation value “
The gradation value "0" is the lowest (dark) gradation, and the gradation value "12" is the highest (bright) gradation.

In the second embodiment, contrary to the example of the first embodiment shown in FIG. In the subframe, the pixel is controlled to be on. In FIG. 18, a hatched cell with a value of "1" indicates that a pixel is controlled to be in an on state, and a cell with a value of "0" indicates that a pixel is controlled to be in an off state. In this way, the driving gradation table 27 stores values indicating pixel on/off control in association with each subframe SF1 to SF12 and gradation value.

In this way, in the second embodiment as well, similar to the first embodiment described above, subframes for performing on and off control are allocated in advance for each gradation.

The subframe data creation unit 26 refers to the drive gradation table 27 according to the video signal data, and converts the data of each pixel into data with a value of "0" or "1" (hereinafter referred to as "0" or "1" data) for each subframe SF.
0/1 data) to create subframe data.

For example, with reference to FIG. The pixels are converted into 0/1 data of values "0", "0", "0", "0", and "0" in subframe SF1, and are used as subframe data of subframe SF1. Each pixel is converted into 0/1 data of values "0", "0", "0", "0", and "1" respectively in subframe SF4, and is used as subframe data of subframe SF4. . Further, in the subframe SF12, the data are converted into 0/1 data with the values "1", "1", "0", "1", and "1", respectively, and are used as the subframe data of the subframe SF12.

FIG. 19 is a time chart showing an example of control according to the second embodiment. The time chart in FIG. 19 corresponds to the time chart in FIG. 5 described above, and includes drive timing for the display element 220 and drive timing for the light source 210. 19(a) and 19(b) show the frame synchronization signal Vsync and the subframe synchronization signal S, respectively.
An example of Fsync is shown. In the example of FIG. 19(b), corresponding to FIG. 18 described above, one frame period is divided into 12 subframes SF1 to SF12, which is one less than the number of gradations.

FIG. 19C shows an example of the drive timing of the display element 210, and FIG. 19D shows an example of the transfer timing of the video signal data to the pixel electrode section 2203. Moreover, FIG. 19(e) shows an example of light amount control of the light source 210.

In FIG. 19(c), the period WC includes all the pixel circuits 2 included in the pixel electrode section 2203.
210 shows a data transfer period during which video signal data for each subframe SF is transferred. Period D
C indicates a driving period when driving the pixel circuit 2210. A period WC and a period DC are arranged in one subframe SF. The period WC starts corresponding to the start timing of the subframe SF, and after the end of the period WC, the period DC starts. The period DC ends corresponding to the end timing of the subframe SF.

Within one frame period, subframes SF1, SF2, ..., SF1 from the beginning in the time axis direction
1, each subframe SF1, SF2,... from the frame buffer 29 in the order of SF12.
Subframe data of SF11 and SF12 is read out and transferred to each pixel circuit 2210 in period WC. The transferred subframe data is held in the sample/hold section 16 of each pixel circuit 2210, respectively.

As an example, the data transfer unit 30 transfers subframe data to the source driver 33 line by line under the control of the drive control unit 31. The source driver 33 includes a drive control section 31
For example, the transferred subframe data is transferred to each data line D0, D1, ..., D
Write and hold each pixel in the register corresponding to n. Here, the data held for each pixel is the value "0" or the value "
1” becomes 0/1 data.

Furthermore, under the control of the drive control unit 31, the gate driver 34 sequentially selects the row selection lines W0, W1, . As a result, the 0/1 data of each pixel held in the source driver 33 is transferred to the row selection lines W0, W1
, . . . Wm is acquired and held in the sample/hold unit 16 of each pixel circuit 2210 selected by Wm. As a result, 0/1 data of the pixel is held in the sample/hold section 16 in all the pixel circuits 2210 included in the pixel electrode section 2203 within the period WC.

In period DC, all the pixel circuits 2210 included in the pixel electrode section 2203 are driven.
Drive control of the pixel circuit 2210 will be described with reference to FIG. 15. Each pixel circuit 2210
During the period WC during which 0/1 data is transferred to
Regardless of the data value, it is necessary to put the pixel in a blanking state. Therefore, under the control of the drive control section 31, the voltage control section 32 sets the voltage V0, the voltage V1, and the common voltage Vcom to the same potential (eg, ground potential) during the period WC.

When the period WC ends, a period DC, which is a driving period, starts. Under the control of the drive control unit 31, the voltage control unit 32 drives each pixel circuit 2210 in each of periods DC#1 and DC#2, which are obtained by equally dividing the period DC. In period DC#1, the voltage control unit 32 sets the voltage V1 to the saturation voltage Vw, and sets the voltage V0 and the common voltage Vcom to the ground potential. Also,
In the period DC#2, the voltage control unit 32 sets the voltage V1 to the ground potential, contrary to the period DC#1.
Voltage V0 and common voltage Vcom are set to saturation voltage Vw.

In the pixel circuit 2210, when the 0/1 data held in the sample and hold section 16 has the value "0", the voltage selection circuit 17 selects the voltage V0 as the voltage to be applied to the pixel electrode 2204. In period DC#1, the voltage Vpe of the pixel electrode 2204 and the common voltage Vcom applied to the counter electrode 2201 are each at the ground potential. Therefore, the voltage applied to the liquid crystal layer 2202 becomes 0 [V], and the driving state of the liquid crystal layer 2202 becomes a blanking state (off state).

In the pixel circuit 2210, when the 0/1 data held in the sample/hold unit 16 has the value “1”, the voltage selection circuit 17 selects the voltage V1 as the voltage to be applied to the pixel electrode 2204. In period DC#1, the voltage Vpe of the pixel electrode 2204 becomes the saturation voltage Vw, and the common voltage Vcom applied to the counter electrode 2201 becomes the ground potential. Therefore, the voltage applied to the liquid crystal layer 2202 becomes a positive saturation voltage Vw with respect to the potential of the counter electrode 2201, and the liquid crystal layer 2202 enters the driving state (on state). Furthermore, in period DC#2, the pixel electrode 220
4, the voltage Vpe is the ground potential, and the common voltage Vcom applied to the counter electrode 2201 is the saturation voltage Vw.
(saturation voltage + Vw), and the voltage applied to the liquid crystal layer 2202 becomes a negative saturation voltage Vw (saturation voltage - Vw) with the potential of the counter electrode 2201 as a reference, and the liquid crystal layer 2202 enters the driving state (on state). Become.

By applying voltages with equal absolute values and different positive and negative values (saturation voltage +Vw and -Vw) to the liquid crystal layer 2202 for the same period of time, the voltage applied to the liquid crystal layer 2202 becomes 0 [v] on average over a long period of time, preventing burn-in. can do.

Returning to the description of FIG. 19, FIG. 19E shows an example of light amount control of the light source 210 by the light source control unit 230. As explained using FIG. 18, in the second embodiment, subframe SF1
2 is a subframe in which pixels are controlled to be turned on at the lowest gradation excluding black display (gradation value "0"), and in this subframe SF12, each gradation except for the gradation value "0" is controlled. Pixels are commonly set to a driving state (ON control) in all modes. Therefore, the light source control unit 230 reduces the light intensity of the light source 210 by, for example, 50% in the subframe SF12 at the rear end of the frame period, according to the frame synchronization signal Vsync and the subframe synchronization signal SFsync supplied from the subframe data creation unit 26. Control is performed to reduce the light intensity by a ratio, and in the other subframes SF1 to SF11, the light intensity of the light source 210 is controlled to 100%.

In this way, even if the light source control is performed to reduce the light intensity of the light source 210 at the rear end side of the frame period, as in the first embodiment described above, the image based on the video signal of the input value in the low gradation range is The display is closer to the intended image than the existing technology, and the display quality can be improved compared to the existing technology.

16 Sample/hold section 17 Voltage selection circuit 21 Signal conversion section 23 Error diffusion section 24 Frame rate control section 26 Subframe data creation section 27 Drive gradation table 28 Memory control section 29 Frame buffer 30 Data transfer section 31 Drive control section 32 Voltage Control unit 33 Source driver 34 Gate driver 100, 100a, 100b Projection device 101 Video output device 102 Projection target medium 110 Video processing unit 111 Drive unit 112 Subframe creation unit 113, 230 Light source control unit 120, 210 Light source 121, 220 Display element 122,240 Projection section 200 Image processing/drive section 2201 Counter electrode 2202 Liquid crystal layer 2203 Pixel electrode section 2204 Pixel electrode 2210 Pixel circuit

Claims (6)

a division period creation unit that creates a division period by dividing the frame period of the video signal;
a light source control unit that drives a light source that irradiates light to a display element whose on and off are controlled for each pixel according to the video signal according to the division period assigned in advance for each gradation;
The light source control section includes:
The first light amount in the first division period corresponding to the lowest gradation excluding black display is set to be lower than the second light amount in the second division period other than the first division period, and All gradations except display include the first light amount,
In all gradations except for black display, the minimum resolution of each gradation is smaller than 1, where the case where the first light amount and the second light amount are the same is set as 1, and becomes smaller as the gradation becomes smaller. A light source driving device for a liquid crystal display device, characterized in that a monotonically decreasing curve is formed , and the monotonically decreasing curve is changed by controlling the first light amount. The light source control section includes:
The light intensity of the light source is further controlled to the first light intensity in one or more continuous division periods from the first division period among the second division periods.
The light source driving device according to claim 1, characterized in that: a division period creation step of creating a division period by dividing the frame period of the video signal;
a light source control step of driving a light source that irradiates light to a display element whose on and off are controlled for each pixel in accordance with the video signal according to the division period assigned in advance for each gradation;
Equipped with
The light source control step includes:
Of the first division period corresponding to the lowest gradation excluding black display and the second division period other than the first division period, at least the first light amount in the first division period, The light amount is lower than the second light amount of the second division period, and the first light amount is included in all gradations except for black display,
In all gradations except for black display, the minimum resolution of each gradation is smaller than 1, where the case where the first light amount and the second light amount are the same is set as 1, and becomes smaller as the gradation becomes smaller. forming a monotonically decreasing curve, and changing the monotonically decreasing curve by controlling the first light amount;
A method for driving a light source of a liquid crystal display device, characterized in that: a light source and
a display element that modulates the light emitted from the light source according to a video signal;
a division period creation unit that creates a division period by dividing the frame period of the video signal;
a driving unit that controls on and off of each pixel of the display element according to the video signal according to the division period assigned in advance for each gradation;
a light source control unit that drives the light source;
Equipped with
The light source control section includes:
Of the first division period corresponding to the lowest gradation excluding black display and the second division period other than the first division period, at least the first light amount in the first division period, The light amount is lower than the second light amount of the second division period, and the first light amount is included in all gradations except for black display,
In all gradations except for black display, the minimum resolution of each gradation is smaller than 1, where the case where the first light amount and the second light amount are the same is set as 1, and becomes smaller as the gradation becomes smaller. forming a monotonically decreasing curve, and changing the monotonically decreasing curve by controlling the first light amount;
A liquid crystal display device characterized by: The light source control section includes:
The light intensity of the light source is further controlled to the first light intensity in one or more continuous division periods from the first division period among the second division periods.
5. The liquid crystal display device according to claim 4. The drive unit includes:
Further controlling on and off of the pixels for each gradation and in units of blocks of the pixels.
The liquid crystal display device according to claim 4 or claim 5, characterized in that: