JP2012103356A - Liquid crystal display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display unit capable of preventing the occurrence of double image phenomenon when framed frequency is increased by displaying an image of the same frame twice without inserting an interpolated image.SOLUTION: A signal processing section 101 of a liquid crystal display unit 100 transforms an input signal into a double-speed re-writing signal. A driver 102 has a sub-frame data creating section 26 that creates sub-frame data based on the double-speed re-writing signal, in which one frame has 2S sub-frames (SF) and all of the sub-frames are configured of a step-bit pulse, SF1 becomes a drive state when driving gradation is 1, SF1 and SF(S+1) become a drive state when driving gradation is 2, SF1, SF2 and SF(S+1) become a drive state when driving gradation is 3, and then, the number of sub-frames that become the drive state increases alternately between SF1 and SF(S) and between SF(S+1) and SF(2S), and toward the rear of sub-frame that is already in the drive state.

Description

  The present invention relates to a liquid crystal display device that converts an input video signal to a frame frequency higher than the frame frequency of the video signal and displays it on a display unit of a liquid crystal display element.

  A double-speed frame interpolation method is widely adopted for the purpose of improving moving image performance in liquid crystal display devices. In the liquid crystal display device, the display of the current image is continuously held until the image of the next frame is rewritten. When the display image is instantaneously rewritten to the next frame image, the images of the previous and subsequent frames are observed simultaneously due to the afterimage effect of the human eye. As a result, it is recognized as blurring of the moving image. The double-speed frame interpolation method is a method for predicting, creating, and inserting an intermediate image from images of previous and subsequent frames, with a frame period, for example, 60 Hz being doubled to 120 Hz as a countermeasure against moving image blur.

  Patent Document 1 generally discloses the following contents. Motion between the frames of the video signal is detected by the motion detection circuit, and the interpolation circuit forms an interpolated video based on the detected motion vector. The video signal and the interpolated video are written in the image memory. The image memory reads out the video signal and the interpolated video at a frequency twice as high as the writing frequency, and outputs a video signal with the frequency doubled and the interpolated video inserted.

JP 2006-165974 A

  The double-speed frame interpolation method is an effective technique for improving moving images. However, since a new image is artificially created, there is also a demand for viewing an image without interpolation. Therefore, when a method of increasing the frame frequency twice, displaying an image of the same frame twice, and setting the frame frequency to 120 Hz in a pseudo manner, there is a problem that a double image phenomenon occurs.

  The driving method of the liquid crystal display element used in the liquid crystal display device is an analog method in which the voltage value applied to the pixel is a continuous analog value, and the voltage applied to the pixel is binary, and the luminance of the image There is a digital method for controlling an effective voltage value applied to a pixel of a liquid crystal by changing a time width of an applied voltage corresponding to (gradation). In the digital method, it is common to use a subfield method in order to obtain a halftone. Even when the sub-frame method is used in the digital method, the above-described problems are the same.

  Therefore, the present invention provides a liquid crystal display device capable of preventing the occurrence of a double image phenomenon when an image of the same frame is displayed twice without inserting an interpolated image and the framed frequency is increased. With the goal.

  In order to solve the above-described problems of the prior art, the present invention includes a signal processing unit (101) that converts an input signal into a signal that is twice the frame frequency and the same frame twice, and the signal processing unit. Based on the signal to be converted, 2S subframes per frame and all subframes are constituted by step bit pulses. When the driving gradation is 1, the first subframe is in the driving state, and the driving gradation Is 1, the first subframe and the (S + 1) th subframe are in the driving state, and when the driving gradation is 3, the first, second, and (S + 1) th subframe are in the driving state, and the number of gradations is As the number of subframes increases, the number of subframes that are driven increases alternately between the first and Sth subframes and between the (S + 1) th and 2Sth subframes. A driving device (102) having a sub-frame data generating unit (26) for generating sub-frame data by a driving gradation table (27) which increases toward the rear of the sub-frame, and is driven by the driving device. A liquid crystal display element (6), an illumination optical system (1) for making illumination light incident on the liquid crystal display element, and a projection lens (11) for projecting the modulated light emitted from the liquid crystal display element. A liquid crystal display device is provided.

  In addition, the signal processing unit (101) that converts the input signal into a signal that is twice the frame frequency and the same frame twice, and 2S signals per frame based on the signal converted by the signal processing unit. All subframes are composed of step bit pulses, and when the driving gradation is 1, the last subframe is in the driving state, and when the driving gradation is 2, the last subframe and the Sth subframe When the driving gradation is 3, the last and (2S-1) th and Sth subframes are in the driving state, and the number of subframes that are in the driving state as the number of gradations increases ( Driving that increases alternately between the (S + 1) th and last subframes and between the 1st and Sth subframes and increases toward the front of the subframe already in the driving state. A driving device (102) having a sub-frame data generating unit (26) for generating sub-frame data by means of a tone table (27), a liquid crystal display element (6) driven by the driving device, and illuminating the liquid crystal display element Provided is a liquid crystal display device comprising an illumination optical system (1) for making light incident and a projection lens (11) for projecting modulated light emitted from the liquid crystal display element.

  In the above configuration, the look-up table unit (21) for converting the signal of the number of bits N output from the signal processing unit into data of (M + F + D) bits larger than N by performing inverse gamma correction and linear interpolation; An error diffusion unit (23) that converts (M + F + D) bit data processed by the lookup table unit into (M + F) bit data by error diffusion processing, and (M + F) bit data processed by the error diffusion unit And a frame rate control unit (24) for converting the data into M-bit data by frame rate control, and the sub-frame data creation unit (26) is based on the M-bit data processed by the frame rate control unit. The subframe data may be created.

  In addition, the signal processing unit (101) that converts the input signal into a signal that is twice the frame frequency and the same frame twice, and 2S signals per frame based on the signal converted by the signal processing unit. When the driving gradation is 1, the first subframe is in the driving state, and when the driving gradation is 2, the first subframe and the (S + 1) th subframe are in the driving state. Is 3, the first and second subframes (S + 1) are in a driving state, and the number of subframes that are in a driving state every time the number of gradations increases is between the first and Sth subframes, and It increases alternately between the (S + 1) -th and 2S-th sub-frames, and increases after the sub-frame already in the driving state, and the liquid crystal light for the input video signal data A driving device (1020) having a sub-frame data generating unit (26) for generating sub-frame data based on a driving gradation table in which the driving period for each sub-frame is changed so that the force has an inverse gamma characteristic; A liquid crystal display element (6) driven by the illumination optical system (1) for making illumination light incident on the liquid crystal display element, a projection lens (11) for projecting modulated light emitted from the liquid crystal display element, A liquid crystal display device is provided.

  Furthermore, a signal processing unit (101) that converts an input signal into a double-speed double writing signal, and 2S subframes per frame based on the signal converted by the signal processing unit, drive gradation When the driving gradation is 2, the last subframe and the Sth subframe are in the driving state, and when the driving gradation is 3, the last subframe and the (2S-1) th are driven. The S-th subframe is in the drive state, and the number of subframes in the drive state each time the number of gradations increases is between the (S + 1) th and last subframes, and the first and S-th subframes. Each subframe increases so that the light output of the liquid crystal with respect to the input video signal data has an inverse gamma characteristic while increasing alternately before the subframe that is already driven. A driving device (1020) having a sub-frame data generating unit (26) for generating sub-frame data based on driving gradation tables having different driving periods; a liquid crystal display element (6) driven by the driving device; Provided is a liquid crystal display device comprising: an illumination optical system (1) for making illumination light incident on a liquid crystal display element; and a projection lens (11) for projecting modulated light emitted from the liquid crystal display element. .

  In the above configuration, a signal conversion unit (22) that linearly interpolates a signal of N bits output from the signal processing unit and converts it into (M + F + D) bit data larger than N, and is processed by the signal conversion unit. An error diffusion unit (23) that converts (M + F + D) -bit data into (M + F) -bit data by error diffusion processing; and (M + F) -bit data processed by the error diffusion unit is converted to M bits by frame rate control. A frame rate control unit (24) for converting the data into the subframe data, and the subframe data creation unit (26) creates the subframe data based on the M-bit data processed by the frame rate control unit. You may comprise.

  According to the present invention, there is provided a liquid crystal display device capable of preventing the occurrence of a double image phenomenon when an image of the same frame is displayed twice without inserting an interpolated image and the framed frequency is increased. Can do.

It is a schematic block diagram which shows the liquid crystal display device using a reflection type liquid crystal display element. It is a figure which shows the drive circuit structure of each pixel in the reflection type liquid crystal display element of a digital drive. It is a figure which shows the relationship between the input voltage of the reflection type liquid crystal display element in 1st Embodiment, and the intensity | strength of output light. It is the schematic which shows the signal processing part for carrying out the double speed interpolation process or double speed double writing of the input signal. 1 is a block diagram showing a drive circuit (drive device) according to a first embodiment of the present invention. It is a figure for demonstrating the gradation expression in 1st Embodiment. It is a figure which shows the drive pattern in the time of double speed interpolation mode and double speed double writing mode in 1st Embodiment. It is a figure which shows the drive gradation table in the double speed interpolation mode in 1st Embodiment. It is a figure which shows the drive gradation table in the double speed double writing mode in 1st Embodiment. It is a figure which shows the error diffusion figure in 1st Embodiment. It is a figure which shows the error diffusion flow in 1st Embodiment. It is a figure which shows the frame rate control flow in 1st Embodiment. FIG. 5 is a diagram showing a frame rate control table in the first embodiment. It is a figure which shows the signal processing in 1st Embodiment. It is a figure which shows the polarity inversion drive of the reflection type liquid crystal display element in 1st Embodiment. It is the figure which compared typically the grade of the generation | occurrence | production of the double image in double speed interpolation mode and double speed double writing mode. It is a figure which shows a mode that the image which a 1 dot width image moves 2 dots to the right every 1/60 second is displayed in double speed interpolation mode and double speed double writing mode. FIG. 10 is a diagram showing temporal changes in image light when the driving gradation table is as shown in FIGS. 8 and 9 in the double speed double writing mode. It is a figure explaining the generation | occurrence | production mechanism of the horizontal electric field in a reflection type liquid crystal element. It is a figure explaining that a horizontal electric field is disperse | distributed equally by frame rate control. It is a figure which shows the drive gradation table in 2nd Embodiment. It is a block diagram which shows the drive circuit (drive device) which concerns on 3rd Embodiment. In a 3rd embodiment, it is a figure showing that the brightness for every drive gradation is on the line of gamma 2.2 by adjusting each sub-frame period.

<First Embodiment>
Hereinafter, an image display device and a driving method thereof according to the present invention will be described with reference to the accompanying drawings. In the following, a projection type display device provided with an active matrix type reflective liquid crystal display element as a display panel will be described as an example. First, schematic configurations of the projection display device and the reflective liquid crystal display element will be described.

  FIG. 1 is a schematic configuration diagram showing a liquid crystal display device using a reflective liquid crystal display element. The liquid crystal display device generally includes a reflective liquid crystal display element 6, a polarization beam splitter 5 (hereinafter referred to as PBS), and a projection lens 13. The reflective liquid crystal display element 6 has a structure in which a liquid crystal 9 is sealed between a counter electrode (also referred to as a transparent electrode) 10 and a pixel electrode 8.

  Light 2 including S-polarized light 3 and P-polarized light 4 emitted from the illumination optical system 1 enters the PBS 5. Polarized light is separated by PBS5. The S-polarized light 3 is reflected by the polarization separation surface of the PBS 5 and proceeds to the reflective liquid crystal display element 6 side. P-polarized light is transmitted through the polarization separation surface of PBS. The liquid crystal 9 of the reflective liquid crystal display element 6 modulates incident S-polarized light according to the voltage applied between the pixel electrode 8 and the counter electrode 10 by the pixel circuit 7. The S-polarized light incident on the counter electrode 10 is modulated in the process from being reflected by the pixel electrode 8 and being emitted from the counter electrode 10, and is emitted from the counter electrode 10 as light composed of P-polarized light and S-polarized light. In the light emitted from the counter electrode 10, only the P-polarized component, which is modulated light, passes through the PBS 5, and the S-polarized component is reflected by the PBS 5. The P-polarized light that has passed through the PBS 5 is emitted by the projection lens 11, and the emitted light 12 is projected on the screen 13 to display an image. The intensity of the output light described later refers to the illuminance of the output light measured on the screen 13.

  FIG. 2 is a diagram showing the drive circuit configuration of each pixel in the digitally driven reflective liquid crystal display element 6. Each pixel of the reflective liquid crystal display element 6 has a structure in which a liquid crystal 9 is sandwiched between a pixel electrode 8 and a counter electrode 10. A pixel circuit 7 indicated by a broken line includes a sample hold unit 16 and a voltage selection circuit 17. The sample hold unit 16 is composed of an SRAM structure flip-flop. The sample hold unit 16 is connected to the column data line D and the row selection line W. The output of the sample hold unit 16 is connected to the voltage selection circuit 17. The voltage selection circuit 17 is connected to the blanking voltage line V0 and the drive voltage line V1. The voltage selection circuit 17 is connected to the pixel electrode 8 and applies a predetermined voltage to the pixel electrode 8. The value of the voltage of the counter electrode 10 is called a common voltage Vcom.

  FIG. 3 is a diagram showing the relationship between the input voltage of the reflective liquid crystal display element 6 and the intensity of output light in the following embodiments. In FIG. 3, the horizontal axis represents the input voltage, and shows the potential difference between the pixel electrode 8 and the counter electrode 10, that is, the driving voltage of the liquid crystal 9. The vertical axis indicates the intensity of output light emitted from the liquid crystal 9. The voltage at which the intensity of the output light emitted from the liquid crystal 9 starts to increase is the dark value voltage Vth. When the voltage is 0 (for example, both the pixel electrode 8 and the counter electrode are GND), the intensity of the output light is small and the state is black (blanking voltage), and the voltage at which the output light begins to saturate is the saturation voltage Vw (white). Level.)

  FIG. 4 is a schematic diagram showing a signal processing unit 101 for performing double speed interpolation processing or double speed double writing processing on an input signal. The input signal and the signal delayed by one frame in the frame memory are input to the motion vector detection circuit. The motion vector detection circuit detects the motion vector of the moving image from the input current frame signal and the signal delayed by one frame, and sends the motion vector of the moving image to the interpolated video signal generation circuit. The interpolated video signal generation circuit generates a motion-compensated interpolation frame to be inserted between the current frame signal and the one-frame delayed signal using the current frame signal, the one-frame delayed signal, and the motion vector. .

  The current frame signal and the interpolation frame signal are written to the frame memory by a write timing control signal. The write address generation circuit has a timing control counter for writing video signals to the frame memory. The write timing control signal calculated from the horizontal sync signal (Hsync) and vertical sync signal (Vsync) of the input signal is stored in the frame memory. Output to the control interface. The frame memory outputs a video signal in the double speed interpolation mode or the double speed double writing mode designated by the selection circuit based on the read timing control signal, and is sent from the selection circuit to the drive device (drive circuit) 102 at the subsequent stage. . The read generation circuit has a timing control counter for reading the video signal written to the frame memory, and is calculated from the horizontal synchronization signal (2HSync) and the vertical synchronization signal (2VSync) having a frequency twice that of the input signal. The read timing control signal is output to the control interface of the frame memory. When interpolation is performed, the current frame signal and the interpolation frame signal are alternately read out. When interpolation is not performed, the current frame signal is output twice in succession.

  FIG. 5 is a block diagram showing a drive circuit (drive device) according to the first embodiment of the present invention. FIG. 6 is a diagram for explaining gradation expression in the first embodiment. FIG. 6 shows an example of gradation expression in each process unit when the number of bits of input video signal data is 8 bits. FIG. 7 is a diagram showing drive patterns in the double speed interpolation mode and the double speed double writing mode in the first embodiment. FIG. 8 is a diagram showing a drive gradation table in the double speed interpolation mode in the first embodiment. FIG. 9 is a diagram showing a drive gradation table in the double speed double writing mode in the first embodiment. FIG. 10 is a diagram showing an error diffusion flow in the first embodiment. FIG. 11 is a diagram showing an error diffusion diagram in the first embodiment. FIG. 12 is a diagram showing a frame rate control flow in the first embodiment. FIG. 13 is a diagram showing a frame rate control table in the first embodiment.

  In FIG. 5, the video signal data inputted with N bits is converted into (M + F + D) bit data larger than N by the look-up table unit 21. Here, M is the number of bits when the number of subframes is expressed in binary, D is the number of bits to be interpolated by the error diffusion processing unit 23, and F is the number of bits to be interpolated by the frame rate control unit 24. . N, M, F, and D are integers.

  In the example of FIG. 6, the number of bits of the input video signal data is 8 bits (N = 8), the number of bits to be interpolated by the error diffusion processing unit 23 is 4 bits (D = 4), and the frame rate control unit 24 The number of bits to be interpolated is set to 2 bits (F = 2). When the number of subframes is expressed in binary, the number of bits is 4 bits (M = 4), and the drive gradation is 12 (not including black).

  Here, the operation of the lookup table unit 21 will be described. Generally, video signals are subjected to gamma correction. On the image display device side, it is necessary to perform inverse gamma correction processing on the video signal that has been subjected to gamma correction to restore the linear gradation. Inverse gamma correction is correction in which the output is X raised to the power of 2.2 with respect to the input X. In this case, the output characteristic is expressed as “gamma 2.2” below. The look-up table unit 21 has a function of realizing a liquid crystal display device having an output characteristic of gamma 2.2 by converting input / output characteristics of the reflective liquid crystal display element 6. The look-up table is adjusted in advance so that the 10-bit output has an arbitrary output characteristic (for example, gamma 2.2). For example, in the first embodiment, images by driving each of the twelve driving gradations (not including black) shown in FIGS. 8 and 9 are projected by the liquid crystal display device shown in FIG. Measure with an illuminometer. By linearly interpolating the illuminance between the respective drive gradations with 6 bits (M + D = 6) (64 gradations), illuminance data for each gradation of 0 to 768 is predicted. It is assumed that 256 pieces of data having arbitrary output characteristics (for example, gamma 2.2) are selected from those illuminance data and are stored as a lookup table in advance.

  The lookup table unit 21 has a lookup table of 256 × 10 bits (that is, “2 to the 8th power” gradation x (4 + 2 + 4) bits). Here, the “2 to the 8th power” gradation x (4 + 2 + 4) bit means that N = 8, M = 4, F = 2, and D = 4 with respect to the “2 to the Nth power” gradation x (M + F + D) bit. Is equivalent to the value of. The look-up table unit 21 converts the input 8-bit image data into 10-bit data and outputs it.

  Returning to FIG. 5, the video signal data converted into (M + F + D) bits by the look-up table unit 21 is (M + F) bit data by diffusing the lower D bits of information to surrounding pixels by the error diffusion unit 23. Is converted to In the example of FIG. 6, the converted 10-bit data is output by the error diffusion unit 23 by diffusing the lower 4 bits of information to surrounding pixels, quantizing the data into upper 6 bits.

  The error diffusion method is a method of compensating for the lack of gradation by diffusing an error (display error) between a video signal to be displayed and an actual display value to surrounding pixels. In the first embodiment, the lower 4 bits of the video signal to be displayed are set as display errors, and as shown in FIG. 10, 7/16 of the display error is displayed on the right adjacent pixel and 3/16 of the display error is displayed on the lower left pixel. , 5/16 of the display error is added to the pixel immediately below, and 1/16 of the display error is added to the pixel on the lower right.

  The operation of the error diffusion unit 23 will be described in more detail with reference to FIG. A video signal at a certain coordinate diffuses an error as described above, and an error obtained by diffusing the previous video is added. In the input 10-bit data, first, an error in which the previous image is diffused is added by the error buffer. The input video signal data is divided into upper 6 bits and lower 4 bits after the error buffer value is added.

The divided lower 4 bits are shown below. The value on the right is a display error.
Lower 4 bits Display error 0000 0
0001 +1
0010 +2
0011 +3
0100 +4
0101 +5
0110 +6
0111 +7
1000-7
1001-6
1010-5
1011 -4
1100-3
1101 -2
1110 -1
1111 0

  The display error corresponding to the divided lower 4-bit value is added to the error buffer and held as shown in FIG. Also, a threshold comparison is performed on the divided lower 4-bit value, and if the value is larger than 1000 (the row after the row where the value on the left is 1000), 1 is added to the upper 6-bit value. Is added. Then, the upper 6-bit data is output from the error diffusion unit.

  Returning to FIG. 5, the video signal data converted into (M + F) bits by the error diffusion unit 23 is input to the frame rate control unit 24. The frame rate control unit 24 includes a frame rate control table. The frame rate control unit 24 specifies the position in the frame rate control table from the lower F bit value, the pixel position information, and the frame count information, and the value (1 or 0, hereinafter 0/1) Are added to the upper M bits and converted to M bit data. Here, the frame rate control method refers to an m (m: m ≧ 2, natural number) frame as one period for display of one pixel of the display element, and n (n: n> 0, m> n) of the period. In this method, pseudo gradation is displayed by performing on display in the (natural number) frame and performing off display in the remaining (mn) frames.

  In the example of FIG. 6, the 6-bit data output by the error diffusion unit 23 is input to the frame rate control unit 24. The frame rate control unit 24 derives a value of 0/1 from the frame rate control table from the lower 2 bits information, the position information in the display area, and the frame counter information, and the upper 4 bits separated from the input 6 bits. Add to the value of the bit.

  The operation of the frame rate control unit 24 will be specifically described with reference to FIG. The input 6-bit data is divided into upper 4 bits and lower 2 bits. The lower 2 bits of the input 6-bit data, the position information in the pixel display area (that is, the lower bits of the X coordinate and the lower 2 bits of the Y coordinate, which are coordinate data), and the lower 2 bits of the frame counter A value of “0” or “1” shown in the frame rate control table of FIG. 13 is specified using a total of 8 bits. The specified value “0” or “1” is added to the upper 4 bits of data and output as 4 bits of data.

  Returning to FIG. 6, the 4-bit data output from the frame rate control unit 24 is limited to 12 which is the maximum value of the drive gradation by the limiter unit 25 shown in FIG. At 26, the data is converted into 12-bit data to be transferred to the reflective liquid crystal display element 6. The drive gradation table 27 is used for conversion to 12-bit data. Thereafter, the number of subframes created by the subframe data creation unit 26 (here, 12) is set to 2S. In the example of FIG. 6, 2S = 12.

  Returning to FIG. 5, the 12-bit data output from the subframe data creation unit 26 is stored in the frame buffer 29 divided for each subframe by the memory control unit 28. The frame buffer 29 has a double buffer structure. While data is being stored in the frame buffer 0, the data in the frame buffer 1 is transferred to the reflective liquid crystal display element 6 via the data transfer unit. In the next frame, the data in the frame buffer 0 stored during the previous frame period is transferred to the liquid crystal display element 6 via the data transfer unit 30, and the subframe data of the video signal data input to the frame buffer 1. Output data from the creation unit 26 is stored.

  The drive control unit 31 controls processing timing for each subframe, and performs a transfer instruction to the data transfer unit 30 and control of the gate driver 34. The data transfer unit 30 instructs the memory control unit 28 in accordance with an instruction from the drive control unit 31, receives the designated subframe data from the memory control unit 28, and transfers the data to the source driver 33. Each time the source driver 33 receives data for one line from the data transfer unit 30, it simultaneously transfers the data to the corresponding pixel circuit 7 of the reflective liquid crystal display element 6 using the column data lines D0-Dn. At this time, the gate driver 34 activates the row selection line Wy of the row designated by the vertical start signal (VST) / vertical shift clock signal (VCK) from the drive control unit 31, and all the designated rows y are activated. Data is transferred to the pixels in the column.

  The drive pattern in the first embodiment will be described with reference to FIG. FIG. 7 shows a common drive pattern in the double speed interpolation mode and the double speed double writing mode, and shows a case where the video signal is 120 frames per second and the number of subframes is 12. WC represents a data transfer period (WC period) in which data for each subframe is transferred to all pixels in the liquid crystal display element. DC represents a driving period (DC period) when driving the liquid crystal. The WC period is 347 [μs], and the DC period is 347 [μs]. In one frame, the WC period and the DC period are alternately repeated 12 times. Data of 0 or 1 assigned to each subframe in the order of SF1, SF2,..., SF11, SF12 from the beginning is transferred in the WC period, and the liquid crystal of all the pixels in the DC period is driven. When the data sampled and held in the pixel is 0, the pixel is in a blanking state, and when it is 1, it is in a driving state.

  Next, the gradation drive table in the first embodiment will be described with reference to FIGS. FIG. 8 shows the drive gradation table in the double speed interpolation mode, and FIG. 9 shows the drive gradation table in the double speed double writing mode. As in FIG. 7, the video signal has 120 frames per second, the number of subframes is 12, the data transfer period (WC period) is 347 [μs], and the drive period (DC period) is 347 [μs]. 8 and 9 show the state of the DC period for each subframe with respect to the drive gradation. The gradations in the vertical columns of FIGS. 8 and 9 are 4-bit data obtained by the frame rate control unit 24 and are limited by the limiter unit 25 to 12 which is the maximum value of the drive gradation. is there. SF1-SF12 represents the order of subframes within one frame. When the DC period column is 1, it indicates a driving state. A zero in the DC period column indicates a blank state.

  In the double speed interpolation mode, when the gradation shown in the vertical column of FIG. 8 is 1, only the first subfield SF1 is in the drive state. When the gradation is 2, only SF1 and SF2 are driven. Hereinafter, every time the number of gradations increases, the number of subframes in the driving state increases, and in the case of 12 which is the highest gradation, all the subframes are in the driving state. In other words, as the number of gradations increases, the number of subframes that are in the drive state increases backward in time.

  In the double speed double writing mode, when the gradation shown in the vertical column of FIG. 9 is 1, only the first subfield SF1 is in the drive state. When the gradation is 2, SF1 and SF7 are driven. When the gradation is 3, SF1, SF2, and SF7 are in a driving state. When the gradation is 4, SF1, SF2, SF7, and SF8 are in a driving state. Hereinafter, every time the number of gradations increases, the number of subframes in the driving state alternately increases between SF1 and SF6 and between SF7 and SF12, and is the highest gradation 12 All the subframes are in the drive state. In other words, as the number of gray levels increases, the subframes in the driving state alternately increase backward in time between SF1 and SF6 and between SF7 and SF12.

  In the double speed double writing mode, when the number of subframes created by the subframe data creation unit 26 is set to 2S, when the drive gradation is 1, the first subframe is in the drive state, and the drive gradation is 2 At this time, the first subframe and the (S + 1) th subframe are in the drive state. When the driving gradation is 3, the first, second, and (S + 1) th subframes are in the driving state, and the number of subframes that are in the driving state each time the number of gradations increases is the number of the first and Sth subframes. And alternately increase between the (S + 1) th and 2Sth subframes, and increase toward the back of the subframes already in the driving state.

  FIG. 14 is a diagram illustrating signal processing in the first embodiment. FIG. 15 is a diagram showing polarity inversion driving of the reflective liquid crystal display element 6 in the first embodiment.

  The signal processing will be described below with reference to FIGS. 2, 5, and 7 with reference to FIG. In FIG. 14, the vertical synchronization signal Vsync becomes active at time T0, and first, the data of subframe 1 (SF1) is transferred to the reflective liquid crystal display element 6 during the period of time T0-T1. This period (T0-T1) is the transfer period WC. During the transfer period WC, the reflective liquid crystal display element 6 needs to be in a blanking state regardless of the sampled and held value in the pixel, and V0 / V1 / Vcom sets the same voltage (here, GND). . Here, V0 is a blanking voltage, V1 is a driving voltage, and Vcom (common voltage) is a voltage of the counter electrode 10 of the liquid crystal. The transfer ends at time T1, and the next period (T1-T3) is the driving period DC. The time T2 is exactly in the middle of the period (T1-T3), and the period (T1-T2) and the period (T2-T3) are the same time. In the period (T1-T2), V1 is Vw and V0 / Vcom is GND. In the period (T2-T3), V1 is GND and V0 / Vcom is Vw, contrary to the period (T1-T2). It is controlled by the voltage controller 32 so that

  When the value of the sample hold in the pixel circuit 7 is “0”, V0 is applied to the pixel electrode 8 by the voltage selection circuit 17 in the pixel circuit 7. In the period T1-T2, the pixel electrode voltage Vpe and the counter electrode voltage Vcom are both GND. The voltage applied to the liquid crystal 9 is 0 [v], and the driving state of the liquid crystal is a blanking state.

  When the sample hold value in the pixel is “1”, V 1 is applied to the pixel electrode 8 by the voltage selection circuit 17 in the pixel circuit 7. In the period T1-T2, the pixel electrode voltage Vpe is Vw, and the counter electrode voltage Vcom is GND. The voltage applied to the liquid crystal 9 is + Vw (counter electrode reference), and the liquid crystal is in a driving state. In the period T2-T3, the pixel electrode voltage Vpe is GND, the counter electrode voltage Vcom is Vw, the voltage applied to the liquid crystal 9 is -Vw (counter electrode reference), and the driving state is established.

  By applying a voltage (+ Vw / −Vw) in the same voltage and different directions to the liquid crystal for the same period, the voltage applied to the liquid crystal on an average over a long period of time is set to + Vw + (− Vw) = 0 [v]. Is preventing. SF2-SF12 performs the same voltage control as in the period T0-T3 of SF1. In FIG. 15, a state corresponding to the period (T1-T2), that is, a state where V1 is Vw and V0 / Vcom is GND is represented as DC balance +. A state corresponding to the period (T2-T3), that is, a state where V1 is GND and V0 / Vcom is Vw is represented as DC balance.

  FIG. 16 is a diagram schematically comparing the degree of generation of a double image in the double speed interpolation mode and the double speed double writing mode. FIG. 16 shows a state where a black character “A” is displayed on a white background. In the double speed interpolation mode shown in FIG. 16A, moving image blur is improved by generating an interpolated image between frames, and a double image is not generated. In the double speed double writing mode shown in FIG. 16B, the original video frequency is doubled and the same video is displayed twice. When the character is stationary, the character “A” is normally displayed. However, a double image is generated when the image is horizontally scrolled. In the double speed double writing mode shown in FIG. 16C, the use of the gradation drive table shown in FIG. 9 prevents the generation of a double image.

  FIG. 17 is a diagram illustrating a state in which a screen in which an image having a width of 1 dot moves 2 dots to the right every 1/60 seconds is displayed in the double speed interpolation mode and the double speed double writing mode. Here, the gradation drive table is shown in FIG. The principle of generation of a double image in the double speed double writing mode will be described with reference to FIG. In the double speed interpolation mode shown in FIG. 17A, an interpolation frame (B) is generated and inserted between an image (A) having a width of 1 dot in the current frame and an image (A) having a width of 1 dot delayed by one frame. The On the other hand, in the double speed double writing mode shown in FIG. 17B, the same image (A ′) is displayed at the same position in the next frame of the image (A) having a certain width of 1 dot. The observer's line of sight moves as the image moves. Although the observer's line of sight is moving, the same image is displayed twice at the same position on the screen in the double speed writing mode, so that the image formed at the position L1 on the retina of the observer's eye An image (A ′) forms an image at a position L2 immediately next to (A). In this way, the observer recognizes the image as a laterally shifted image. Since there is a period in which the display approaches black (blackout period) between the display of the image (A) and the display of the image (A ′), the image (A) formed at the position L1 and the position The image (A ′) imaged on L2 is recognized as two independent images apart from each other.

  FIG. 18 is a diagram showing temporal changes in image light when the driving gradation table is set to FIGS. 8 and 9 in the double speed double writing mode. The input video signal is assumed to be a 50% white signal. FIG. 18A shows the drive voltage of the reflective liquid crystal display element 6 when the drive gradation table is that shown in FIG. According to the gradation drive table of FIG. 8, since SF1 to SF6 are in the drive state and SF7 to SF12 are in the blanking state, the input signal of the reflective liquid crystal display element 6 is substantially “1 (drive) in the first half of the frame A. Status) ”and the second half of the frame is“ 0 (blanking state) ”. FIG. 18B schematically shows the light output of the reflective liquid crystal display element 6. After the light output rises in the driving state of the first half of the frame A, the light output attenuates in the second half of the frame A and almost approaches the black level. Since the blackout period is long in this way, it looks like a double image.

  FIG. 18C shows the drive voltage of the reflective liquid crystal display element 6 when the drive gradation table is that shown in FIG. According to the gradation drive table of FIG. 9, SF1 to SF3, SF7 to SF9 are in the drive state, and SF4 to SF6 and SF10 to SF12 are in the blanking state, so the drive is divided into two subfield groups, and the reflection type The input signal of the liquid crystal display element 6 becomes “1” twice in one frame as shown in FIG. The reflective liquid crystal display element 6 responds twice in one frame. Compared with the case of the gradation drive table in FIG. 8, the blackout period is shortened, so that a double image is not formed. To summarize the above, in the double speed double writing mode in the first embodiment, the gradation drive table of FIG. 9 is applied to the double-speed video of one frame, and the drive is divided into two subfield groups. Thus, the generation of a double image can be eliminated.

  The first embodiment is also characterized in that step bit pulses having the same width are used without using binary bit pulses that cause a moving image pseudo contour, as shown in FIGS. The binary bit pulse performs so-called “binary weighting” in which a weight is expressed by 2n (n = 0, 1, 2, 3,...) For each subfield. On the other hand, when there are 1, 2, 4, 8, 16 binary bit pulses, step bit pulses are pulses having the same weight, such as 32, 32, 32, 32, 32, 32, 32. Compared with the case where all binary bit pulses are used, the combined use of step bit pulses has an effect of relatively reducing the moving image pseudo contour.

  Video pseudo-contour means that in a similar gradation of adjacent pixels, most of the binary bit pulses in one pixel are in the driving state, and many of the binary bit pulses in the other pixel are in the blanking state In this case, when the line of sight is moved or when the face is moved up, unintended luminance is perceived by the eyes. In the present embodiment, step bit pulses having the same width are used without using binary bit pulses that cause moving image pseudo contours. Therefore, even when the line-of-sight direction is moved, the luminance does not change remarkably, so that the moving image pseudo contour is hardly perceived.

  Next, an effect obtained by providing a frame rate control unit in a driving circuit of a liquid crystal display device using a reflective liquid crystal display element will be described. FIG. 16 is a diagram for explaining the generation mechanism of the transverse electric field in the reflective liquid crystal element. As shown in FIG. 16, the pixel electrodes 8 </ b> A and 8 </ b> B of the reflective liquid crystal element are formed on the silicon substrate 43.

  In the case of digital drive, the drive state (drive / blanking) frequently differs between adjacent pixels. For example, it is assumed that the gradation of adjacent pixels in a certain frame is “5” (pixel PA) and “6” (pixel PB), respectively. Further, consider the case where the counter electrode 10 is V0 with DC balance +. That is, since DC balance is + in FIG. 15, V0 = Vcom = 0 (V) and V1 = Vw. At the time of subframe 6, the driving state of adjacent pixels is different. As can be seen from FIG. 7, since the pixel PA is in the blanking state, a voltage of V0 is applied to the pixel electrode 8A, and since the pixel PB is in the driving state, a voltage of V1 is applied to the pixel electrode 8B.

  FIG. 16 shows the state of the electric field 41 of the liquid crystal layer when the voltage V0 is applied to the pixel electrode 8A and the voltage V1 is applied to the pixel electrode 8B. A potential difference is generated between the pixel electrode 8B (potential: Vw) and the counter electrode 10 (potential: 0 (V)) of the pixel PB, and the liquid crystal is rotated by a predetermined amount. At this time, a potential difference also occurs between the pixel electrode 8A (potential: 0 (V)) of the pixel PA and the pixel electrode 8B (potential: Vw) of the pixel PB, and an electric field is generated in the horizontal direction. Such a lateral electric field 42 causes unintentional disruption in the movement of the liquid crystal between the pixels. The above phenomenon contributed to image quality deterioration.

  By using the frame rate control, the above problem can be solved. FIG. 17 is a diagram for explaining that the horizontal electric field is evenly distributed by the frame rate control.

  FIG. 17 illustrates a case where the value of the lower F bits of the input data ((M + F) bits) to the frame rate control unit is “01”. Four tables (frames 0 to 3) are used for each frame. In each frame, when the driving state (driving or blanking) is different between adjacent pixels, the driving state is “0” (blanking state) from the pixel whose driving state is “1” (driving state). A horizontal electric field is generated in the direction of the pixel. The direction of the horizontal electric field between the pixels is represented by an arrow in FIG. In the rightmost state, the horizontal electric field states of the four frames are superimposed. That is, on the average of four frames, the horizontal electric field between all the pixels cancels out. As described above, by using the frame rate control, it is possible to cancel a lateral electric field that is a cause of image quality degradation.

<Second Embodiment>
FIG. 21 is a diagram showing a drive gradation table in the second embodiment. The second embodiment is the same as the first embodiment except that the gradation drive table is different.

  FIG. 21 shows the state of the DC period for each subframe with respect to the drive gradation, as in FIG. As in FIG. 9, a case where the video signal is 60 frames per second and the number of subframes is 12 will be described. The data transfer period (WC period) is 347 [μs], and the drive period (DC period) is 347 [μs]. That is, the gradation in the vertical column in FIG. 21 is 4-bit data obtained by the frame rate control unit 24 and is limited by the limiter unit 25 by 12 which is the maximum value of the drive gradation. . SF1-SF12 represents the order of subframes within one frame. When the DC period column is 1, it indicates a driving state. A zero in the DC period column indicates a blank state.

  In the double speed double writing mode, when the gradation shown in the vertical column of FIG. 21 is 1, only the last subfield SF12 is driven. When the gradation is 2, SF12 and SF6 are driven. When the gradation is 3, SF11, SF12, and SF6 are driven. When the gradation is 4, SF11, SF12 and SF5, SF6 are in a driving state. Hereinafter, every time the number of gradations increases, the number of subframes in the driving state alternately increases between SF1 and SF6 and between SF7 and SF12, and is the highest gradation 12 All the subframes are in the drive state. In other words, as the number of gradations increases, the subframes that are in the driving state alternately increase forward in time between SF1 and SF6 and between SF7 and SF12.

  In the double speed double writing mode, when the number of subframes created by the subframe data creation unit 26 is set to 2S, when the drive gradation is 1, the last subframe is in the drive state, and the drive gradation is 2 At this time, the last subframe and the Sth subframe are in the drive state. When the drive gradation is 3, the last and (2S-1) th and Sth subframes are in the drive state, and the number of subframes that are in the drive state each time the number of gradations is increased is the (S + 1) th and last. Alternately increase between subframes and between the first and Sth subframes, and increase toward the front of the subframe already in the driving state.

  Even in the double-speed twice writing mode in the second embodiment, the grayscale drive table of FIG. 21 is applied to the double-speed video of one frame, and the drive is divided into two subfield groups, thereby creating a double image. Can be eliminated. In the second embodiment, the effect of suppressing the moving image pseudo contour and the effect that the horizontal electric field that is a cause of image quality degradation can be canceled by using the frame rate control are the same as those in the first embodiment. Is equivalent to

<Third Embodiment>
FIG. 22 is a block diagram showing a drive circuit according to the third embodiment of the present invention. The drive circuit according to the present embodiment is different from the drive circuit according to the first embodiment shown in FIG. 5 in that the look-up table unit 21 is changed to a signal conversion unit 22. The configuration after the error diffusion unit 23 is the same as that of the drive circuit of the first embodiment.

  The drive pattern in the third embodiment is the same as the drive pattern in the first embodiment. The video signal is 120 frames per second, the number of subframes is 12, and the data transfer period (WC period) is 347 [μs]. It is. On the other hand, in the case of the first embodiment, the driving period of all subframes is the same time, whereas the driving period (DC period) of each subframe in the third embodiment is different. . In the third embodiment, the drive gradation is set as shown in FIG. 9 or FIG.

  The point that the period for each subframe is changed with respect to the first embodiment will be described below. The look-up table unit 21 in FIG. 5 has a function of realizing a liquid crystal display device having an input / output characteristic of gamma 2.2 by converting input / output characteristics of the reflective liquid crystal display element 6. In the third embodiment, the input / output characteristic conversion function is achieved by “changing the time of the drive period (DC period) for each subframe”. This will be specifically described below. FIG. 23 is a diagram showing that the luminance for each drive gradation is on the line of gamma 2.2 by adjusting each subframe period in the third embodiment. In the third embodiment, for example, the DC period for each subframe is set in advance so that the luminance characteristic for each drive gradation is on the line of gamma 2.2 as shown in FIG. The DC period of each subframe is in the range of about twice.

  As a result, the inverse gamma correction function can be omitted from the lookup table unit. As a result, the look-up table unit 21 using the look-up table can be changed to the signal conversion unit 22 not using the look-up table. Changing the lookup table unit 21 to the signal conversion unit 22 has an effect of cost reduction.

Hereinafter, the signal conversion unit 22 will be described. In the third embodiment, since the interpolation drive gradation itself has a luminance characteristic of gamma 2.2,

Input gradation X: interpolation driving gradation Y = 255 (maximum input gradation): 768 (maximum interpolation driving gradation)

From the relational expression, it is possible to use the following arithmetic expression. The signal converter 22 calculates input video signal data using the following calculation formula.

Output data Y: (M + F + D) bit = input data X × 768/255
Here, 768: maximum interpolation driving gradation (ie, 11000000)
255: Maximum drive gradation

Here, the drive gradation represents the gradation of the single element shown in FIGS. In addition, the interpolation driving gradation represents a gradation including a pseudo gradation that is interpolated by the error diffusion unit and the frame rate control unit.

  Also in the third embodiment, the effects of the first embodiment are equivalent.

  In the first to fourth embodiments, the number of bits of the input video signal data is N, the number of bits when the number of gradations that can be driven by the display element is expressed in binary, and the number of bits as an error by error diffusion processing. The case where N = 8, M = 4, D = 4, and F = 2 has been described, where D is the number of bits to be diffused and F is the number of bits expressed as a pseudo gradation by frame rate control. . However, the values of N, M, D, and F are not limited to the above values, and various values can be used. Among them, it is more preferable that N = 8 to 12, M = 4 to 6, D = 4 to 8, and F = 2 to 3.

1 illumination optical system, 2 light, 3 S polarized light, 4 P polarized light,
5 Polarizing beam splitter (PBS), 6 Reflective liquid crystal display element
7 pixel circuit, 8 pixel electrode, 9 liquid crystal, 10 counter electrode (transparent electrode),
11 projection lens, 12 emission light, 13 screen,
15 sample hold unit, 17 voltage selection circuit,
21 lookup table section, 22 signal conversion section,
23 error diffusion unit, 24 frame rate control unit,
25 limiter section, 26 subframe data creation section,
27 drive gradation table, 28 memory control unit, 29 frame buffer,
30 data transfer unit, 31 drive control unit, 32 voltage control unit,
33 source driver, 34 gate driver 41 electric field, 42 lateral electric field, 43 silicon substrate,
100 projection type liquid crystal display device, 101 signal processing circuit (signal processing unit),
102, 1020 drive circuit (drive device)

Claims (8)

A signal processing unit for converting an input signal into a signal in which the frame frequency is twice and the same frame is continuous twice;
Based on the signal converted by the signal processing unit, 2S subframes per frame and all subframes are configured by step bit pulses. When the driving gradation is 1, the first subframe is in a driving state. When the driving gradation is 2, the first subframe and the (S + 1) th subframe are in the driving state, and when the driving gradation is 3, the first and second, and the (S + 1) th subframe are in the driving state. Each time the number of gradations increases, the number of subframes that are in the drive state increases alternately between the first and Sth subframes and between the (S + 1) th and 2Sth subframes, and the drive state is already A driving device having a subframe data creation unit that creates subframe data by a driving gradation table that increases toward the rear of the subframe that is
A liquid crystal display element driven by the driving device;
An illumination optical system for making illumination light incident on the liquid crystal display element;
A projection lens that projects the modulated light emitted from the liquid crystal display element;
A liquid crystal display device comprising: A look-up table unit that converts a signal of N bits output from the signal processing unit into data of (M + F + D) bits larger than N by performing inverse gamma correction and linear interpolation, and processed by the look-up table unit An error diffusion unit that converts (M + F + D) bit data into (M + F) bit data by error diffusion processing, and (M + F) bit data processed by the error diffusion unit is converted into M bit data by frame rate control And a frame rate control unit for
The liquid crystal display device according to claim 1, wherein the subframe data creation unit creates the subframe data based on M-bit data processed by the frame rate control unit. A signal processing unit that converts an input signal into a signal in which the frame frequency is twice and the same frame is continuous twice;
Based on the signal converted by the signal processing unit, 2S subframes per frame and all subframes are configured by step bit pulses. When the driving gradation is 1, the last subframe is in a driving state. When the driving gradation is 2, the last subframe and the Sth subframe are in the driving state, and when the driving gradation is 3, the last and (2S-1) th, the Sth subframe are in the driving state. Each time the number of gradations increases, the number of subframes that are in the driving state increases alternately between the (S + 1) th and last subframes, and between the first and Sth subframes, and is already in the driving state. A driving device having a subframe data creation unit that creates subframe data by a driving gradation table that increases toward the front of the subframe,
A liquid crystal display element driven by the driving device;
An illumination optical system for making illumination light incident on the liquid crystal display element;
A projection lens that projects the modulated light emitted from the liquid crystal display element;
A liquid crystal display device comprising: A look-up table unit that converts a signal of N bits output from the signal processing unit into data of (M + F + D) bits larger than N by performing inverse gamma correction and linear interpolation, and processed by the look-up table unit An error diffusion unit that converts (M + F + D) bit data into (M + F) bit data by error diffusion processing, and (M + F) bit data processed by the error diffusion unit is converted into M bit data by frame rate control And a frame rate control unit for
4. The liquid crystal display device according to claim 3, wherein the sub-frame data creating unit creates the sub-frame data based on M-bit data processed by the frame rate control unit. A signal processing unit that converts an input signal into a signal in which the frame frequency is twice and the same frame is continuous twice;
Based on the signal converted by the signal processing unit, 2S subframes are formed per frame. When the driving gradation is 1, the first subframe is in the driving state, and when the driving gradation is 2, the first subframe is in the driving state. And the (S + 1) th subframe are in the driving state, and when the driving gradation is 3, the first and second, (S + 1) th subframes are in the driving state, and the driving state is increased every time the number of gradations increases. The number of sub-frames increases alternately between the first and S-th sub-frames, and between the (S + 1) -th and 2S-th sub-frames, toward the back of the sub-frame already in the driving state. In addition to the increase in the subframe data, the driving gradation table with different driving periods for each subframe so that the optical output of the liquid crystal with respect to the input video signal data has an inverse gamma characteristic. A driving device having a sub-frame data creation unit for creating,
A liquid crystal display element driven by the driving device;
An illumination optical system for making illumination light incident on the liquid crystal display element;
A projection lens that projects the modulated light emitted from the liquid crystal display element;
A liquid crystal display device comprising: A signal conversion unit for linearly interpolating a signal of N bits output from the signal processing unit to convert it into (M + F + D) bit data larger than N, and (M + F + D) bit data processed by the signal conversion unit An error diffusing unit that converts data into (M + F) bits by error diffusion processing; and a frame rate control unit that converts (M + F) bits of data processed by the error diffusing unit into M bits data by frame rate control. In addition,
6. The liquid crystal display device according to claim 5, wherein the sub-frame data creating unit creates the sub-frame data based on M-bit data processed by the frame rate control unit. A signal processing unit that converts an input signal into a signal in which the frame frequency is twice and the same frame is continuous twice;
Based on the signal converted by the signal processing unit, 2S subframes are formed per frame. When the driving gradation is 1, the last subframe is in a driving state, and when the driving gradation is 2, the last is subtracted. The subframe and the Sth subframe are in the drive state, and when the drive gradation is 3, the last and (2S-1) th and Sth subframes are in the drive state. The number of sub-frames increases alternately between (S + 1) and the last sub-frame, and between the first and S-th sub-frames, toward the sub-frame already in the driving state. Subframe data is created using a drive gradation table with different drive periods for each subframe so that the liquid crystal light output for the input video signal data has an inverse gamma characteristic. A driving device having a sub-frame data generation section that,
A liquid crystal display element driven by the driving device;
An illumination optical system for making illumination light incident on the liquid crystal display element;
A projection lens that projects the modulated light emitted from the liquid crystal display element;
A liquid crystal display device comprising: A signal conversion unit for linearly interpolating a signal of N bits output from the signal processing unit to convert it into (M + F + D) bit data larger than N, and (M + F + D) bit data processed by the signal conversion unit An error diffusing unit that converts data into (M + F) bits by error diffusion processing; and a frame rate control unit that converts (M + F) bits of data processed by the error diffusing unit into M bits data by frame rate control. In addition,
The liquid crystal display device according to claim 1, wherein the subframe data creation unit creates the subframe data based on M-bit data processed by the frame rate control unit.

Images