JP6197583B2 - Liquid crystal display device, driving device, and driving method - Google Patents

Description

  The present invention relates to a liquid crystal display device, a display device drive device, and a drive method.

  The driving method of the liquid crystal display element used in the liquid crystal display device is an analog method in which the voltage value applied to the pixel is a continuous analog value, and the voltage applied to the pixel is binary, and the luminance of the image There is a digital method for controlling an effective voltage value applied to a pixel of a liquid crystal by changing a time width of an applied voltage corresponding to (gradation). In the case of the digital method, since only information of 0 or 1 is applied to the pixel, it is difficult to be influenced by external factors such as noise.

  In the digital method, it is common to use a subfield method in order to obtain a halftone. In the subfield method, a predetermined number of subfields with different relative ratios of drive (light emission) periods are prepared in one field period of the video signal, and the subfield is appropriately selected according to the gradation of the video signal to be displayed. Display, and halftone display is performed using the visual integration effect of the viewer.

  In the digital method, gradation expression is performed only by turning on / off the drive (light emission), so that it is difficult to be affected by electrical noise in the transmission line and the like, and a stable display image can be obtained, but each adjacent pixel is turned on. When the switch is turned off, a horizontal electric field is generated between the pixels, and the movement of the liquid crystal between the pixels is disturbed, resulting in image quality deterioration.

  Patent Document 1 describes a method of dispersing a lateral electric field by using a pseudo gradation (dithering) circuit for gradation generation and using FRC (frame rate control) at the final stage.

  Further, in Patent Document 2, although not for the purpose of dispersing the horizontal electric field, an error diffusion circuit is used in the pseudo gradation circuit for gradation generation, and a pseudo noise signal is loaded when data is quantized. A method of dispersing noise due to pseudo gradation is described.

JP 2012-93479 A JP-A-10-91120

  In Patent Document 1, the use of FRC (frame rate control) at the final stage of dithering has an effect of diffusing a horizontal electric field and suppressing image quality deterioration. However, due to the characteristics of the FRC, there is a risk that a fixed pattern may be seen when the video is scrolled, or that the effect may be reduced when there is a gradation difference between pixels. In Patent Document 2, when applied to a liquid crystal display device, there is a risk that a noise component greater than the dispersion of the horizontal electric field may be perceived.

  The present invention has been made in view of the above points, and provides a liquid crystal display device, a driving device, and a driving method that can display with high display quality even when an image is scrolled or there is a gradation difference between pixels. The purpose is to provide.

  In the display device driving device according to one embodiment of the present invention, the pixel data of each pixel of the display element includes feedback error data that is a quantization error of the same pixel in the previous frame and quantization errors of peripheral pixels. An error diffusion unit that generates error addition data by adding error data of peripheral pixels, a subframe data generation unit that generates subframe data using data on the upper bit side in the error addition data, and A drive control unit that drives a pixel by driving a plurality of subframes included in one frame using the subframe data, and the error diffusion unit includes lower bits in the error addition data of the target pixel The error data of the target pixel is calculated using the data on the side, and using the error data of the target pixel and the error data of the surrounding pixels, And calculates the feedback error data of the pixel data to be elephants pixel, those.

  The driving method of the display device according to one embodiment of the present invention includes feedback error data that is a quantization error of the same pixel in the previous frame and quantization errors of peripheral pixels with respect to pixel data of each pixel of the display element. Adding error data of peripheral pixels to generate error addition data; for pixel data of each pixel of the display element, feedback error data that is a quantization error of the same pixel in the previous frame; and peripheral pixels Adding error data of peripheral pixels, which is a quantization error, and generating error addition data, and driving a plurality of subframes included in one frame using the subframe data, Driving a pixel of the display element, and using the lower bit side data in the error addition data of the target pixel, the error data of the target pixel Calculating the data, by using the error data of the surrounding pixels and the error data of the target pixel, then and calculates the feedback error data of the pixel data of interest pixel is intended.

  According to the present invention, it is possible to provide a liquid crystal display device, a driving device, and a driving method that can display with high display quality even when an image is scrolled or when there is a gradation difference between pixels.

It is a schematic block diagram of an example of the projection type display apparatus using the reflection type liquid crystal display element to which this invention is applied. It is a block diagram of one pixel in a liquid crystal display element. It is a figure which shows the relationship between the input voltage of a liquid crystal display element, and the intensity | strength of output light. It is a block diagram which shows the drive circuit structure of a liquid crystal display device. It is signal explanatory drawing of each part of FIG. It is explanatory drawing of an example of the drive pattern of a liquid crystal display element. It is a figure which shows an example of a drive gradation table. It is a figure which shows the error diffusion from an adjacent pixel. It is a figure which shows an error diffusion flow. It is a timing chart which shows signal processing. It is a figure which shows the polarity inversion drive of a liquid crystal display element. It is a figure explaining the generation | occurrence | production mechanism of the horizontal direction electric field in a liquid crystal display element.

  Embodiments of the present invention will be described below with reference to the drawings. The present invention can be applied to a panel type display device having a display panel in which a plurality of pixels are arranged in a matrix. In the following embodiments, an active matrix type reflective liquid crystal display element is used as a display panel. The projection type display device provided will be described as an example. First, a schematic configuration of a projection display device and a reflective liquid crystal display element to which the present invention is applied will be described. The present invention can be applied not only to a liquid crystal display device (LCD) but also to a panel type display device such as a plasma display panel (PDP) or a digital light processing (DLP).

(overall structure)
FIG. 1 shows a schematic configuration diagram of an example of a projection display device using a reflective liquid crystal display element to which the present invention is applied. In the figure, the projection display device 10 includes a liquid crystal display element 11, a polarization beam splitter (hereinafter referred to as PBS) 16, and a projection lens 17, and light emitted from the projection lens 17 is projected onto a screen 18. The

  The liquid crystal display element 11 includes a plurality of pixel electrodes 12 each having conductivity and light reflectivity, a liquid crystal layer 13, and a counter electrode (transparent electrode) 14 having conductivity and light transmission common to the plurality of pixel electrodes 12. And a pixel circuit 15. The plurality of pixel electrodes 12 are arranged in a two-dimensional matrix on the surface of a first substrate (not shown). FIG. 1 shows only one arbitrary pixel electrode among the plurality of pixel electrodes 12. The counter electrode 14 is formed on the surface of a second substrate (not shown). The liquid crystal layer 13 is sealed in a space between substrates formed by separating the first substrate and the second substrate so that the pixel electrode 12 and the counter electrode 14 face each other. Each surface of the pixel electrode 12 and the counter electrode 14 is covered with an alignment film (not shown). The pixel circuit 15 is electrically connected to the pixel electrode 12.

  In the projection display device 10, incident light L <b> 1 that is a backlight emitted from an illumination optical system (not shown) enters the PBS 16. The incident light L1 includes an S-polarized component and a P-polarized component whose planes of polarization are orthogonal to each other. In FIG. 1, the P-polarized component is schematically shown as a line segment, and the S-polarized component is shown as a circle. The PBS 16 has an optical characteristic of reflecting the S-polarized component of incident light and transmitting the P-polarized component. Accordingly, the PBS 16 reflects the S-polarized component of the incident light L 1 and enters the counter electrode 14.

  The liquid crystal display element 11 causes the S-polarized light component incident on the counter electrode 14 to be incident on the pixel electrode 12 and reflected through the liquid crystal layer 13, and the reflected light from the pixel electrode 12 passes through the liquid crystal layer 13 and the counter electrode 14. Eject. Here, the liquid crystal display element 11 responds to pixel data applied to the pixel electrode 12 in the above process until the S-polarized component incident on the counter electrode 14 is reflected by the pixel electrode 12 and emitted from the counter electrode 14. The S-polarized component incident on the counter electrode 14 is modulated in accordance with the potential difference between the drive voltage and the common voltage applied to the counter electrode 14, and a part of the S-polarized component is used as the P-polarized component. The light is emitted as a component and a P-polarized component.

  The PBS 16 transmits the P-polarized component of the light emitted from the liquid crystal display element 11 and enters the projection lens 17, and the S-polarized component reflects and enters the illumination optical system. The projection lens 17 projects the P-polarized component from the PBS 16 onto the screen 18 as outgoing light L2, and displays an image. The “output light intensity” described later refers to the illuminance of the emitted light L2 measured on the screen 18.

(Pixel configuration)
FIG. 2 shows a configuration diagram of one pixel of the liquid crystal display element 11. In FIG. 2, one pixel 20 of the liquid crystal display element 11 includes a pixel circuit 15 a and a liquid crystal element LC, and is arranged at the intersection of the column data line D and the row selection line W. As described above, in the liquid crystal element LC, the liquid crystal layer 13 is sealed in the space between the substrates formed by separating the first substrate and the second substrate so that the pixel electrode 12 and the counter electrode 14 face each other. It is set as the structure.

  On the other hand, the pixel circuit 15a is an example of the pixel circuit 15 in FIG. 1, and includes a sub-sample hold unit 21, a transfer switching transistor 22, a main sample hold unit 23, and a voltage selection unit 24 as shown in FIG. The sub-sample hold unit 21 and the main sample hold unit 23 are composed of a flip-flop having an SRAM (Static Random Access Memory) structure. The subsample hold unit 21 is connected to the column data line D and the row selection line W. When selected by a row selection signal applied via the row selection line W, the subsample hold unit 21 passes through the column data line D. The supplied pixel data is sampled and held.

  The transfer switching transistor 22 has a source connected to the output terminal of the subsample hold unit 21, a drain connected to the input terminal of the main sample hold unit 23, and a gate connected to the transfer signal line T. The transfer switching transistor 22 is activated when a transfer signal having a predetermined logical value is applied via the transfer signal line T, and the sub-frame data (pixel data voltage) held in the sub-sample hold unit 21 is activated. ) Is transferred to the main sample hold unit 23.

  The main sample and hold unit 23 samples and holds the subframe data (pixel data voltage) input through the transfer switching transistor 22. The voltage selection unit 24 is connected to the blanking voltage line V0 and the drive voltage line V1. An output terminal of the voltage selection unit 24 is connected to the pixel electrode 12. The voltage selection unit 24 determines whether the blanking voltage line V0 is blanked according to whether the value of the subframe data (pixel data voltage) held by the main sample hold unit 23 is “0” or “1”. One of the voltage and the driving voltage of the driving voltage line V <b> 1 is selected and applied to the pixel electrode 12. The voltage applied to the counter electrode 14 is called a common voltage Vcom.

  The subsample hold unit 21 receives and holds subframe data for a predetermined subframe during a data transfer period for the predetermined subframe. Then, after the data transfer period for the predetermined subframe ends, the subsample hold unit 21 transfers the data for the predetermined subframe to the main sample hold unit 23. Further, the predetermined subframe is driven using the subframe data held by the main sample hold unit 23 during the data transfer period for the next subframe of the predetermined subframe. This makes it possible to efficiently transfer data and drive subframes simultaneously.

  FIG. 3 is a diagram illustrating the relationship between the input voltage of the liquid crystal display element 11 and the intensity of output light. In FIG. 3, the horizontal axis represents the input voltage, and shows the potential difference between the pixel electrode 12 and the counter electrode 14, that is, the driving voltage of the liquid crystal layer 13. The vertical axis in FIG. 3 indicates the intensity (luminance) of output light emitted from the liquid crystal layer 13.

  When the voltage is 0 (for example, both the pixel electrode 12 and the counter electrode 14 are GND), the intensity of the output light is small and the output light is in a black state (blanking voltage), and the voltage at which the output light starts to saturate is the saturation voltage Vw ( White level.)

(Driver and drive method)
The display element driving apparatus and driving method according to the present embodiment will be described with reference to FIGS. FIG. 4 is a block diagram showing a liquid crystal display panel 30 provided with a driving device. FIG. 5 is a diagram for explaining gradation expression. FIG. 5 shows an example of gradation expression in each process unit when the number of bits of input video signal data is 8 bits. FIG. 6 is a diagram showing a drive pattern. FIG. 7 shows a drive gradation table. FIG. 8 is a diagram showing a feedback type error diffusion flow. FIG. 9 is a diagram showing an error diffusion diagram. In the present embodiment, error data of peripheral pixels is diffused by using a pseudo gradation (dithering) circuit for gradation generation.

  As shown in FIG. 4, the liquid crystal display panel 30 of the present embodiment includes a lookup table unit 27, an error diffusion unit 28, a limiter unit 29, a subframe data generation unit 31, a memory control unit 32, The frame buffer 33, the drive control unit 34, the data transfer unit 36, the source driver 37, the voltage control unit 38, the gate driver 39, and the pixel unit 40 are configured.

  The pixel unit 40 is arranged at each intersection where n + 1 column data lines D0 to Dn and m + 1 row selection lines W0 to Wm intersect, and a total of (n + 1) × (m + 1) pixels 20 are arranged. Consists of One pixel 20 has the configuration of the pixel 20 shown in FIG. Further, as shown in FIG. 2, in all the pixels 20 of the pixel unit 40, the blanking voltage line V0 and the drive voltage line V1 are commonly connected to each voltage selection unit 24, and the gates of the transfer switching transistors 22 are connected. The transfer signal line T is connected in common.

  The look-up table unit 27 receives N-bit video signal data. The lookup table unit 27 has a lookup table (LUT). The lookup table unit 27 performs inverse gamma correction with reference to the LUT. As a result, the N-bit video signal data is converted into (M + D) -bit pixel data larger than N. Here, M is the number of bits when the number of subframes is expressed in binary, D is the number of bits to be interpolated by the error diffusion unit 28, and N, M, and D are positive integers.

  In the example of FIG. 5, the number of bits of the input video signal data is 8 bits (N = 8), the number of bits interpolated by the error diffusion unit 28 is 6 bits (D = 6), and the number of subframes is a binary number. In this case, the number of bits is 4 bits (M = 4), and the drive gradation is 15 (not including black).

  Here, the operation of the lookup table unit 27 will be described. Generally, video signals are subjected to gamma correction. On the display device side, it is necessary to perform inverse gamma correction processing on the video signal that has been subjected to gamma correction to restore the linear gradation. Inverse gamma correction is correction in which the output is X raised to the power of 2.2 with respect to the input X. In this case, the output characteristic is expressed as “gamma 2.2” below.

  The look-up table unit 27 has a function of realizing a liquid crystal display device having an output characteristic of gamma 2.2 by converting input / output characteristics of the liquid crystal display element 11. The look-up table is adjusted in advance so that the 10-bit output has an arbitrary output characteristic (for example, gamma 2.2). For example, an image obtained by driving each of the 15 drive gradations (not including black) shown in FIG. 7 is projected by the liquid crystal display device shown in FIG. 1, and the illuminance on the screen 18 is measured by an illuminometer or the like. deep. Illuminance data for each gradation of 0 to 960 is predicted by linearly interpolating the illuminance between the respective drive gradations with 6 bits (D = 6) (64 gradations). It is assumed that 256 pieces of data having arbitrary output characteristics (for example, gamma 2.2) are selected from those illuminance data and are stored as a lookup table in advance.

  The lookup table unit 27 has a lookup table of 256 × 10 bits (that is, “2 to the 8th power” gradation x (4 + 6) bits). Here, for “2 to the 8th power” gradation x (4 + 6) bits, values of N = 8, M = 4, and D = 6 are substituted for “2 to the Nth power” gradation x (M + D) bits. Is equivalent to The look-up table unit 27 converts the input 8-bit image data into unsigned 10-bit data and outputs it.

  Returning to FIG. The video signal data converted into (M + D) bits by the look-up table unit 27 is converted into (M + 1) bit data by diffusing the lower D bits of information to surrounding pixels by the error diffusion unit 28. In the example of FIG. 5, the converted 10-bit data is 5 in which the error diffusion unit 28 diffuses lower 6-bit information to surrounding pixels, quantizes it into upper 4-bit data, and adds 1 bit of carry. Output as bit data.

  The error diffusion method is a method of compensating for the lack of gradation by diffusing the quantization error of the pixel to be quantized to surrounding pixels. In other words, it is a method of compensating for the lack of gradation by adding the error (quantization error) of the surrounding pixels to the pre-quantization value of the pixel to be quantized and then performing the quantization process. . In the first embodiment, not only the quantization error of the pixel to be quantized is diffused to the surrounding pixels but also diffused to the rear frame. In other words, the error of the surrounding pixels (quantization error) and the feedback error that is the error of the same pixel (quantization error) of the previous frame are added to the value before quantization of the pixel to be quantized. This is a method of compensating for the lack of gradation by performing a quantization process thereafter.

The operation of the error diffusion unit 28 will be described in more detail with reference to FIG. As shown in FIG. 9, the error diffusion unit 28 of the present embodiment includes an error diffusion buffer 51, an error diffusion buffer control unit 52, a feedback error frame buffer control unit 53, a feedback error frame buffer 54, and a quantization. And a control unit 55.
As shown in FIG. 8, the coordinates of the pixel (target pixel) to be quantized are (x, y). The feedback error frame buffer 54 stores the feedback error data F (x, y) stored in the previous frame. The feedback error frame buffer control unit 53 stores the previous frame from the feedback error frame buffer 54. The feedback error data F (x, y) thus read is read out. The feedback error frame buffer 54 has a structure that holds signed 7-bit data for all pixels. The feedback error frame buffer control unit 53 adds the feedback error data F (x, y) to the input unsigned 10-bit data D (x, y).

  The feedback error frame buffer control unit 53 adds signed 7-bit feedback error data F (x, y) to unsigned 10-bit pixel data D (x, y). Then, unsigned 11-bit data D ′ (x, y), which is one bit added to the data D (x, y) for carrying, is output. At this time, if the result of addition is a negative number, it is set to “0”.

  The error diffusion buffer 51 stores error data generated at the time of quantization for each pixel. From the error diffusion buffer 51, the error diffusion buffer control unit 52 performs quantization error data E (x−1, y) on the left adjacent pixel and quantization error data E (x−1, y−1) on the upper left pixel. ), Quantization error data E (x, y-1) of the pixel immediately above, and quantization error data E (x + 1, y-1) of the upper right pixel. Then, the error diffusion buffer control unit 52 performs quantization error data E (x−1, y), quantization error data E (x−1, y−1), quantization error data E (x, y−1). And E (x, y), which is the average value of the quantization error data E (x + 1, y-1), is added to the data D '(x, y).

Here, as shown in FIG. 8, a weighted average value is used as the average value of the quantization error data. Therefore, the error diffusion buffer control unit 52 calculates the quantization error data E (x−1, y−1) of the left adjacent pixel, the quantization error data E (x−1, y−1) of the upper left pixel, The quantization error data E (x, y-1) of the pixel and the quantization error data E (x + 1, y-1) of the upper right pixel are read out. Then, the error diffusion buffer control unit 52 calculates a weighted average value as in the following equation (1).
E (x, y) = (E (x-1, y-1) * a + E (x, y-1) * b + E (x + 1, y-1) * c + E (x-1 , y) * d) / (a + b + c + d) (1)
Here, a, b, c, and d are arbitrary coefficients. As described above, the error can be appropriately diffused by using the weighted average of the quantization error data of a plurality of peripheral pixels. Note that E (x, y) may not be a weighted average value but simply an arithmetic average value. That is, the coefficients a, b, c, and d can be set to 1, respectively.

  The weighted average value E (x, y) is error data diffused from surrounding pixels. The error diffusion buffer 51 stores signed 6-bit data as error data E (x, y). The error diffusion buffer control unit 52 adds signed 6-bit error data E (x, y) to unsigned 11-bit data D ′ (x, y). The error diffusion buffer control unit 52 outputs unsigned 11-bit error addition data D ″ (x, y). At this time, if the result of addition is a negative number, it is set to “0”. In this manner, the error diffusion unit 28 adds (M + D) -bit pixel data D (x, y) to the feedback error data F (x, y) and the error data E (x, y) diffused from the surrounding pixels. Are added to generate (M + D + 1) -bit error addition data D ″ (x, y).

  Next, the quantization control unit 55 divides the 11-bit error addition data D ″ (x, y) into upper 5 bits and lower 6 bits. The upper 5 bits are treated as unsigned 5-bit data DU (x, y). The lower 6 bits are handled as signed 6-bit error data DL (x, y) without conversion. If the most significant (sign) bit of the signed 6-bit error data DL (x, y) is “1”, “1” is added to the unsigned 5-bit data DU (x, y), and the sign None 5-bit data DU ′ (x, y) is output from the error diffusion unit 28. On the other hand, when the most significant (sign) bit of the signed 6-bit error data DL (x, y) is “0”, the 5-bit data DU (x, y) is directly converted into the unsigned 5-bit data DU ′. It is output from the error diffusion unit 28 as (x, y).

  Here, “1” is added to the data DU (x, y) according to the value of the most significant bit of the error data DL (x, y), but the error data DL (x, y) and the threshold value are added. "1" may be added to the data DU (x, y) in accordance with the comparison result. That is, when the error data DL (x, y) is larger than a preset threshold value, “1” is added to the data DU (x, y), and when it is smaller, “1” is added to the data DU (x, y). ) May not be added. That is, the quantization control unit 55 determines whether or not to add “1” to the data DU (x, y) according to the comparison result between the threshold value and the error data DL (x, y).

  Next, the error diffusion buffer control unit 52 stores signed 6-bit error data DL (x, y) in the error diffusion buffer 51. This signed 6-bit error data DL (x, y) is used for error diffusion to surrounding pixels, and is quantized when obtaining error data (weighted average value) E (x ′, y ′) in the surrounding pixels. Used as error data. That is, the error data DL (x, y) becomes the quantization error data represented by the equation (1), is multiplied by the coefficient, and is used for using the weighted average value. For example, when the error data E (x + 1, y) is obtained, the error data DL (x, y) is used as the quantization error data E (x, y). In this way, quantization errors are sequentially diffused to adjacent pixels.

  Next, the feedback error frame buffer control unit 53 calculates the weighted average value E (x, y) of the quantized error data of the signed 6-bit peripheral pixels from the signed 6-bit error data DL (x, y). Subtracted and stored in the feedback error frame buffer 54 as signed 7-bit feedback error data F ′ (x, y). That is, the feedback error frame buffer control unit 53 calculates the feedback error data F ′ (x, y) from the difference between the error data DL (x, y) and the weighted average value E (x, y) of the quantization error data. calculate. The feedback error frame buffer control unit 53 uses the feedback error data F ′ (x, y) as feedback error data F (x, y) in the next frame.

  4 and 5, the unsigned 5-bit data DU ′ (x, y) output from the error diffusion unit 28 is output to the limiter unit 29. The limiter unit 29 limits the data DU ′ (x, y) to 15 which is the maximum value of the drive gradation, and outputs it to the subframe data generation unit 31. That is, the limiter unit 29 outputs 4-bit data to the subframe data generation unit 31. The subframe data generation unit 31 converts 4-bit data into 15-bit subframe data. The conversion to 15-bit subframe data can use the drive gradation table 31a.

  FIG. 7 shows an example of the drive gradation table 31a. A subframe is composed of step bit pulses. Therefore, when the subframe data is “1”, the subframe is in a driving state, and when it is “0”, the subframe is in a blanking state. Each time the driving gradation is increased by 1, the number of subframes in the driving state increases one by one before or after the subframe that is already in the driving state. Therefore, the subframes in the driving state are continuous. Note that the subframe that is in the driving state when the driving gradation (subframe data) is 1 is preferably the first subframe (SF1) or the last subframe (SF15). In the drive gradation table of FIG. 7, it is only necessary that the number of subframes that are in the drive state increases by 1 each time the drive period is increased, and the position of the subframe that is in the drive state may be arbitrary. Also for the driving period, it is not necessary that all the subframes are the same, and may be arbitrary.

  Returning to FIG. 4, the 15-bit subframe data output from the subframe data generation unit 31 is stored in the frame buffer 33 divided for each subframe by the memory control unit 32. The frame buffer 33 has a double buffer structure, and includes a first frame buffer 33a and a second frame buffer 33b. While data is being stored in the first frame buffer 33a, the data in the second frame buffer 33b is transferred to the pixel circuit via the data transfer unit. In the next frame, the data of the first frame buffer 33a stored during the previous frame period is transferred to the pixel circuit via the data transfer unit 36, and the input video signal is input to the second frame buffer 33b. Output data from the data subframe data generation unit 31 is stored.

  The drive control unit 34 controls processing timing for each subframe based on the horizontal start signal HST and the horizontal clock signal HCK, and performs a transfer instruction to the data transfer unit 36 and control of the gate driver 39. . The data transfer unit 36 instructs the memory control unit 32 according to the instruction from the drive control unit 34, receives the designated subframe data from the memory control unit 32, and transfers it to the source driver 37. Each time the source driver 37 receives data for one line from the data transfer unit 36, it simultaneously transfers the data to the corresponding pixel circuit 15a of the liquid crystal display element 11 using the column data lines D0-Dn.

  At this time, the gate driver 39 activates the row selection line Wy of the row designated by the vertical start signal (VST) / vertical shift clock signal (VCK) from the drive control unit 34, and all the designated rows y are activated. Data is transferred to the pixels in the column. In addition, a transfer signal line T is connected to each pixel 20. As shown in FIG. 2, the transfer signal line T is connected to the transfer switching transistors 22 of the pixel circuits 15 a of all the pixels 20. The drive control unit 34 drives the pixel 20 by digitally driving the subframe using the subframe data.

  The drive pattern in this embodiment will be described with reference to FIG. FIG. 6 shows a case where the video signal is 60 frames per second and the number of subframes is 15. WC represents a data transfer period (WC period) in which data for every 20 subframes of all pixels in the liquid crystal display element is transferred. DC represents a driving period (DC period) when driving the liquid crystal. The WC period is 1111 [μs] (= 1 / (60 × 15)), and the DC period is 1111 [μs]. In one frame, first, data transfer of SF1 (WC period) is performed and held in the sub-sample hold unit 21 in the pixel circuit 15a. After the data transfer to all the pixels is completed, the transfer signal T becomes high, and the data held in the sub-sample hold unit 21 of all the pixels is transferred to the main sample hold unit 23. After that, data transfer of SF2 (WC period) is performed, and at the same time, driving of SF1 (DC period) is performed for the same period as the WC period.

  In this way, the WC period and the DC period are shifted by the WC period (DC period) in parallel and continued 15 times. Data of 0 or 1 assigned to each subframe is transferred in the order of SF1, SF2,..., SF14, SF15 from the top in time, and the liquid crystal of all pixels is driven in the DC period. . When the data sampled and held in the pixel is 0, the pixel is in a blanking state, and when the data is 1, the pixel is in a driving state.

  By the way, in this embodiment, the projection type display apparatus provided with the active matrix type liquid crystal display element 11 as a display element is explained as an example. Here, characteristics when the liquid crystal is driven by the gradation drive table of FIG. 7 will be described. In FIG. 7, it is assumed that the gradation is K. Then, SF1 to SFK becomes 1 (driving state). Since 1 from SF1 to SFK is regarded as a substantially continuous ON state, the relationship between K (number of gradations) and output light is substantially the relationship between the input voltage of the liquid crystal display element 11 shown in FIG. 3 and the intensity of the output light. Draw a curve close to. This has an advantageous effect on the operation of the lookup table unit 27. That is, since the relationship between the input voltage of the liquid crystal display element 11 and the intensity of the output light is relatively close to the curve of gamma 2.2 targeted by the lookup table unit 27, the lookup table unit 27 uses a gamma of 2.2. The burden of converting to a curve is reduced. The above characteristics are the same in the transmissive liquid crystal element.

  FIG. 10 is a diagram showing signal processing in this embodiment. FIG. 11 is a diagram showing polarity inversion driving of the liquid crystal display element 11 in the present embodiment.

  Hereinafter, the signal processing will be described with reference to FIG. 10, with reference to FIGS. In FIG. 10, the vertical synchronization signal Vsync becomes active at time T0, and first, the data of subframe 1 (SF1) is transferred to the liquid crystal display element 11 during the period of time T0-T2. This period (T0-T2) is the transfer period WC. Data is transferred to a pixel (x, y) at time T 1 and held in the sub-sample hold unit 21. At time T2, the transfer signal T becomes high, and the data held in the subsample hold unit 21 is transferred to the main sample hold unit 23 in all the pixels. In the period of time T2-T4, data of the next subframe 2 (SF2) is transferred. At the same time, the period of time T2-T4 is the driving period DC of subframe 1 (SF1), DC balance + drive is performed in period (T2-T3), and DC balance-drive is performed in period (T3-T4). In the period (T2-T3), the voltage control unit is set so that V0 / Vcom becomes GND and V1 becomes Vw, and in the period (T3-T4), V1 becomes GND and V0 / Vcom becomes Vw. 38.

  When the value of the main sample hold unit 23 in the pixel circuit 15 a is “0”, V 0 is applied to the pixel electrode 12 by the voltage selection unit 24 in the pixel circuit 15. In the period T1-T2, the pixel electrode voltage Vpe and the counter electrode voltage Vcom are both GND. The voltage applied to the liquid crystal layer 13 is 0 [v], and the driving state of the liquid crystal is a blanking state.

  When the value of the main sample hold unit 23 in the pixel 20 is “1”, V 1 is applied to the pixel electrode 12 by the voltage selection unit 24 in the pixel circuit 15. In the period T1-T2, the pixel electrode voltage Vpe is Vw, and the counter electrode voltage Vcom is GND. The voltage applied to the liquid crystal layer 13 is + Vw (counter electrode reference), and the liquid crystal is in a driving state. In the period T2-T3, the pixel electrode voltage Vpe is GND, the counter electrode voltage Vcom is Vw, the voltage applied to the liquid crystal layer 13 is -Vw (counter electrode reference), and the driving state is established.

  By applying the same voltage and different voltages (+ Vw / −Vw) to the liquid crystal for the same period, the voltage applied to the liquid crystal on an average over a long period of time is set to + Vw + (− Vw) = 0 [v]. By doing so, liquid crystal burn-in is prevented. SF2-SF12 performs the same voltage control as in the period T0-T3 of SF1. In FIG. 10, a state corresponding to the period (T1-T2), that is, a state in which V1 is Vw and V0 / Vcom is GND as shown in FIG. A state corresponding to the period (T2-T3), that is, a state where V1 is GND and V0 / Vcom is Vw is represented as DC balance.

  FIG. 12 is a diagram for explaining the generation mechanism of the transverse electric field in the reflective liquid crystal element. FIG. 12 schematically illustrates the configuration of adjacent pixels 20A and 20B. As shown in FIG. 12, the pixel electrodes 12 </ b> A and 12 </ b> B of the reflective liquid crystal element are formed on the silicon substrate 43.

  In the case of digital drive, the drive state (drive / blanking) frequently differs between adjacent pixels. For example, it is assumed that the gradations of adjacent pixels in a certain frame are “5” (pixel 20A) and “6” (pixel 20B), respectively. Further, consider the case where the counter electrode 14 is V0 with DC balance +. That is, in FIG. 11, since DC balance is +, V0 = Vcom = 0 (V) and V1 = Vw. At the time of subframe 6 (SF6), the drive states of adjacent pixels are different. As can be seen from FIG. 7, since the pixel 20A is in a blanking state, a voltage of V0 is applied to the pixel electrode 12A, and since the pixel 20B is in a driving state, a voltage of V1 is applied to the pixel electrode 12B.

  FIG. 12 shows the state of the electric field 41 of the liquid crystal layer 13 when the voltage V0 is applied to the pixel electrode 12A and the voltage V1 is applied to the pixel electrode 12B. A potential difference is generated between the pixel electrode 12B (potential: Vw) and the counter electrode 14 (potential: 0 (V)) of the pixel 20B, and the liquid crystal is rotated by a predetermined amount. At this time, a potential difference also occurs between the pixel electrode 12A (potential: 0 (V)) of the pixel 20A and the pixel electrode 12B (potential: Vw) of the pixel 20B, and an electric field is generated in the horizontal direction. Such a lateral electric field 42 causes unintentional disruption in the movement of the liquid crystal between the pixels. The above phenomenon contributed to image quality deterioration.

  By using the error diffusion unit 28, it is possible to eliminate the above problems. For example, it is possible to prevent the fixed pattern from being seen when scrolling. Further, even when there is a gradation difference between pixels, the lateral electric field can be effectively dispersed. Therefore, it is possible to display with high display quality. In particular, when displaying using high-bit pixel data, it is possible to effectively prevent deterioration in image quality. Further, since the frame rate control table is not used as in Patent Document 1, it is possible to prevent the frame rate control table pattern from appearing on the display. Therefore, display quality can be improved.

  In the above description, the feedback error data F ′ (x, y) is calculated from the difference between the error data DL (x, y) and the weighted average value E (x, y) of the quantization error. The feedback error data F ′ (x, y) may be calculated by taking a difference after multiplying by an appropriate coefficient.

  When the number of bits of the input video signal data is N, the number of bits in which the display element can be driven is expressed in binary, the number of bits is M, and the number of bits diffused as an error by error diffusion processing is D , N = 8, M = 4, D = 6. However, the values of N, M, and D are not limited to the above values, and various values can be used. Among them, it is more preferable that N = 8 to 12, M = 4 to 6, and D = 6 to 10.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 11 Liquid crystal display element 12 Pixel electrode 13 Liquid crystal layer 14 Common electrode 15 Pixel circuit 20 Pixel 23 Main sample hold part 24 Voltage selection part 30 Liquid crystal display panel D0-Dn, D column data line DX0-DXn, DX Inversion column data line W0- Wm, W Row selection line V0 Blanking voltage line V1 Drive voltage line

Claims (7)

The error addition data is obtained by adding the feedback error data that is the quantization error of the same pixel in the previous frame and the error data of the peripheral pixel that is the quantization error of the peripheral pixels to the pixel data of each pixel of the display element. An error diffusion unit for generating
A subframe data generation unit that generates subframe data using data on the upper bit side in the error addition data;
A drive control unit that drives the pixels of the display element by driving a plurality of subframes included in one frame using the subframe data;
The error diffusion unit calculates error data of the target pixel using data on a lower bit side in the error addition data of the target pixel,
Using the difference between the error data of the surrounding pixels and the error data of the target pixel, then and calculates the feedback error data of the pixel data of interest pixels,
Drive device for display device.   The display device driving apparatus according to claim 1, wherein the error diffusion unit includes an error diffusion buffer control unit that calculates error data of the peripheral pixels from quantization errors of the plurality of peripheral pixels. The subframe data generation unit is configured such that when the subframe data has a first value, the subframe is in a driving state, and when the subframe data has a second value, the subframe is blanked. State
Each time the driving gradation of the pixel increases by 1, the subframe data is set so that the number of subframes that are in the driving state increases one by one before or after the subframe that is already in the driving state. driving device for a display device according to claim 1 or 2, characterized in that to generate. A drive device for a display device according to any one of claims 1 to 3 ,
The display element is a liquid crystal display element;
An illumination optical system for making illumination light incident on the liquid crystal display element;
A liquid crystal display device further comprising: a projection lens that projects the modulated light emitted from the liquid crystal display element. The liquid crystal display element includes a first sample hold unit and a second sample hold unit,
The first sample hold unit receives and holds subframe data for the predetermined subframe during a data transfer period for the predetermined subframe,
After the end of the data transfer period for the predetermined subframe, the data for the predetermined subframe is transferred to a second sample and hold unit, and the liquid crystal display element transfers data for the subframe next to the predetermined subframe. The liquid crystal display device according to claim 4 , wherein the predetermined subframe is driven using subframe data held by the second sample hold unit during a period.   The liquid crystal display element further includes a voltage selection unit and a pixel electrode unit,
  The voltage selection unit selects one voltage line from a plurality of voltage lines according to a value held in the second sample hold unit, and outputs a voltage related to the selected voltage line to the pixel electrode unit. The liquid crystal display device according to claim 5, wherein the liquid crystal display device is applied to the liquid crystal display device. The error addition data is obtained by adding the feedback error data that is the quantization error of the same pixel in the previous frame and the error data of the peripheral pixel that is the quantization error of the peripheral pixels to the pixel data of each pixel of the display element. A step of generating
Generating subframe data using data on the upper bit side in the error addition data; and
Driving the pixels of the display element by driving a plurality of subframes included in one frame using the subframe data ;
Calculating error data of the target pixel using lower-order bit data in the error addition data of the target pixel ;
Using the difference between the error data of the target pixel and the error data of the surrounding pixels, and calculating feedback error data of the pixel data that will be the target pixel next .
A driving method of a display device.

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