JP7340178B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- H—ELECTRICITY
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- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
図1は、第1の実施形態による半導体装置1の一例を示す構成図である。
図1に示すように、半導体装置1は、例えば、3次元(3D)NAND型フラッシュメモリ装置であり、メモリ半導体チップ10と、平面バッファチップ20と、TSV(Through-Silicon Via)30とを備えている。
図2に示すように、半導体装置1は、アドレスデコーダ11と、電圧生成回路12と、制御回路13と、平面バッファ部200と、メモリセルアレイ40とを備えている。
図3は、メモリセルアレイ40及び平面バッファチップ20の構成例を示す断面図である。図4は、図3に示すメモリセルアレイ40の一部を拡大した断面図である。図5は、メモリセルアレイ40及び平面バッファチップ20の電気的接続構造を示す構成図である。図6は、図5に示すメモリセルアレイ40及び平面バッファチップ20の電気的接続構造を平面的に見た構成図である。
上述した図2において、半導体装置1からデータを読み出す際に、アドレス情報と、例えば、データ読み出しコマンドが半導体装置1に入力されると、まず、アドレスデコーダ11が、入力されたアドレス情報に基づいて、読み出すメモリセルMCを選択するための、SGDx0信号,SGDx1信号,SGDy0信号,SGDy1信号、SGS信号、及びCG0信号~CG31信号を生成する。
図7は、本実施形態における平面バッファチップ20が備えるバッファ回路21とセンスアンプ60との接続例を示す構成図である。
これに対して、本実施形態による半導体装置1では、例えば、10ページ分(160KB)を並列処理可能であり、スループットを160MB/sに高速化させることができる。
次に、図面を参照して、第2の実施形態による半導体装置1aについて説明する。
図10に示すように、半導体装置1aは、例えば、NAND型フラッシュメモリ装置であり、メモリ半導体チップ10と、デコーダ10Aと、平面バッファチップ20と、TSV30とを備えている。なお、図10において、上述した図1と同一の構成には同一の符号を付与して、その説明を省略する。
図11は、本実施形態におけるバッファデコーダ部50の一例を示す構成図である。
図11に示すように、バッファデコーダ部50は、Xバッファデコーダ51と、Yバッファデコーダ52と、デコーダスイッチ部53とを備えている。
図12は、本実施形態におけるデコーダスイッチ部53のY0線を選択する場合の構成図である。また、図13は、本実施形態におけるデコーダスイッチ部53のX0線を選択する場合の構成図である。
例えば、上記半導体装置1については、図14~図16に示すような構成とすることも可能である。
10 メモリ半導体チップ
10A チップ積層体
10-SGS、10-0、10-30、10-31、10-SGD ゲートプレート電極
10A デコーダ
11 アドレスデコーダ
12 電圧生成回路
13 制御回路
20 平面バッファチップ
21 バッファ回路
22 ビット配線層
23 層間絶縁層
24 コンタクトプラグ
30 TSV(貫通電極)
31 ビット配線層
32 コンタクトプラグ
33 層間絶縁層
40 メモリセルアレイ
50 バッファデコーダ部
51 Xバッファデコーダ
52 Yバッファデコーダ
53 デコーダスイッチ部
60 センスアンプ
200 平面バッファ部
CP セルピラー
MC メモリセル
NS NANDセルストリング
SW1、SW2 選択スイッチ部
TR1、TR2 選択トランジスタ
Claims (5)
- 複数のメモリセルが半導体基板の上に積層されたメモリ半導体チップと、
前記メモリセルから読み出したデータ及び前記メモリセルに書き込みされるデータを保持し、保持した前記データを出力するバッファ回路を、前記複数のメモリセルのビット線の数に応じて複数備える半導体チップである平面バッファチップと、
前記メモリ半導体チップの前記メモリセルのビット線と、前記平面バッファチップの前記バッファ回路とを、前記メモリ半導体チップ及び平面バッファチップの厚み方向に、電気的に接続する電気的接続構造とを備え、
前記電気的接続構造は、少なくとも前記複数のメモリセルを厚み方向に貫通する貫通電極を介して前記複数のメモリセルのビット線を厚み方向に電気的に接続している
ことを特徴とする半導体装置。 - 前記メモリ半導体チップを厚み方向に積層したチップ積層体を備え、
前記チップ積層体は、前記メモリ半導体チップの各間が前記貫通電極を介して電気的に接続されている
ことを特徴とする請求項1に記載の半導体装置。 - 前記複数のメモリセルと、選択トランジスタとがセルピラーを介して厚み方向に電気的に接続されたセルストリングを備え、
前記貫通電極の周囲に複数配置された前記セルストリングの各セルピラーと前記貫通電極とが電気的に接続されている
ことを特徴とする請求項1又は2に記載の半導体装置。 - 前記電気的接続構造は、前記メモリ半導体チップ及び前記平面バッファチップを厚み方向に貫通する前記貫通電極を介して前記メモリ半導体チップと前記平面バッファチップとの間を電気的に接続している
ことを特徴とする請求項1から請求項3のいずれか一項に記載の半導体装置。 - 前記メモリセルがNAND型フラッシュメモリセルである
ことを特徴とする請求項1から請求項4のいずれか一項に記載の半導体装置。
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JP2020005051A JP7340178B2 (ja) | 2020-01-16 | 2020-01-16 | 半導体装置 |
US17/147,658 US11437349B2 (en) | 2020-01-16 | 2021-01-13 | Semiconductor device |
US17/147,633 US11404396B2 (en) | 2020-01-16 | 2021-01-13 | Semiconductor device comprising memory semiconductor chip in which memory cell is laminated on semiconductor substrate |
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JP2019528546A (ja) | 2016-08-08 | 2019-10-10 | マイクロン テクノロジー,インク. | マルチデッキメモリデバイス及び操作 |
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KR100308479B1 (ko) | 1998-08-11 | 2001-11-01 | 윤종용 | 컴퓨터 시스템 내에서 부트-업 메모리로 사용되는 플래시 메모리 장치 및 그것의 데이터 읽기 방법 |
JP5280880B2 (ja) * | 2009-02-10 | 2013-09-04 | 株式会社日立製作所 | 半導体集積回路装置 |
KR102189757B1 (ko) | 2014-07-30 | 2020-12-11 | 삼성전자주식회사 | 반도체 메모리 장치, 이를 포함하는 메모리 시스템, 및 이의 동작 방법 |
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KR102601214B1 (ko) | 2016-05-16 | 2023-11-10 | 삼성전자주식회사 | 수직형 구조를 가지는 메모리 장치 및 이를 포함하는 메모리 시스템 |
KR20180001296A (ko) | 2016-06-27 | 2018-01-04 | 삼성전자주식회사 | 수직형 구조를 가지는 메모리 장치 |
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