JP7339935B2 - 半導体部材の製造方法及び半導体装置の製造方法 - Google Patents
半導体部材の製造方法及び半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 219
- 238000004519 manufacturing process Methods 0.000 title claims description 53
- 239000012535 impurity Substances 0.000 claims description 109
- 238000000034 method Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- 239000007789 gas Substances 0.000 description 33
- 230000008859 change Effects 0.000 description 25
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- 238000012937 correction Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000003085 diluting agent Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000005046 Chlorosilane Substances 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- UOALEFQKAOQICC-UHFFFAOYSA-N chloroborane Chemical compound ClB UOALEFQKAOQICC-UHFFFAOYSA-N 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000002484 cyclic voltammetry Methods 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Description
図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
本願明細書と各図において、既に説明したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
以下の説明及び図面において、n+、n-及びp+、p、p-の表記は、各不純物濃度の相対的な高低を表す。すなわち、「+」が付されている表記は、「+」及び「-」のいずれも付されていない表記よりも不純物濃度が相対的に高く、「-」が付されている表記は、いずれも付されていない表記よりも不純物濃度が相対的に低いことを示す。これらの表記は、それぞれの領域にp形不純物とn形不純物の両方が含まれている場合には、それらの不純物が補償しあった後の正味の不純物濃度の相対的な高低を表す。
以下で説明する各実施形態について、各半導体領域のp形とn形を反転させて各実施形態を実施してもよい。
図1に表した半導体装置100は、n+形(第1導電形)ドレイン領域1、n-形ドリフト領域2、p-形(第2導電形)ピラー領域3、p形ベース領域4、n+形ソース領域5、p+形コンタクト領域6、ゲート電極10、ドレイン電極21、及びソース電極22を含む。
ドレイン電極21に、ソース電極22に対して正の電圧が印加された状態で、ゲート電極10に閾値より高い電圧を印加する。p形ベース領域4にチャネル(反転層)が形成される。電子は、チャネル及びn-形ドリフト領域2を通ってドレイン電極21へ流れる。これにより、半導体装置100がオン状態になる。その後、ゲート電極10に印加される電圧が閾値よりも低くなると、p形ベース領域4におけるチャネルが消滅し、半導体装置100がオフ状態になる。
n+形ドレイン領域1、n-形ドリフト領域2、p-形ピラー領域3、p形ベース領域4、n+形ソース領域5、及びp+形コンタクト領域6は、半導体材料として、シリコン、炭化シリコン、及び窒化ガリウムからなる群より選択された少なくとも1つを含む。半導体材料としてシリコンが用いられる場合、n形不純物として、ヒ素、リン、またはアンチモンを用いることができる。p形不純物として、ボロンを用いることができる。
ゲート電極10は、ポリシリコンなどの導電材料を含む。ゲート絶縁層10a及び絶縁層15は、酸化シリコンなどの絶縁材料を含む。ドレイン電極21及び第2金属層22bは、銅、アルミニウムなどの金属を含む。第1金属層22aは、チタン、窒化チタン、タングステンなどの、バリアメタルとして機能する金属を含む。
図2及び図3は、実施形態に係る半導体部材の製造方法を表す断面図である。
n+形半導体層1a及びn-形半導体層2a(第1半導体層)を含む半導体基板Subを用意する。n-形半導体層2aは、n+形半導体層1aの上に設けられている。半導体基板Subは、n+形半導体層1aを含まず、n-形半導体層2aのみを含んでも良い。n+形半導体層1aからn-形半導体層2aに向かう方向は、Z方向に平行である。n-形半導体層2aの上面は、X方向及びY方向に平行である。半導体基板Subの熱酸化又は化学気相堆積(CVD)により、図2(a)に表したように、n-形半導体層2aの上面に絶縁層IL1(第1層)を形成する。
1つ目の方法では、p-形半導体層3aを形成する際に、第2ガスの流量を調整する。質量差が大きいほど、第2ガスの流量を小さくする。流量に代えて圧力を調整しても良い。例えば、質量差が大きいほど、p-形半導体層3aを形成する空間における第2ガスの圧力を低くする。流量が大きいほど、又は圧力が高いほど、形成される半導体層へのp形不純物の供給量が増大する。これにより、p-形半導体層3aにおけるp形不純物濃度を変化させることができる。
2つ目の方法では、最初に、p形不純物を含む不純物層を開口OP1の内壁に沿って形成する。次に、アンドープ又はp形不純物濃度の低い半導体層を開口OP1の内部に形成する。その後、熱処理により、不純物層から、アンドープ又は低濃度の半導体層にp形不純物が拡散することで、p-形半導体層3aが形成される。不純物層を形成する際に、質量差に応じて、第2ガスの流量を調整することで、p-形半導体層3aにおけるp形不純物濃度を変化させることができる。
第2ガスの流量又は圧力の調整に代えて、希釈ガス又はエッチングガスの流量又は圧力を調整しても良い。希釈ガスとして、水素ガスを用いることができる。
又は、第2ガスの流量又は圧力の調整に加えて、希釈ガス又はエッチングガスの流量又は圧力を調整しても良い。
まず、上述した半導体部材の製造方法により、n-形半導体層2a及びp-形半導体層3aを含む半導体部材を製造する。絶縁層IL1を除去する。化学機械研磨(CMP)により、n-形半導体層2a及びp-形半導体層3aの上面を平坦化する。n-形半導体層2aの上面及びp-形半導体層3aの上面にp形不純物をイオン注入し、p形半導体領域4a(第1半導体領域)を形成する。フォトリソグラフィ及びRIEにより、図4(a)に表したように、n-形半導体層2aの上に開口OP3を形成する。開口OP3は、p形半導体領域4aを貫通し、n-形半導体層2aに達する。開口OP3は、X方向において複数形成される。各開口OP3は、Y方向に延伸している。
上述したように、半導体装置100がオフ状態のとき、n-形ピラー領域2nとp-形ピラー領域3のpn接合面から、X方向に沿って空乏層が広がる。n-形ピラー領域2n及びp-形ピラー領域3が空乏化することで、半導体装置100の耐圧が向上する。n-形ピラー領域2n及びp-形ピラー領域3の空乏化を促進させるためには、n-形ピラー領域2nに含まれるn形不純物の量と、p-形ピラー領域3に含まれるp形不純物の量と、の間の不純物量差が小さいことが好ましい。n-形ピラー領域2nの幅(X方向における長さ)、n-形ピラー領域2nにおけるn形不純物濃度、p-形ピラー領域3の幅、及びp-形ピラー領域3におけるp形不純物濃度は、当該差が小さくなるように設計される。
実施形態に係る製造方法では、第1質量、第2質量、及び開口OP2の幅を測定する。参考例に係る製造方法では、開口OP2の幅のみを測定し、第1質量又は第2質量は測定しない。
半導体装置の製造過程において、開口OP2の幅を測定する。p-形半導体層3aは、公称流量で第2ガスを供給して形成される。製造された半導体装置の電気特性から、n-形半導体層2aに含まれるn形不純物量とp-形半導体層3aに含まれるp形不純物量の比が算出できる。具体的には、製造された半導体装置について、ゲート電極10に電圧を印加していないときの耐圧値(ブレークダウンボルテージ)と、ゲート電極10に電圧を印加したときの耐圧値と、を測定し、これらの比を測定する。過去の量産データにおいて得られた、当該比に関するシミュレーション結果を参照する。シミュレーション結果から、当該比に対応する、n-形半導体層2aに含まれるn形不純物量とp-形半導体層3aに含まれるp形不純物量との比を得る。これを実測値とする。実測値は、(Np/Nn-1)の数式で、単位%で表すことができる。プラスの符号は、p形不純物量がn形不純物量よりも多い状態を表す。マイナスの符号は、n形不純物量がp形不純物量よりも多い状態を表す。
半導体装置の製造過程において、第1質量、第2質量、及び開口OP2の幅を測定する。p-形半導体層3aは、公称流量で第2ガスを供給して形成される。製造された半導体装置の電気特性から、n-形半導体層2aに含まれるn形不純物量とp-形半導体層3aに含まれるp形不純物量の比が算出できる。これを実測値とする。
第1変化量及び第2変化量に対応した流量で第2ガスを供給したときの、n-形半導体層2aにおけるn形不純物量及びp-形半導体層3aにおけるp形不純物量を予測する。(Np1/Nn1-1)で表される不純物量比の予測値を算出する。
Claims (6)
- 第1導電形の第1半導体層を含む半導体基板の第1質量を測定し、
前記第1半導体層の上面に第1開口を形成し、
前記第1開口が形成された前記半導体基板の第2質量を測定し、
前記第1開口の内部に第2導電形の第2半導体層を形成する際に、前記第2半導体層における第2導電形の不純物濃度を、前記第1質量と前記第2質量との質量差に応じて変化させる、半導体部材の製造方法。 - 前記第1開口の形成において、
前記第1開口が形成される位置に対応して設けられた第2開口を有する第1層を、前記上面の上に形成し、
前記上面に沿う第1方向における前記第2開口の長さを測定し、
前記第1層をマスクとして用いて前記第1開口を形成し、
前記第2半導体層を形成する際に、前記第2半導体層における第2導電形の前記不純物濃度を、さらに前記長さに応じて変化させる、請求項1記載の半導体部材の製造方法。 - 前記第2半導体層は、半導体材料を含む第1ガスと、第2導電形の不純物を含む第2ガスと、を前記半導体基板に供給して形成され、
前記第2半導体層を形成する際に、前記第2ガスの流量又は圧力を前記質量差に応じて変化させることで、前記第2半導体層における第2導電形の前記不純物濃度を変化させる、請求項1又は2に記載の半導体部材の製造方法。 - 前記第1開口は、前記上面に沿う第1方向において複数形成される、請求項1~3のいずれか1つに記載の半導体部材の製造方法。
- 前記第1半導体層及び前記第2半導体層は、シリコン、炭化シリコン、及び窒化ガリウムからなる群より選択される少なくとも1つを含む請求項1~4のいずれか1つに記載の半導体部材の製造方法。
- 請求項1~5のいずれか1つに記載の半導体部材の製造方法を実施し、
前記第1半導体層の前記上面及び前記第2半導体層の上面に、第2導電形の第1半導体領域を形成し、
前記第1半導体層の上にゲート電極を形成し、
前記第1半導体領域の上面に第1導電形の第2半導体領域を形成し、
前記第2半導体領域の上に、前記第2半導体領域と電気的に接続される第1電極を形成し、
前記第1半導体層の下に、前記第1半導体層と電気的に接続される第2電極を形成する、半導体装置の製造方法。
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