JP7338991B2 - Wiring board with support, electronic component package with support, and manufacturing method thereof - Google Patents

Description

TECHNICAL FIELD The present invention relates to a wiring board with a support, an electronic component package with a support, and a method for manufacturing these.

In recent years, along with the miniaturization and thinning of electronic equipment, thin package substrates for mounting semiconductor elements (hereinafter sometimes referred to as package substrates) for mounting semiconductor elements for these electronic equipment are being used. there is Moreover, the thickness of the semiconductor package itself, in which a semiconductor element is mounted on such a package substrate, tends to be thin.

As a semiconductor package corresponding to such thinning, there is known a semiconductor package with a support substrate by mounting a semiconductor element using a package substrate with a support substrate (Patent Documents 1 to 3). .

JP 2003-218524 A JP 2011-228613 A JP 2013-138115 A

By using a semiconductor package with a support substrate, it is possible to suppress warpage during mounting even if the package is thin. However, it is necessary to separate the support substrate in order to produce a semiconductor package used when assembling electronic equipment. In addition, in order to be able to mount a single semiconductor package after separating the supporting substrate into an electronic device by soldering, etc., the mounting surface of the semiconductor package (the back side of the semiconductor element mounting surface) must be placed on an insulating layer. It is desirable to form a solder resist. Moreover, it is desirable that protective plating is formed on the mounting terminals.

In Patent Documents 1 and 2, the support substrate is separated by peeling at the interface between the carrier of the metal foil with the carrier and the metal foil. At this time, since the metal foil of the metal foil with the carrier remains on the surface of the semiconductor package, it is removed by etching. Then, what is exposed on the surface (mounting surface) is the adhesive layer and conductors (conductor posts, conductor patterns, and conductive vias). Therefore, in order to mount the semiconductor package separated from the support substrate on the electronic device, it is necessary to form a solder resist or a protective plating on the mounting surface.

In Patent Document 3, similarly to Patent Documents 1 and 2, the support substrate is separated by peeling at the interface between the carrier of the metal foil with the carrier and the metal foil. Further, an example is described in which the solder resist appears on the mounting surface of the semiconductor package separated from the supporting substrate. However, the solder resist in this case is collectively formed so as to serve also as an insulating layer for the inner layer wiring. In this case, the thickness of the solder resist (insulating layer) should be sufficiently thick so that it can flow and follow the unevenness of the surface wiring pattern, and the thickness of the solder resist, which also serves as an insulating layer, should be ensured. There is a need to. For this reason, the thickness of the solder resist, which also serves as an insulating layer, tends to vary due to unevenness and density of the pattern, and there is a problem that it is difficult to meet the demand for thinning.

The present invention has been made in view of the above problems, and it is possible to suppress the warpage during mounting even if the package is thin, and the step of mounting the electronic component package after the separation of the support on the electronic device is eliminated. An object of the present invention is to provide a wiring board with a support, an electronic component package with a support using the wiring board, and a method for manufacturing these, which can be simplified.

The present invention relates to the following.
[1] A support layer, and a multi-layered metal foil disposed on at least one of the front and back surfaces of the support layer, wherein a plurality of layers of metal foil are laminated in such a manner that they can be peeled off at the boundary between at least any of the metal foils; a support, a solder resist and a wiring pattern arranged on the multilayer metal foil of the support, and an insulating layer arranged on the solder resist and the wiring pattern; A wiring board with a support.
[2] The wiring board with a support according to [1] above, wherein the wiring pattern has a protective plating disposed on the side of the multilayer metal foil.
[3] The boundary between the peelable metal foils in the multilayer metal foil of the support is at least between the first metal foil on which the solder resist and the wiring pattern are arranged and the adjacent second metal foil. The wiring board with support according to the above [1] or [2], which is provided at the boundary.
[4] The wiring board with support according to any one of [1] to [3] above, and an electronic component element disposed on the surface of the wiring board with support opposite to the support. An electronic component package with a support, comprising:
[5] A step (A) of forming a solder resist and a wiring pattern on a multilayer metal foil provided on a support, and a step of forming a wiring board provided with the solder resist and the wiring pattern on at least one of front and back surfaces. (B) and a method for manufacturing a wiring board with a support.
[6] The method for producing a wiring board with a support according to [5] above, wherein in the step (A), a protective plating is formed on the multilayer metal foil side of the wiring pattern.
[7] A method for manufacturing an electronic component package with a support, comprising a step (C) of arranging an electronic component element on a surface of the wiring board with a support opposite to the support after the step (B). .
[8] After the step (C), the electronic component has a step (D) of separating the support and the electronic component package by peeling at the boundary between the metal foils of the multilayer metal foil on the support. How the package is made.

According to the present invention, a support that is capable of suppressing warpage during mounting even if it is thin and that simplifies the process of mounting an electronic component (semiconductor) package on an electronic device after separating the support. It is possible to provide a wiring board with a support, an electronic component package with a support using the same, and a method of manufacturing these.

1 is a cross-sectional view showing a wiring board with a support according to Embodiment 1 of the present invention; FIG. 2 is a partially enlarged view of FIG. 1; 1 is a cross-sectional view showing an electronic component package with a support (semiconductor package with a support) according to Embodiment 1 of the present invention; FIG. FIG. 4 is a cross-sectional view showing a manufacturing process of the wiring board with support according to Embodiments 1 and 2 of the present invention. FIG. 4 is a cross-sectional view showing a manufacturing process of the wiring board with support according to Embodiments 1 and 2 of the present invention. FIG. 4 is a cross-sectional view showing a manufacturing process of the wiring board with support according to Embodiments 1 and 2 of the present invention. FIG. 4 is a cross-sectional view showing a manufacturing process of the electronic component package with support according to Embodiments 1 and 2 of the present invention; FIG. 4 is a cross-sectional view showing a manufacturing process of the electronic component package with support according to Embodiments 1 and 2 of the present invention; It is sectional drawing which shows the manufacturing process of the electronic component package of the modification 1 of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the electronic component package of the modification 2 of Embodiment 1 of this invention. FIG. 4 is a cross-sectional view showing a wiring board with a support according to Embodiment 2 of the present invention; FIG. 12 is a partially enlarged view of FIG. 11; FIG. 4 is a cross-sectional view showing an electronic component package with a support (semiconductor package with a support) according to Embodiment 2 of the present invention; FIG. 4 is a cross-sectional view showing a manufacturing process of an electronic component package with a support (semiconductor package with a support) according to Embodiment 2 of the present invention;

DETAILED DESCRIPTION OF THE INVENTION Embodiments for carrying out the present invention will be described in detail below. However, the present invention is not limited to the following embodiments. In the following embodiments, the constituent elements (including element steps and the like) are not essential unless otherwise specified. The same applies to numerical values and their ranges, which do not limit the present invention.
In the following embodiments, the term "process" includes a process that is independent of other processes, and even if it cannot be clearly distinguished from other processes, if the purpose of the process is achieved, the process is also included.
In the following embodiments, the numerical range indicated using "-" includes the numerical values before and after "-" as the minimum and maximum values, respectively.
In the following embodiments, the term "layer" includes the case where the layer is formed over the entire area when the area where the layer is present is observed, and the case where the layer is formed only in part of the area. Also included if any.

[Embodiment 1]
(Wiring board with support)
1 and 2 show a wiring board 1 with a support according to Embodiment 1, which is an example of the present invention. The wiring board 1 with a support of the present embodiment is arranged on at least one of the support layer 33 and the front and back surfaces of the support layer 33, and a plurality of layers of metal foil can be separated at least at the boundary between the metal foils. a multilayer metal foil 31 laminated in a state; a solder resist 8 and a wiring pattern 5 arranged on the multilayer metal foil 31 of the support 3; and an insulating layer 7 arranged on the wiring pattern 5 .

A wiring board 1 with a support is a wiring board 2 having a support 3 . A wiring board 1 with a support of the present embodiment includes a package board 2 as the wiring board 2 and is also referred to as a package board 1 with a support. The package substrate 2 constitutes a semiconductor package (electronic component package) 19 by mounting an electronic component element 11 such as a semiconductor element. The wiring board 2 is not limited to the package board 2 on which a semiconductor element is mounted. good.

(support)
The support 3 increases the rigidity of the wiring board 2 and suppresses warping in the manufacturing process of the wiring board 2 or the mounting process of the semiconductor element. As shown in FIGS. 1 and 2, the support 3 is arranged on a support layer 33 and on the front and rear surfaces of the support layer 33 (only the front surface in FIGS. 1 and 2), and a plurality of layers of metal foil are arranged between the metal foils. and a multi-layered metal foil 31 laminated in a detachable state at the boundary. In this embodiment, as the support layer 33, an insulating resin made of glass epoxy is used, and on one side thereof, a so-called peelable copper foil 31, which can be mechanically peeled off, is laminated as the multilayer metal foil 31 to form the support 3. A copper foil clad laminate is used. The support 3 includes the multilayer metal foil 31 on at least one of the front and back surfaces of the support layer 33, and can suppress warping of the wiring board 2 by increasing rigidity in the manufacturing process of the wiring board 2 or the mounting process of the semiconductor element. There is no particular limitation as long as it is a substance. As the support 3, a material and a structure generally used for manufacturing the wiring board 2 can be used. Here, the "boundary" includes the interface between the metal foils of the multilayer metal foil 31 or the interface between the release layer 313 and the metal foil and the release layer itself when the metal foils are laminated via the release layer.

The support layer 33 used for the support 3 increases rigidity and holds the multilayer metal foil 31 in close contact. In the present embodiment, a prepreg that is in a semi-cured state by impregnating a glass fiber that is a reinforcing material with an epoxy resin that is a thermosetting resin composition having good heat resistance and chemical resistance is cured by heating and pressing. A so-called glass epoxy resin is used for the support layer 33, but the material is not limited to this. The material and formation method are not limited as long as the multilayer metal foil 31 is held in close contact. For example, a semi-cured resin film that does not have a reinforcing material such as glass fiber may be used and similarly cured by heating and pressurizing, and a thermosetting resin composition in a varnish state is applied, dried and cured. You may let Further, as the thermosetting resin composition, in addition to the epoxy resin used in the present embodiment, one or two types of resin such as phenol resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, fluorine resin, etc. A mixture of the above may be used. The support layer 33 may be formed by photolithography using a photosensitive resin composition.

The support layer 33 made of glass epoxy according to the present embodiment has a thickness of 0.5 mm by stacking five 0.1 mm-thick prepregs and laminating them under heat and pressure. The thickness of the support layer 33 used for the support 3 is not particularly limited as long as the support 3 formed together with the multilayer metal foil 31 can increase the rigidity of the wiring board 2 and suppress warpage. As the thickness of the support layer 33, for example, 0.01 to 1 mm is used.

The multilayer metal foil 31 used for the support 3 is formed by laminating a plurality of layers of metal foils in a detachable state at the boundaries between the metal foils. In the present embodiment, as such a multilayer metal foil 31, two layers of copper foil, an ultra-thin copper foil 311 (first metal foil 311) and a carrier copper foil 312 (second metal foil 312), are provided. A so-called peelable copper foil (multilayer metal foil 31) that can be mechanically peeled off at a boundary 313 between the thin copper foil 311 and the carrier copper foil 312 is used. In the present embodiment, a peelable copper foil is used as the multilayer metal foil 31, with the ultra-thin copper foil 311 having a thickness of 3 μm and the carrier copper foil 312 having a thickness of 9 μm. As the peelable copper foil, the thickness of the ultra-thin copper foil 311 is 1 to 10 μm, and the thickness of the carrier copper foil 312 is 5 to 35 μm. Can be selected together.

As shown in FIGS. 1 and 2, in this embodiment, the carrier copper foil 312 side of the peelable copper foil (multilayer metal foil 31) provided with two layers of copper foil, the ultra-thin copper foil 311 and the carrier copper foil 312, is , is arranged in close contact with one surface of the support layer 33 of the support 3 . As a result, when the peelable copper foil is separated, the thick carrier copper foil 312 is transferred to the support 3 side, and the thin ultra-thin copper foil 311 is transferred to the wiring board 2 side. Therefore, when it is necessary to remove the ultra-thin copper foil 311 that has migrated to the wiring board 2 side, it can be easily removed by quick etching with a thickness of 10 μm or less.
Conversely, the ultra-thin copper foil 311 side may be placed in close contact with one surface of the support layer 33 of the support 3 . As a result, the thick carrier copper foil 312 moves to the side of the wiring board 2 constituting the semiconductor package 19. Therefore, for example, by etching away the carrier copper foil 312 at locations corresponding to the external connection terminals 53, the package substrate is removed. 2 external connection terminals 53 can be formed to protrude more. At this time, by selecting the thickness of the carrier copper foil 312 to be used, the projection height of the external connection terminal 53 can be freely set.

The number of layers of the multilayer metal foil 31 is not particularly limited as long as a plurality of layers of metal foil are laminated in such a manner that they can be manually and mechanically separated at the boundaries between the metal foils. For example, the multilayer metal foil 31 is not limited to two layers, and may have three or more layers. Here, the number of layers of the multilayer metal foil 31 is the number of layers when the thickness direction is divided by the boundary (separation layer) 313 that can be peeled off. For example, if the multilayer metal foil 31 has two layers, there is one peelable boundary 313 , and if the multilayer metal foil 31 has three layers, there are two peelable boundaries 313 . is one.

As shown in FIGS. 1 and 2, the boundary 313 between the peelable metal foils 311 and 312 in the multilayer metal foil 31 of the support 3 is at least the first layer on which the solder resist 8 and the wiring pattern 5 are arranged. It is provided at the boundary 313 between one metal foil 311 and the adjacent second metal foil 312 . In this embodiment, as the multilayer metal foil 31, two layers of the multilayer metal foil 31 of an ultra-thin copper foil 311 (first metal foil 311) and a carrier copper foil 312 (second metal foil 312) are used. Therefore, one peelable boundary 313 is provided at the boundary 313 between the ultra-thin copper foil 311 and the carrier copper foil 312 . For this reason, as shown in D-1 in FIG. 8, a boundary (hereinafter sometimes referred to as a peeling boundary) at which the support 3 is separated from the electronic component package 18 with the support (semiconductor package 18 with the support) ) is adjacent to the first metal foil 311 on which the solder resist 8 and the wiring pattern 5 are arranged, on the side opposite to the surface on which the solder resist 8 and the wiring pattern 5 are arranged (back side). It is set at the boundary 313 with the second metal foil 312 . As a result, as shown in D-2 of FIG. 8, FIGS. 9 and 10, the first metal foil 311 moves to the wiring substrate 2 (package substrate 2) side, so the first metal foil 311 is removed by etching. By doing so, the external connection terminals 53 of the wiring board 2 can be easily formed.

When using the multi-layer metal foil 31 of three or more layers, there are two or more peelable boundaries 313, but among the peelable boundaries 313, the support 3 is separated from the electronic component package 18 with the support. The boundary 313 that is peeled off when the first metal foil 311 is separated may be provided at the boundary 313 with a metal foil (not shown) that is not adjacent to the first metal foil 311 . Here, the metal foil that is not adjacent to the first metal foil 311 means that it is not the second metal foil 312 that is laminated adjacent to the first metal foil 311 . The metal foil 311 refers to the metal foil laminated on the opposite side.
As such an example, a case of using a three-layered multilayer metal foil 31 consisting of a first metal foil 311, a second metal foil 312, and a third metal foil (not shown) will be described. This multilayer metal foil 31 has two peelable boundaries 313 . Here, a separation boundary for separating the support 3 from the wiring substrate 1 with support (package substrate 1 with support) is set at the boundary between the second metal foil 312 and the third metal foil. Then, when the support 3 is separated by peeling at this separation boundary, both the first metal foil 311 and the second metal foil 312 move to the wiring substrate 2 (package substrate 2) side. Then, by peeling off the exposed second metal foil 312 of the transferred first metal foil 311 and the second metal foil 312, the surface of the second metal foil 312 is removed after the step of separating the support 3. It is possible to remove factors that lead to defects such as foreign matter and scratches adhering to the surface. Then, circuit processing such as etching can be performed using the first metal foil 311 from which the factors leading to defects have been removed. It becomes possible to form the wiring pattern 5 such as the external connection terminal 53 with few defects.

The peel strength at the peelable boundary of the multilayer metal foil 31 may be at a level at which manual mechanical peeling is possible, for example, 2 to 100 N/m.

The metal foil that constitutes the multilayer metal foil 31 is not particularly limited as long as it has electrical conductivity and can be removed by etching. Although copper foil is used in the present embodiment, there are other metal foils commonly used in wiring boards, such as copper foil, nickel foil, solder foil, and aluminum foil. etc.

As shown in FIGS. 1 and 2, the peelable copper foil (multilayer metal foil 31) used in this embodiment has a release layer 313 at the boundary 313 between the ultra-thin copper foil 311 and the carrier copper foil 312. there is The peeling layer 313 facilitates the mechanical peeling of the ultra-thin copper foil 311 and the carrier copper foil 312 and maintains them with appropriate peeling strength. Examples of the peeling layer 313 include those using an organic substance such as benzotriazole, metals such as chromium, copper, nickel, molybdenum, and tungsten, and oxides of these metals. Examples of such materials include those containing metal oxides of nickel and tungsten, metal oxides of nickel and molybdenum, and those made of Cu--Ni--Mo alloys. Since the peel strength is less likely to change due to heat history such as heating and pressurization in the manufacturing process of the wiring board 2, peeling is performed by distributing metals such as molybdenum and tungsten and their oxides while changing their compositions in a gradient manner. Layers are preferred. This is because the oxide-rich layer in one peeling layer exerts the peeling function, the metal-rich layer prevents the diffusion of copper to stabilize the peeling strength, and the composition changes in a gradient manner. , the mismatch of the thermal expansion coefficient, etc., and contributes to the stability of the peel strength. The thickness of this release layer 313 is preferably 40 to 50 nm.

In addition, when the ultra-thin copper foil 311 and the carrier copper foil 312 are separated, the release layer 313 is peeled off in a state of adhering to the metal foil side that moves to the support 3 side, and the metal that moves to the wiring board 2 side is removed. Desirably, it does not remain on the surface of the foil side. In this embodiment, a release layer 313 is formed on the ultra-thin copper foil 311 side remaining on the wiring substrate 2 (package substrate 2 for mounting a semiconductor element) so that the release layer 313 does not migrate. Thereby, it is possible to suppress the peeling layer 313 from affecting the circuit formability of the metal foil transferred to the wiring substrate 2 side.

(wiring board)
As shown in FIGS. 1 and 2, the wiring board 2 is arranged on the solder resist 8 and the wiring pattern 5 arranged on the multilayer metal foil 31 of the support 3, and on the solder resist 8 and the wiring pattern 5. and an insulating layer 7 . In this embodiment, three layers of wiring patterns 5, two layers of insulating layers 7 provided therebetween, and these insulating layers 7 (first insulating layer 71 and second insulating layer 72) are A wiring substrate 2 is used which has interlayer connections 6 (conductors 62) formed so as to electrically connect the wiring patterns 5 through each other. There is no particular limitation as long as the wiring board 2 is capable of mounting and supporting the electronic component element 11 by providing the support 3, and materials and structures used for the wiring board 2 can be used. . The wiring board 2 alone may warp in the mounting process for mounting the electronic component element 11 . For example, the wiring board 2 may have a total thickness of 0.15 mm or less.

The wiring board 2 of this embodiment will be described in more detail (see FIG. 3).
As shown in FIGS. 1 and 2, in the wiring board 2 of the present embodiment, the ultra-thin copper foil (multilayer metal foil 31) of the peelable copper foil (multilayer metal foil 31) on the side of the copper-clad laminate (support 3) serving as the support 3 A solder resist 8 and a wiring pattern 5 are formed on the foil 311 in close contact with each other. The solder resist 8 and the wiring pattern 5 are included in the configuration of the wiring board 2 rather than the configuration of the support 3 . Lands 53 provided on the wiring pattern 5 are external connection terminals 53 . Lines 51 and lands 52 are formed as the wiring pattern 5 on the insulating layer 7 (first insulating layer 71 ) formed in close contact with the solder resist 8 and the wiring pattern 5 . The land 52 is an internal connection terminal 52 and is electrically connected to the land 53 (external connection terminal 53 ) by an interlayer connection 6 formed through the first insulating layer 71 . Interlayer connection 6 (see FIG. 5, conductor 62 ) is formed by forming conductor 62 in interlayer connection hole 61 (see FIG. 5 ) formed in first insulating layer 71 . A non-through hole 61 formed by laser processing or the like, for example, can be used as the interlayer connection hole 61 . As the conductor 62, for example, a filled plating solution, which is a copper sulfate plating solution containing a predetermined additive, may be used to fill the interlayer connection hole 61 with copper plating. can. A second insulating layer 72 is formed on the lines 51 and the lands 52 on the first insulating layer 71, and the lines 51 and the lands 52 are formed as the wiring pattern 5 on the second insulating layer 72. ing. The land 52 is an internal connection terminal 52 and is electrically connected to the land 52 on the first insulating layer 71 by the interlayer connection 6 formed through the second insulating layer 72 .
Also, as shown in FIG. 3, the land 52 on the second insulating layer 72 is used to mount the electronic component element 11 such as a semiconductor element and to mount the electronic component (semiconductor) package 18 (electronic component package 19) with the support. It is used as an internal connection terminal 52 for connecting with the semiconductor element (electronic component element) 11 when forming. As shown in FIG. 3, the solder resist 8 may be formed on the wiring pattern 5 so that the land 52 that becomes the internal connection terminal 52 is exposed and the other wiring pattern 5 including the line 51 is protected. . Nickel/gold plating may be formed on the land 52 as the protective plating 54 . Preliminary solder 10 for connecting to the semiconductor element 11 may be formed on the lands 52 to be used as the internal connection terminals 52, for example, on the lands 52 for flip chip connection.

The solder resist 8 protects the surface of the wiring board 2 , and remains on the surface of the wiring board 2 to constitute the wiring board 2 even after the wiring board 2 and the support 3 are separated, as will be described later. It is something to do. There is no particular limitation as long as it has solder heat resistance, chemical resistance, etc. when mounting the semiconductor element 11 on the wiring board 2 or mounting the wiring board 2 itself on an electronic device, and the package substrate for mounting the semiconductor element 2 can be used. In this embodiment, a photosensitive solder resist is used to adhere to the surface of the multilayer metal foil 31 (the surface of the ultra-thin copper foil 311) of the support 3 to form the solder resist 8 in a predetermined pattern. Specifically, first, a liquid photosensitive photosolder resist ink was applied to the surface of the ultra-thin copper foil 311 of the multilayer metal foil 31 by screen printing. Next, after drying the solvent, the solder resist 8 is formed in close contact with the multilayer metal foil 31 by exposing it to ultraviolet light in a predetermined pattern and developing it. Although the thickness of the solder resist 8 at this time is 10 μm, it is not particularly limited and may be set according to the thickness of the wiring pattern 5 to be formed later. For example, it may be 5 to 30 μm.

The wiring pattern 5 of the wiring board 2 is for electrical connection and includes lines 51 , internal connection terminals 52 and external connection terminals 53 . In this embodiment, external connection terminals 53 are provided in the gaps of solder resist 8 formed in a predetermined pattern by adhering to the surface of multilayer metal foil 31 (surface of ultrathin copper foil 311) of support 3. A wiring pattern 5 is formed. More specifically, by using the multilayer metal foil 31 as a power supply layer and the previously formed solder resist 8 as a plating resist, pattern electroplating is performed using a copper sulfate plating bath to form a A closely attached wiring pattern 5 is formed. At this time, the thickness of the wiring pattern 5 (thickness of the copper electroplating pattern) is made equal to the thickness of the solder resist 8 (5 to 30 μm). As a result, the height of the surface of the wiring pattern 5 and the solder resist 8 become approximately the same, and the difference in level is reduced. Therefore, even if the insulating layer 7 is thin and has low fluidity, the thickness can be kept uniform, and electric properties such as insulating properties can be ensured.

The insulating layer 7 of the wiring board 2 insulates the gaps between the wiring patterns 5 in the same wiring layer or the gaps between the wiring patterns 5 in different wiring layers. In this embodiment, the insulating layer 7 is arranged both on the solder resist 8 and on the wiring pattern 5 . Specifically, it is formed so as to cover the entire surface, straddling over the solder resist 8 and the wiring pattern 5 formed so as to fill the gap. As the insulating layer 7, as described above, since it may be thin and has low fluidity, glass epoxy with a thickness of 10 to 100 μm can be used. Therefore, the thickness of the wiring board 2 itself can be made thinner. Although glass epoxy is used as the insulating layer 7 in this embodiment, it is not limited to this. A material and a manufacturing method similar to those of the support layer 33 described above can be used.

(Semiconductor package with support)
As shown in FIG. 3, the semiconductor package with support 18 of the present embodiment includes the wiring substrate with support 1 described above (package substrate with support 1) and the support 3 of the wiring substrate with support 1. As shown in FIG. and an electronic component element 11 (semiconductor element 11) disposed on the surface opposite to the (copper-clad laminate 3).

In this embodiment, two semiconductor elements 11 are stacked and electrically connected to each other. The number of semiconductor elements 11 is not limited to two, and may be one, or three or more may be stacked. Moreover, the arrangement in the case of a plurality is not limited to lamination, and may be arranged side by side.
A flip-chip terminal 111 is arranged under the semiconductor element 11 in the lower layer, and is flip-chip connected to the internal connection terminal 52 of the package substrate 1 with the support body 1 by the reflowed preliminary solder 10 . The method of connecting the underlying semiconductor element 11 and the internal connection terminals 52 of the package substrate 1 with support is not limited to flip-chip connection, and other methods such as wire bond connection, which will be described later, may be used. In the case of wire bond connection, the lower semiconductor element 11 is made slightly larger than the upper semiconductor element 11, and the lower semiconductor element 11 protrudes from the upper semiconductor element 11 (periphery of the lower semiconductor element 11). It is conceivable to provide a flip-chip terminal 111 on top of the element 11 . An underfill material 12 is filled in the gap between the semiconductor element 11 in the lower layer and the package substrate 1 with support. As for the underfill material 12 , the mold resin 14 may be filled in the gap between the underlying semiconductor element 11 and the package substrate 1 with the supporting member during molding to be described later.
A wire bond terminal 112 is arranged on the upper semiconductor element 11 and is wire-bonded to the internal connection terminal 52 of the package substrate 1 with the support by the bonding wire 13 .
A semiconductor element 11 mounted on a package substrate 1 with a support is molded with a molding resin 14 so as to include bonding wires 13 to form a semiconductor package 18 with a support integrated with the package substrate 1 with a support.

(Method for manufacturing wiring board with support)
4 to 6 show a method of manufacturing the wiring board 1 with a support according to Embodiment 1, which is an example of the present invention. The method for manufacturing a wiring board 1 with a support according to the present embodiment comprises a step (A) of forming a solder resist 8 and a wiring pattern 5 on a multilayer metal foil 31 provided on a support 3; and a step (B) of forming a wiring board 2 having wiring patterns 5 on at least one of the front and back surfaces. A method for manufacturing the wiring board 1 with a support according to the present embodiment will be described in detail below.

(Step (A))
As shown in A-1 of FIG. 4, a copper-clad laminate is prepared as a support 3. As shown in FIG. This copper-clad laminate has a 0.5 mm-thick glass epoxy resin (supporting layer 33) (a glass-epoxy insulating material) obtained by stacking five 0.1 mm-thick prepregs and heating and pressurizing them as the supporting layer 33. resin) is used. A multilayer metal foil 31 is arranged on one side of the support layer 33 (upper surface in FIG. 4), and a single-layer metal foil 32 is arranged on the other side (lower surface in FIG. 4). When the support layer 33 is formed, the multilayer metal foil 31 and the metal foil 32 are adhered to the respective surfaces of the support layer 33 by overlapping them together with the prepreg and applying heat and pressure. The multilayer metal foil 31 includes two layers of copper foil, an ultra-thin copper foil 311 (first metal foil 311) and a carrier copper foil 312 (second metal foil 312). A so-called peelable copper foil 31 that can be mechanically peeled off at a boundary 313 with 312 is used. In this embodiment, the ultra-thin copper foil 311 has a thickness of 3 μm, and the carrier copper foil 312 has a thickness of 9 μm, and the peelable copper foil 31 is used. The carrier copper foil 312 side of the peelable copper foil 31 is adhered to the glass epoxy resin (support layer 33).

As shown in A-2 of FIG. 4, a solder resist 8 is formed on the peelable copper foil 31 (more specifically, on the ultra-thin copper foil 311) provided on the copper-clad laminate (support 3). The solder resist 8 was formed by applying a liquid photosensitive photosolder resist ink onto the ultra-thin copper foil 311 by screen printing. Next, after drying the solvent, the solder resist 8 was formed in close contact with the ultra-thin copper foil 311 by exposing it to ultraviolet light in a predetermined pattern and developing it. The pattern of the solder resist 8 at this time is a reverse pattern (negative pattern) of the wiring pattern 5 to be formed later, and has a thickness of 10 μm.

As shown in A-3 of FIG. 4, a wiring pattern 5 is formed on an ultra-thin copper foil 311 provided on a copper-clad laminate (support 3). Wiring patterns 5 to be external connection terminals 53 are formed in gaps between solder resists 8 which are adhered to the surface of the ultra-thin copper foil 311 of the support 3 and formed in a predetermined pattern. Specifically, the peelable copper foil 31 is used as a power supply layer, the previously formed solder resist 8 is used as a plating resist, and a copper sulfate plating bath is used to form a pattern plating, thereby adhering to the ultra-thin copper foil 311 . A wiring pattern 5 is formed. At this time, the thickness of the wiring pattern 5 (thickness of the copper electroplating pattern) is made equal to the thickness of the solder resist 8 (10 μm). The surface heights of the wiring pattern 5 and the solder resist 8 are approximately the same, and the steps are reduced. For this purpose, a method of etching, polishing, or the like to match the heights of the wiring pattern 5 and the solder resist 8 may be used.

(Step (B))
As shown in B-1 of FIG. 5, a glass epoxy resin serving as a first insulating layer 71 and a copper foil 16 serving as a conductor layer 16 are arranged over the wiring pattern 5 and the solder resist 8. As shown in FIG. Specifically, one sheet of prepreg with a thickness of 0.05 mm and a copper foil 16 with a thickness of 9 μm are superimposed thereon and heated and pressed.

As shown in B-2 of FIG. 5, an opening 17 is formed in the copper foil 16, and an interlayer connection hole 61 is formed in the glass epoxy resin (first insulating layer 71). Specifically, the surface of the copper foil 16 is subjected to a surface treatment (roughening treatment) for facilitating the absorption of laser light, and then the openings 17 are formed in the copper foil 16 by laser processing and glass epoxy resin is applied. (First insulating layer 71) is removed, and non-through holes 61, which are interlayer connection holes 61, are formed so as to reach wiring patterns 5 (lands 53) formed by pattern plating. Thus, in this embodiment, a so-called direct laser construction method is used. The processing method is not limited, and a so-called conformal mask method is used in which openings 17 are formed in copper foil 16 by etching, and interlayer connection holes 61 are formed in glass epoxy resin using copper foil 16 as a mask for laser processing. may

As shown in B-3 of FIG. 5, a conductor 62 is formed in the interlayer connection hole 61, and the surface conductor layer 16 (copper foil 16) and the wiring pattern 5 (land 53) formed by pattern plating are electrically connected. connected to each other. Specifically, first, the surface of the copper foil 16 is etched to remove the surface treatment layer (roughened layer) and laser processing residue. Next, the wiring pattern 5 (land 53) on the inner wall and bottom surface of the interlayer connection hole 61 is subjected to a so-called desmear treatment to remove laser processing residues and the like. Alkaline permanganate treatment, plasma treatment, and the like, which are generally used in the production of wiring boards, can be used for the desmear treatment. Next, electroless plating for thin attachment (hereinafter sometimes referred to as “electroless plating”) is formed as a base. Next, using this as a power supply layer, a fill plating 62 in which the inside of the interlayer connection hole 61 is filled with copper plating is formed by electroplating. The filled plating 62 is performed using a filled plating solution which is a copper sulfate plating solution containing a predetermined additive. A filled plating solution is generally a copper sulfate plating solution to which a plating inhibitor for suppressing plating growth and a plating accelerator for promoting plating growth are added. As these predetermined additives, those generally used in the manufacturing method of wiring substrates can be used.

As shown in B-4 of FIG. 5, the surface conductor layer 16 is etched to form a wiring pattern 5 (lines 51 and lands 52). The above-described fill plating 62 tends to deposit not only inside the interlayer connection hole 61 but also on the surface conductor layer 16 (copper foil 16). In order to miniaturize the wiring pattern 5 (lines 51 and lands 52) formed by etching the surface conductor layer 16, it is advantageous to reduce the thickness of the surface conductor layer 16. FIG. For this purpose, a method of thinning the surface conductor layer 16 by etching the entire surface so as to have a predetermined thickness can be used. In this embodiment, the wiring pattern 5 is formed by etching after etching the entire surface so that the surface conductor layer 16 has a thickness of 9 μm, after forming an etching resist.

As shown in B-5 of FIG. 6, a second insulating layer 72 (glass epoxy resin) and wiring patterns are formed on the first insulating layer 71 (glass epoxy resin) and wiring patterns 5 (lines 51 and lands 52). 5 (line 51, land 52). This method is the same as B-1 to B-4 in FIG. 5 described above.

As shown in B-6 of FIG. 6, on the second insulating layer 72 (glass epoxy resin) and the wiring pattern 5 (lines 51, lands 52), portions used for connection with the semiconductor element 11 (internal connection terminals 52) and the like are removed to form a solder resist 8. As shown in FIG. The solder resist 8 can be formed in the same manner as in A-2 of FIG. 4, using a liquid photosensitive photosolder resist ink. Internal connection terminals 52 (lands 52) used for connection with an electronic component element 11 (semiconductor element 11) to be described later have a portion (at least part of the internal connection terminal 52) used for connection with the semiconductor element 11 from the solder resist 8. , are exposed from the solder resist 8 .

As shown in B-7 of FIG. 6, protective plating 54 is formed on the internal connection terminals 52 (lands 52) exposed from the solder resist 8. As shown in FIG. Specifically, first, nickel plating is formed on the internal connection terminals 52 . Nickel plating such as electroless nickel plating and electric nickel plating can be used to form the nickel plating. The thickness of nickel plating is generally 0.5 to 10 μm. Next, gold plating is formed on the nickel plating. Gold plating such as immersion gold plating, electroless gold plating, and electrogold plating can be used to form the gold plating. The thickness of gold plating is generally 0.01 to 1 μm. In addition, before forming the gold plating, the nickel plating may be plated with a noble metal such as palladium plating, and then the gold plating may be formed. In addition, in the present embodiment, the protective plating 54 as described above is used, but the surface of the copper foil forming the internal connection terminal 52 (land 52) is prevented from being oxidized to the extent that it interferes with the connection with the semiconductor element 11. The type of protective treatment is not limited to plating, provided that it is possible to do so. A copper foil surface protective treatment generally used for wiring substrates, such as solder and organic anticorrosive film, can be used.

Further, as shown in B-7 of FIG. 6, pre-solder 10 is formed on internal connection terminals 52 (lands 52) to be flip-chip connected to semiconductor element 11. Next, as shown in FIG. Specifically, preliminary solder 10 can be formed on internal connection terminals 52 by supplying solder paste and reflowing it using a printing method using a metal mask. The internal connection terminals 52 for flip-chip connection are arranged inside the semiconductor element 11 in plan view. The thickness of the preliminary solder 10 is, for example, 1 to 20 μm. As described above, the package substrate 1 with the support of the present embodiment can be manufactured.

(Method for manufacturing electronic component package with support)
FIG. 7 shows a method of manufacturing an electronic component package 18 with a support (semiconductor package 18 with a support) according to Embodiment 1, which is an example of the present invention. The method for manufacturing a semiconductor package 18 with a support according to the present embodiment includes, after the step (B), the step (C) of arranging a semiconductor element on the surface of the wiring board with a support on the side opposite to the support. have. A method for manufacturing the semiconductor package 18 with a support according to this embodiment will be described in detail below.

(Step (C))
As shown in C-1 of FIG. 7, the semiconductor element 11 is flip-chip connected onto the internal connection terminals 52 of the package substrate 1 with support. Specifically, flip chip terminals 111 for flip chip connection are provided under the semiconductor element 11 . The flip-chip terminals 111 are arranged so as to face the internal connection terminals 52 of the package substrate 1 with the supporting body to which the flux is applied. The flip-chip terminals 111 and the internal connection terminals 52 are soldered together by reflow soldering, in which the preliminary solder 10 is heated to a melting temperature.

As shown in C-2 of FIG. 7, an underfill material 12 is filled in the gap between the package substrate 1 with support member and the semiconductor element 11 . The underfill material 12 may be filled in the gap between the semiconductor element 11 and the package substrate 1 with the support body when the mold resin 14 is molded, which will be described later.

As shown in C-3 of FIG. 7, the semiconductor element 11 (upper layer) is further stacked on the semiconductor element 11 (lower layer), and the upper semiconductor element 11 and the package substrate 1 with the support are connected by wire bonding. do. Specifically, a wire bond terminal 112 is provided on the upper part of the semiconductor element 11 in the upper layer, and the wire bond terminal 112 and the internal connection terminal 52 of the package substrate 1 with support are connected by the bonding wire 13 . be. The internal connection terminals 52 of the package substrate 1 with wire bonding connection are internal connection terminals 52 that are not used for flip-chip connection, and are arranged outside the semiconductor element 11 in plan view.

As shown in C-4 of FIG. 7, the semiconductor element 11 mounted on the package substrate 1 with the support is molded with the mold resin 14 so as to include the bonding wires 13, and integrated with the package substrate 1 with the support. A semiconductor package 18 with a supporting body is formed. As described above, the semiconductor package 18 with a supporting body of the present embodiment is formed.

(Manufacturing method of electronic component package)
FIG. 8 shows a method of manufacturing an electronic component package 19 (semiconductor package 19) according to Embodiment 1, which is an example of the present invention. In the method for manufacturing the semiconductor package 19 of the present embodiment, after the step (C), the multilayer metal foil 31 on the support 3 is separated at the boundary 313 between the metal foils 311 and 312 to separate the support 3 and the A step (D) of separating the electronic component package 19 from the semiconductor package 19 is included. Details of the method for manufacturing the semiconductor package 19 of this embodiment will be described below.

(Step (D))
As shown in D-1 of FIG. 8, the peelable copper foil (composite metal foil 31) of the copper-clad laminate (support 3) is peeled at the boundary 313 between the ultra-thin copper foil 311 and the carrier copper foil 312. Thus, the copper foil-clad laminate (support 3) and the semiconductor package 19 are separated. At the boundary 313 between the ultra-thin copper foil 311 and the carrier copper foil 312, heat and pressure press when manufacturing the package substrate 1 with support, reflow when mounting the semiconductor element 11, and heating during molding. A peeling layer 313 is formed that can suppress variation in peeling strength even in thermal history such as pressure. According to this peeling layer 313, even after the thermal history as described above, the peeling strength is maintained at a level at which manual peeling is possible as in the beginning. In addition, since the release layer 313 is adjusted to be easily transferred to the copper foil-clad laminate side after the separation, the transfer to the surface of the ultra-thin copper foil 311 remaining on the package substrate 1 side with the support is prevented. Suppressed. Therefore, when the ultra-thin copper foil 311 is subjected to circuit processing such as etching, adverse effects of the release layer 313 on the circuit processing are suppressed.

As shown in D-2 of FIG. 8, the ultra-thin copper foil 311 remaining in close contact with the solder resist 8 and the pattern-plated wiring pattern 5 to be the external connection terminals 53 due to the separation in D-1 is removed. , are removed by etching on the entire surface, and the solder resist 8 is exposed. As a result, the semiconductor package 19 having the solder resist 8 and the external connection terminals 53 (wiring patterns 5) on the bottom surface can be obtained.

(Modification 1 of method for manufacturing electronic component package)
FIG. 9 shows Modification 1 of the method for manufacturing the electronic component package 19 (semiconductor package 19) of Embodiment 1, which is an example of the present invention. This modification 1 is the same as the above up to the separation of the support layer 3, part of the composite metal foil, and the semiconductor package 19 as shown in D-1 of FIG. The process is different. The details of Modification 1 of the method for manufacturing the semiconductor package 19 of the present embodiment will be described below.

(Step (D))
As shown in D-3 of FIG. 9, the ultra-thin copper foil 311 remaining in close contact with the solder resist 8 and the pattern-plated wiring pattern 5 to be the external connection terminals 53 due to the separation in D-1 is removed. A plating resist 20 is formed thereon while leaving it as it is. Next, as shown in D-4 of FIG. 9, the ultra-thin copper foil 311 remaining on the semiconductor package 19 side is used as a power supply layer, and a copper sulfate plating bath is used to form a pattern copper plating 21, thereby forming an ultra-thin copper foil 311. A copper bump 22 is formed on the thin copper foil 311 . Next, as shown in D-5 of FIG. 9, the plating resist 20 is removed, and then the entire surface is etched to remove the ultra-thin copper foil 311 remaining on the solder resist 8. expose the As a result, the semiconductor package 19 having the solder resist 8 and the copper bumps 22 as the external connection terminals 53 on the bottom surface can be obtained.

(Modification 2 of the method for manufacturing an electronic component package)
FIG. 10 shows Modification 2 of the method for manufacturing the electronic component package 19 (semiconductor package 19) of Embodiment 1, which is an example of the present invention. This modification 2 is the same as the above up to the separation of the support layer 3, part of the composite metal foil, and the semiconductor package 19 as shown in D-1 of FIG. The process is different. The details of Modified Example 2 of the method for manufacturing the semiconductor package 19 of the present embodiment will be described below.

(Step (D))
As shown in D-7 of FIG. 10, the ultra-thin copper foil 311 remaining in close contact with the solder resist 8 and the pattern-plated wiring pattern 5 to be the external connection terminals 53 due to the separation in D-1 is removed. An etching resist 23 is formed thereon while leaving it as it is. At this time, the etching resist 23 is formed in a pattern covering the region corresponding to the external connection terminal 53 (the wiring pattern 5 formed by pattern plating in A-3 of FIG. 4). Next, as shown in D-8 of FIG. 10, etching is performed to remove the ultra-thin copper foil 311 remaining on the solder resist 8 to expose the solder resist 8. Next, as shown in FIG. Next, the etching resist 23 is removed. As a result, the semiconductor package 19 having the solder resist 8 and the wiring pattern 5 (external connection terminals 53) on the bottom surface can be obtained.

(action/effect)
According to the wiring board 1 with the support or the electronic component (semiconductor) package 18 with the support of the present embodiment, the solder resist 8 and the wiring pattern 5 arranged on the multilayer metal foil 31 of the support 3 and the solder and an insulating layer 7 arranged over both the resist 8 and the wiring pattern 5 . Thereby, as described below, the insulating layer 7 can be formed separately after the solder resist 8 and the wiring pattern 5 are formed.
That is, first, after forming the solder resist 8 on the multilayer metal foil 31 of the support 3, pattern plating 15 can be performed using the multilayer metal foil 31 as a power supply layer and the solder resist 8 as a plating resist. At this time, the height of the surface of the solder resist 8 and the wiring pattern 5 can be made approximately the same to suppress the step due to the unevenness of the wiring pattern 5 .
Next, the insulating layer 7 is formed over both the solder resist 8 and the wiring pattern 5. Since the step due to the unevenness of the wiring pattern 5 is suppressed, the insulating layer 7 is made to flow following the step. No need. Therefore, even if the insulating layer 7 is thin and has low fluidity, the thickness can be kept uniform, and electric properties such as insulating properties can be ensured. As a result, the thickness of the wiring board 2 itself can be made thinner, and a separable support 3 can be provided.
Further, after separating the support 3 from the electronic component (semiconductor) package 18 with the support, the metal foil moved to the electronic component (semiconductor) package 18 with the support is removed by etching, or circuit processing is performed. The solder resist 8 and the wiring pattern 5 such as the external connection terminals 53 are formed only by performing a simple process.
Therefore, the wiring board 1 with the support or the support can simplify the process of mounting the electronic component package on the electronic device after the support 3 is separated, while making it possible to suppress warping during mounting even if the wiring board 1 is thin. An electronic component package 18 with a body can be provided.

[Embodiment 2]
(Wiring board with support)
11 and 12 show a wiring board 1 with a support according to Embodiment 2, which is an example of the present invention. In addition to the configuration of the wiring board 1 with a support of the first embodiment, the wiring board 1 with a support of the present embodiment further includes a protective plating in which the wiring pattern 5 is arranged on the multilayer metal foil 31 side. 54. The wiring board 1 with support according to the present embodiment will be described in detail below.

(support)
The support 3 used in the wiring board 1 with a support of this embodiment is the same as that of the first embodiment described above, so the description thereof is omitted.

(wiring board)
As shown in FIGS. 11 and 12, the wiring board 2 includes the solder resist 8 and the wiring pattern 5 arranged on the multilayer metal foil 31 of the support 3, and the solder resist 8 as in the first embodiment. and an insulating layer 7 arranged on the top and the wiring pattern 5 . In addition to the configuration of the first embodiment, the wiring board 2 of the second embodiment further includes a protective plating 54 arranged on the multilayer metal foil 31 side of the wiring pattern 5 . In other words, the protective plating 54 is disposed on the portion of the wiring pattern 5 that is in close contact with the multilayer metal foil 31 side. Other than this, it is the same as the wiring board 2 used in the first embodiment.

The wiring board 2 of this embodiment will be described in more detail. As shown in FIGS. 11 and 12, in the wiring board 2 of the present embodiment, on the ultra-thin copper foil 311 of the peelable copper foil (multilayer metal foil 31) on the side of the copper-clad laminate serving as the support 3, A solder resist 8 and a wiring pattern 5 are formed in close contact with each other. Nickel/gold plating as a protective plating 54 is disposed on the portion of the wiring pattern 5 that is in close contact with the multilayer metal foil 31 side. This protective plating 54 is a part of the wiring pattern 5 and is included in the wiring pattern 5 . The wiring pattern 5 including the solder resist 8 and the protective plating 54 is included in the configuration of the wiring board 2 rather than the configuration of the support 3 . Lands 53 provided on the wiring pattern 5 are external connection terminals 53 . Nickel/gold plating (protective plating 54 ) is formed on the end of the land 53 on the peelable copper foil side. Other detailed configurations are the same as those of the wiring board 2 used in the first embodiment.

(Semiconductor package with support)
As shown in FIG. 13, the semiconductor package with support 18 of the present embodiment includes the wiring substrate with support 1 described above (package substrate with support 1) and the support 3 of the wiring substrate with support 1. As shown in FIG. and an electronic component element 11 (semiconductor element 11) disposed on the surface opposite to the (copper-clad laminate). That is, the above-described embodiment except that the nickel/gold plating as the protective plating 54 is disposed on the portion of the wiring substrate 2 (package substrate 2) that is in close contact with the multilayer metal foil 31 side of the wiring pattern 5. 1 is the same as the semiconductor package 18 with support. Therefore, detailed description is omitted.

(Method for manufacturing wiring board with support)
FIG. 14 shows a method of manufacturing the wiring board 1 with a support according to Embodiment 2, which is an example of the present invention. The manufacturing method of the wiring board 1 with the support of the second embodiment is similar to the manufacturing method of the first embodiment described above. and a step (B) of forming the wiring board 2 having the solder resist 8 and the wiring pattern 5 on at least one of the front and back surfaces. However, the manufacturing method of Embodiment 2 differs from the manufacturing method of Embodiment 1 only in that, in the step (A), a protective plating 54 is formed on the multilayer metal foil 31 side of the wiring pattern 5. ing. A method for manufacturing the wiring board 1 with a support according to Embodiment 2 will be described in detail below.

(Step (A))
As shown in A-1 of FIG. 14, in the same manner as in the manufacturing method of Embodiment 1, a copper foil-clad laminate serving as the support 3 provided with a peelable copper foil (multilayer metal foil 31) as the support 3 was prepared. prepare.

As shown in A-2 of FIG. 14, in the same manner as in the manufacturing method of Embodiment 1, on a peelable copper foil (multilayer metal foil 31) provided on a copper-clad laminate (specifically, an ultra-thin copper foil) 311), a solder resist 8 is formed.

As shown in A-3 of FIG. 14, the wiring pattern 5 is formed on the ultra-thin copper foil 311 provided on the copper-clad laminate in the same manner as in the manufacturing method of the first embodiment. Wiring patterns 5 to be external connection terminals 53 are formed in gaps between solder resists 8 which are adhered to the surface of the ultra-thin copper foil 311 of the support 3 and formed in a predetermined pattern. However, unlike the manufacturing method of the first embodiment, a protective plating 54 is formed on the tip of the wiring pattern 5 on the ultra-thin copper foil 311 side.
Specifically, the peelable copper foil is used as the power supply layer, the previously formed solder resist 8 is used as the plating resist, and nickel/gold plating as the protective plating 54 is first formed as follows. Gold plating is formed on the ultra-thin copper foil 311 using electrogold plating. The thickness of gold plating is 0.01 to 1 μm. Next, nickel plating is formed on the gold plating using nickel electroplating. The thickness of nickel plating is, for example, 0.5 to 10 μm. Before forming the nickel plating, the gold plating may be plated with a noble metal such as palladium plating, and then the nickel plating may be formed.
Next, in the same manner as in the manufacturing method of Embodiment 1, pattern plating is formed on the nickel plating using a copper sulfate plating bath, so that the ultra-thin copper foil 311 is adhered to the ultra-thin copper foil 311 . A wiring pattern 5 having a nickel/gold plating 54 on the tip of the side is formed. Other than this, the wiring pattern 5 is formed in the same manner as in the first embodiment.

(Step (B))
As shown in B-1 to B-4 in FIG. 5 and as shown in B-5 to B-7 in FIG. 6, a wiring substrate (package substrate) 2 was formed in the same manner as in Embodiment 1. .

(Method for manufacturing electronic component package with support)
In the same manner as shown in FIG. 7, a method for manufacturing an electronic component package 18 with a support (semiconductor package 18 with a support) of Embodiment 2, which is an example of the present invention, is shown. In the method of manufacturing the semiconductor package 18 with a support according to the second embodiment, after the step (B), the wiring board with the support is provided on the side opposite to the support, as in the manufacturing method of the first embodiment described above. has a step (C) of arranging a semiconductor element on the surface of Since it is the same as the first embodiment, details are omitted.

(Manufacturing method of electronic component package)
A method of manufacturing an electronic component package 19 (semiconductor package 19) according to Embodiment 2, which is an example of the present invention, is shown in the same manner as shown in FIG. In the method of manufacturing the electronic component (semiconductor) package 19 of Embodiment 2, after the step (C), the multilayer metal foil 31 on the support 3 is separated at the boundary 313 between the metal foils 311 and 312, A step (D) of separating the support 3 and the semiconductor package 19 that is the electronic component package 19 is included. Details of the method for manufacturing the semiconductor package 19 of this embodiment will be described below.

(Step (D))
As shown in D-1 of FIG. 8, in the same manner as the manufacturing method of Embodiment 1, an ultra-thin copper foil in the peelable copper foil (composite metal foil 31) of the copper-clad laminate (support 3) The copper foil-clad laminate (support 3) and the semiconductor package 19 are separated by peeling at the boundary 313 between 311 and the carrier copper foil 312 .

As shown in D-2 of FIG. 8, the ultra-thin copper foil 311 remaining in close contact with the solder resist 8 and the pattern plating that will be the external connection terminals 53 due to the separation in D-1 is entirely etched. removed to expose the solder resist 8 . At this time, the tip (surface) of the pattern plating is provided with nickel/gold plating 54 . Therefore, after the ultra-thin copper foil 311 on the pattern plating is completely removed, the nickel/gold plating 54 functions as an etching resist, and excessive etching of the pattern plating 15 can be suppressed. . That is, the surface of the solder resist 8 and the surface of the pattern plating 15 are flat without a step. Thereby, the semiconductor package 19 having the solder resist 8 and the external connection terminals 53 on the bottom surface can be obtained.

(action/effect)
According to the second embodiment, in addition to having the same effects as those of the first embodiment, the following effects are obtained. That is, after separating the support 3 from the semiconductor (electronic component) package 18 with support, when removing the ultra-thin copper foil 311 moved to the semiconductor package 18 with support by etching, the tip of the wiring pattern 5 The protective plating 54 provided functions as an etching resist to prevent the wiring pattern 5 from being excessively etched. As a result, the semiconductor package 19 having the solder resist 8 and the external connection terminals 53 on the lower surface can be obtained in a stable process with a wide control margin. Further, the step of forming the protective plating 54 on the external connection terminals 53 later can be eliminated.

1. Wiring substrate with support (package substrate with support)
2. Wiring board (package board)
3. Support (copper clad laminate)
31. Multi-layer metal foil (peelable copper foil)
311. Daiichi Metal Foil (ultra-thin copper foil)
312. Second metal foil (carrier copper foil)
313. Boundary (delamination layer)
32. Metal foil (copper foil)
33. Support layer (glass epoxy resin)
5. Wiring pattern 51 . line 52 . Land (internal connection terminal)
53. Land (external connection terminal)
54. Protective plating (nickel/gold plating)
6. Interlayer connection (non-through via)
61. Interlayer connection hole (non-through hole)
62. Conductor (fill plating)
7. Insulating layer (glass epoxy resin)
71. First insulating layer (glass epoxy resin)
72. Second insulating layer (glass epoxy resin)
8. solder resist10. pre-soldering11. Electronic component element (semiconductor element)
111. Flip chip terminal 112 . wire bond terminals 12 . underfill material 13 . bonding wire 14 . mold resin 15 . pattern plating 16 . Conductor layer (copper foil)
17. opening 18 . Electronic component package with support (semiconductor package with support)
19. Electronic component package (semiconductor package)
20. plating resist 21 . Pattern copper plating22. copper bumps 23 . etching resist

Claims (8)

A support comprising: a support layer; and a multi-layered metal foil disposed on at least one of the front and back surfaces of the support layer and having a plurality of layers of metal foil laminated in a detachable state at the boundary between at least any of the metal foils. body and
a wiring board comprising: a solder resist and a wiring pattern arranged on the multilayer metal foil of the support; and an insulating layer arranged on the solder resist and the wiring pattern;
has
A wiring board with a support, wherein the multilayer metal foil is a peelable metal foil, and the peel strength between the peelable metal foils is 2 to 100 N/m. 2. The wiring board with support according to claim 1, wherein said wiring pattern is provided with protective plating disposed on said multilayer metal foil side. The boundary between the peelable metal foils in the multilayer metal foil of the support is at least the boundary between the first metal foil on which the solder resist and the wiring pattern are arranged and the adjacent second metal foil, 3. The wiring board with a support according to claim 1, provided. 4. A support, comprising: the wiring board with support according to claim 1 ; and an electronic component element disposed on the surface of the wiring board with support opposite to the support. Electronic components package with. A step (A) of forming a solder resist and a wiring pattern on a multilayer metal foil provided on a support;
A step (B) of forming a wiring board having the solder resist and the wiring pattern on at least one of front and back surfaces;
has
The method for producing a wiring board with a support, wherein the multilayer metal foil is a peelable metal foil, and the peel strength between the peelable metal foils is 2 to 100 N/m. 6. The method for manufacturing a wiring board with a support according to claim 5, wherein in said step (A), a protective plating is formed on the side of said wiring pattern on the side of said multilayer metal foil. A method for manufacturing a wiring board with a support according to claim 5 or claim 6;
A method of manufacturing an electronic component package, comprising, after the step (B), the step (C) of arranging an electronic component element on the surface of the wiring board with a support opposite to the support. 8. The method according to claim 7 , further comprising, after the step (C), a step (D) of separating the support and the electronic component package by separating the metal foils of the multilayer metal foil on the support at the boundary between the metal foils. method of manufacturing an electronic component package.