JP5625250B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a multilayer wiring board applied to a package substrate or the like of a semiconductor element and a semiconductor device using the multilayer wiring board, and is particularly effective for measures such as warpage, mountability and reliability of the multilayer wiring board. The invention relates to the arrangement and shape of openings formed in a power supply or ground layer in a wiring board.

  In recent years, with the advent of the advanced information era, information communication technology and information processing technology have been rapidly developed, and the high density of various electronic modules for implementing those technologies and various semiconductor modules mounted as components on the electronic devices. Increasingly, speeding up. Therefore, an interposer substrate for mounting a semiconductor and a multilayer substrate for a semiconductor package on which an electronic component including a semiconductor is mounted are required to have a high density and a high-speed response. On the other hand, since electronic devices are often required to be small, thin, and light, it is necessary to balance high density, high speed, miniaturization, and thinning in a balanced manner.

  Against this backdrop, semiconductor package multi-layer substrates, in which the insulating layer is made of an organic material, have come to dominate, particularly for interposer substrates for semiconductor packages and substrates for modules. This is because, compared to inorganic materials, it has been evaluated that it is flexible and has an impact resistance that can withstand an impact such as dropping, and it is lightweight and inexpensive.

However, there is a difference in the amount of moisture to be absorbed depending on the type of the insulating layer of the organic material, and moisture absorbed after being formed as a multilayer substrate for a semiconductor package is formed on the insulating layer after a heating step or the like. There are cases where problems such as bulging or peeling of the contact portion between the insulating layer and the wiring layer occur due to the water vaporized by the heat treatment that goes under the wiring layer and becomes a gas by repeated heat treatment.
It is considered that this phenomenon occurs as a result because the conductor of the wiring layer prevents gas from being diffused into the atmosphere from the insulating layer.

As a typical example, a polyimide material, which is one of organic materials for an insulating layer, has a low dielectric constant and a low dielectric constant compared to a general epoxy material as a material for a multilayer substrate for a semiconductor package. It has very good electrical characteristics such as tangent value, which is advantageous for high-speed response. Moreover, since the temperature of a glass transition point is higher than the value of the said reflow temperature, it is hard to deform | transform and heat resistance is high. In addition, it has excellent characteristics such as being able to be thinned because it has excellent mechanical properties such as strong tensile strength resistance.
However, polyimide materials and the like have a problem of high hygroscopicity.

As a measure for solving the above problem, it has been proposed to form a through-opening for degassing in a part of the conductor layer, for example, other than a signal area of the wiring and a certain area of the upper and lower layers thereof There is one in which an opening is provided in the part (Patent Document 1).
By such measures, there has been proposed a multilayer substrate for a semiconductor package, which can effectively dissipate the generated gas and hardly cause blistering or peeling even in the heating process.

On the other hand, as described above, warping of the multilayer substrate for semiconductor packages has become an important problem from the viewpoint of mountability and reliability as the multilayer substrate for semiconductor packages becomes thinner and lighter.
That is, due to the warpage of the semiconductor package substrate, the connection pads corresponding to each terminal are sufficiently connected in FC (flip chip) mounting, BGA mounting, LGA mounting, etc., which are mounting of a semiconductor to a bare chip or a motherboard. This may reduce the connection reliability.

Therefore, as a countermeasure for solving the problem of the connection failure, for example, a method of bending the four sides of the wiring board to cope with external stress has been proposed (Patent Document 2).
However, this method has a problem that foreign matter is generated from the bent portion, and delamination is likely to occur in the case of a multilayer wiring board.

In addition, a method has been proposed in which, when an insulating layer of a wiring board is formed, a heat process applied in a later process is performed in advance to suppress an increase in warpage in the later process (Patent Document 3). ).
The purpose of this method is to suppress the warpage associated with the hardening shrinkage of the insulating layer, but the timing of hardening shrinkage only changes depending on whether it is an early stage or a late stage, and changes to the internal stress that is finally accumulated. However, it is not considered to be a measure that fundamentally resolves warpage.

JP 2005-353835 A Japanese Patent Laid-Open No. 09-097856 JP 2005-183441 A

  Conventionally, as described above, a countermeasure for providing an opening in the power supply or ground portion of the conductor layer for degassing the multilayer wiring board and a countermeasure for reducing warpage have been proposed separately. However, an effective method for easily obtaining a multilayer wiring board having a well-balanced productivity, quality or performance for solving these problems at the same time and actually obtaining a product has not been proposed.

  The present invention has been made in view of the above problems of the prior art, and can suppress warpage while preventing peeling and blistering of the multilayer wiring board due to degassing, and can be used for semiconductor packages with high mountability and reliability. An object of the present invention is to provide a multilayer wiring board and a semiconductor device using the same.

As means for solving the above-mentioned problem, the invention according to claim 1 is characterized in that a conductor layer and an insulating layer are laminated, and the conductor layer has a wiring layer and a power supply or ground layer, In the multilayer wiring board in which openings are formed in the power supply or ground layer in the thickness direction,
First multilayer wiring board, a percentage of the wiring layer of the opening, and wherein the first multilayer wiring board that the center side peripheral side has high low of the first plane of the conductor layer of the multilayer wiring substrate,
Third multilayer wiring board, the ratio of the opening occupying the wiring layer, the third multilayer wiring low in a layer located on the center side in the thickness direction of the substrate, formed higher in a layer located on the outside is a semiconductor device which is characterized in that the features of the third multilayer wiring board that are are combined.

The aperture ratio of the conductor layer other than the signal portion is low on the central side in the plane and high on the peripheral side. Here, the low aperture ratio means that the proportion of conductor remaining (hereinafter simply referred to as “residual conductor ratio”) is high (many conductors remain). On the central side, the rigidity on the central side is increased by leaving many conductors mainly made of metal having a high elastic modulus. On the other hand, the rigidity is low on the peripheral side.
As a specific example, as shown in FIG. 1 or Table 1, it is effective to divide the conductor surface into several regions and to define the aperture ratio for each region. Due to the high rigidity on the center side, warpage near the center of the substrate can be suppressed.

As a result, the amount of warpage of the entire substrate is reduced. This is because, as shown in FIG. 2, if the multilayer wiring board warps with the same curvature, the warping amount is larger when only the center side warps.
This aperture ratio can be adjusted by appropriately changing the size, number, pitch, arrangement, etc. of the apertures. In the present invention, the opening ratio is preferably 5 to 60%, and more preferably 10 to 30%. In the present invention, the aperture ratio can be set to be higher or lower than other regions for each position, but can be appropriately optimized depending on the material of the conductor layer and the insulating layer and the wiring pattern. desirable.

In addition, the semiconductor device is characterized by the shape formed by the outline of the formation area, which is the area where the opening is formed, and the outline of the non-formation area, where the opening is not formed, as a feature of the second multilayer wiring board. Any one or both of the shapes may be combined radially from the center side in the plane of the conductor layer of the second multilayer wiring board to the outside.

  That is, as shown in FIGS. 3 (a) and 3 (b), warping is suppressed by consciously using a portion where an opening is provided and a portion where no opening is provided. As shown in FIG. 3A, by leaving the conductor portion radially from the center in the conductor layer, the rigidity of the portion is increased and the warpage is reduced. The image is like sticking a rigid rod to the non-opening region to suppress warpage. On the other hand, as shown in FIG. 3B, the effect of the method for defining the opening formation region is the same as that of FIG. However, there are cases where it is easier to understand that the formation area is defined than the non-formation area is defined as the ease of defining the opening. Since these are essentially the same thing, they can be used arbitrarily for the convenience of the designer.

  As shown in FIG. 4 and Table 2, in the present invention, by increasing the aperture ratio in the central layer and increasing it in the outer layer, the rigidity of the central layer is increased and the rigidity is decreased in the outer layer. ing. FIG. 5 shows an example in which the aperture ratio is changed by changing the diameter of the aperture. FIG. 10 is a cross-sectional image view of the wiring board in the case described above. The opening is formed in the power supply layer or the ground portion, not the signal portion.

  In the case of a multilayer substrate, the number of layers generally increases and the number of laminations increases and the internal stress increases.However, the outer layer has a lower rigidity than the center layer, so that the shape of the center layer is maintained even when laminated. The amount of warpage does not increase greatly when dragged. The aperture ratio is preferably 5 to 60%, more preferably 10 to 30%, and the aperture ratio can be set higher or lower than other layers for each layer. It is desirable to optimize variously according to the material of the insulating layer and the wiring pattern.

In addition, as a feature of the fourth multilayer wiring board, the semiconductor device has a shape in which each opening has a longitudinal direction and a short direction, and the longitudinal direction is the surface of the conductor layer of the fourth multilayer wiring board. You may combine that it is the direction which goes to an outer side from the inner center side radially.

In addition, as a feature of the fifth multilayer wiring board, the semiconductor device has a shape in which each opening has a longitudinal direction and a short direction, and the longitudinal direction corresponds to the center side in the plane of the conductor layer and the multilayer wiring board. In an area close to the side between the sides, the direction perpendicular to the direction of the side may be combined.

According to the fourth multilayer wiring board and the fifth multilayer wiring board , as shown in FIG. 6A, the individual shapes of the openings 103 are directed in the radial direction from the center. The opening 103 is schematically drawn with a short line so that the directionality can be easily understood.
The invention relating to the fourth multilayer wiring board, the fifth multilayer wiring board , and the sixth multilayer wiring board to be described later has a technical idea in common with the second multilayer wiring board . In the case of the second multilayer wiring board , the arrangement of the openings is macroscopically radial, whereas in this case, the individual openings are directed in the radial direction in a microscopic manner. The effect is the same, and the remaining conductor portion runs radially, so that a region with high rigidity is responsible for suppressing warpage.

In addition, as a feature of the sixth multilayer wiring board, the semiconductor device has an individual shape of the opening having a longitudinal direction and a transverse direction, and the longitudinal direction is radially outward from the center side in the plane of the conductor layer. You may combine that it is a direction perpendicular | vertical to the direction which goes to.

The sixth multilayer wiring board provides constituent requirements in contrast to the fourth multilayer wiring board and the fifth multilayer wiring board . As shown in FIG. 6B, the individual shapes of the openings are directed in the direction perpendicular to the radial direction from the center. In this case, since a highly rigid portion is formed in the concentric direction, the undulation can be suppressed when the undulation at the end of the substrate is large, which is effective. It is desirable to apply various shapes related to the fourth multilayer wiring board to the sixth multilayer wiring board depending on the warpage state of each board.

According to the invention from the fourth multilayer wiring board to the sixth multilayer wiring board , as shown in FIG. 6A, the individual shapes of the openings are directed in the radial direction from the center. The idea is in common with the second multilayer wiring board . In the case of the second multilayer wiring board , the arrangement of the openings is macroscopically radial, whereas in this case, the individual openings are directed in the radial direction in a microscopic manner. The effect is the same, and the remaining conductor portion runs radially, so that a region with high rigidity is responsible for suppressing warpage.

In the inventions of the fourth multilayer wiring board to the sixth multilayer wiring board , examples of individual shapes having the directionality of the opening include polygons such as oval, ellipse, parallelogram, rectangle, or rhombus. Or a composite shape obtained by combining them or the like.
That is, the shape of the opening can be variously modified as illustrated in FIG. 7 in consideration of the convenience of design, processing, and arrangement. The arrows in FIG. 7 indicate the directionality, and the rigidity in the micro region is defined by the formation region of the opening and the remaining portion of the opening (non-formation region).

Pattern for holding a part of the wiring layer except for the portion relating to signal transmission with a high high-frequency region than even called 1MHz the signal layer In general, power supply, ground parts, the mechanical strength in the multilayer wiring board Multilayers that do not degrade high-frequency electrical characteristics by selectively arranging openings in so-called dummy patterns or dummy patterns that are not electrically energized used for patterning correction such as etching. A printed wiring board can be provided.
Further, a signal transmission unit for high-frequency transmission often has a high-density wiring rule, and the wiring is thin. Therefore, if an opening is disposed in this part, the mechanical strength is lowered. For this reason, a multilayer substrate with high reliability can be provided by not disposing openings selectively in the above-mentioned portions.
In the previous section, the remaining conductor ratio (1-aperture ratio) has been described without considering the signal area where high-speed signals flow, but in order to effectively suppress warping, the signal layer It is desirable to calculate the remaining conductor ratio including.

By combining the configurations of the first multilayer wiring board to the sixth multilayer wiring board, the warpage can be drastically reduced by the synergistic action of the individual warpage suppressing effects. FIG. 8 and Table 3 relate to an example in which the first multilayer wiring board and the third multilayer wiring board are combined, and the aperture ratio decreases toward the center side (in the plane and in the thickness direction) of the substrate, and the outer side. Then it is getting bigger.

In the present invention, it is preferable that at least one insulating layer of the multilayer wiring board includes a layer made of polyimide. Polyimide-based materials have very good electrical characteristics such as low dielectric constant and low dielectric loss tangent compared to general epoxy-based materials as insulating layer materials for multilayer substrates for semiconductor packages. It is advantageous for handling and has excellent mechanical properties such as high heat resistance due to high glass transition temperature and good tensile strength resistance.
With these characteristics, the insulating function can be maintained and the thickness can be reduced. This is effective for reducing the thickness and weight of the substrate.

As a result of using the multilayer wiring board according to claim 1 of the present invention, a semiconductor device on which a semiconductor element is mounted is excellent in mountability and reliability.

  According to the present invention, it is possible to effectively dissipate the gas in the substrate without impairing the electrical characteristics, it is difficult to cause blistering or peeling even in the heating process, etc. A highly reliable and reliable multilayer substrate for a semiconductor package can be proposed.

The top view for description which drawn the conductor part of the multilayer wiring board concerning the present invention typically. Explanatory drawing which drew the mode of the curvature when a multilayer wiring board bent with the same curvature typically. Explanatory drawing which drawn typically the area | region where the opening of the multilayer wiring board based on this invention is distribute | arranged. (A) When defining a non-formation region (b) When defining a formation region Explanatory drawing which drew typically the aperture ratio for every layer of the multilayer wiring board which concerns on this invention. Explanatory drawing which drawn typically the opening at the time of changing an aperture ratio. (For supplementary explanation of FIG. 4) Explanatory drawing typically drawn about the shape and directionality of the opening of the multilayer wiring board concerning the present invention. (A) when the longitudinal direction of the opening shape in the direction of case (b) opening shape toward the outside in the plane longitudinal direction in a direction parallel to the side in a plane Explanatory drawing typically drawn about the shape and directionality of the opening of the multilayer wiring board concerning the present invention. FIG. 3 is an explanatory diagram schematically illustrating an example in which constituent requirements of a multilayer wiring board according to the present invention are combined. BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which drew typically the cross section of an example of the multilayer wiring board which concerns on this invention. BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which drew typically the cross section of an example of the wiring routing of the multilayer wiring board based on this invention.

  FIG. 9 shows a typical configuration of the multilayer wiring board according to the present invention, in which a cross section in the case of six layers is schematically drawn.

  The multilayer wiring board according to the present invention includes wiring layers 11, 21, 31, 41, 51, 61 made of a conductor, insulating layers 12, 22, 32, 42, 52 made of an organic material, and an outermost layer made of an organic material. The solder resist 105 is formed. Then, interlayer connection is performed by the vias 14, 24, 34, 44, 54.

In addition, as an organic material of the laminated insulating layer used in the present invention, a polyimide material, an epoxy material, a polyolefin material, an organic material having a liquid crystal polymer structure, a composite material such as a glass epoxy material, or the like is used. Can do.
As a material for the wiring layer according to the present invention, a metal such as copper or aluminum, a carbon nanotube, or a conductive material such as a conductive polymer can be used.
Moreover, as a solder resist, the well-known thing sold by each company for semiconductor packages can be used.

In FIG. 9, wiring layers 31 and 41 are disposed above and below the insulating layer 32 and patterned. Further, the insulating layer 22 is disposed on the wiring layer 31 and the insulating layer 42 is disposed below the wiring layer 41. At this time, by applying pressure while heating, the organic material of the insulating layers 22 and 42 is filled between the patterns of the wiring layers 31 and 41, and the gap between the patterns is filled.
Next, the wiring layer 21 and the wiring layer 51 are disposed and patterned. Insulating layers 12 and 52 are formed by the same method, and wiring layers 11 and 61 are also formed.

In order to form the pattern of the wiring layer, a conductive film such as a metal can be formed by a plating method or the like, and patterning can be performed by a photolithography method or the like.
Specifically, a metal film formed by first thick plating is patterned by a photolithography method to form a wiring pattern, or photolithography is performed on a metal film formed by thin electroless plating. By forming a resist pattern by the method, forming a thick metal pattern by electroplating where there is no resist, removing the resist, and then etching the whole to remove the thin electroless plating layer, wiring pattern It may be formed by applying a semi-additive method or the like that forms the film. Further, a carbon nanotube, a conductive organic polymer material, or the like may be formed into a film by a method such as coating or a method using an apparatus such as sputtering, and a wiring pattern may be formed by a photolithography method or the like.

  When forming the pattern of the wiring layer, it is desirable to provide the opening according to the present invention at the same time. The opening according to the present invention is a vent hole for gas generated during the manufacturing process, and at the same time has an effect of suppressing warpage (in cooperation with the non-opening). In consideration of the material of the conductor layer and the insulating layer, the wiring pattern, etc., it is desirable to determine the aperture ratio and the residual conductor ratio so that the effect of the present invention is enhanced.

  As a method of laminating the wiring layers 31 and 41 on the insulating layer 32, a laminating method, an adhesion method, a heat sealing method, a casting method, a sputtering method, or the like can be used.

  Thereafter, a via 34 is formed to establish conduction between the wiring layers 31 and 41. Etching is partially performed in a circular shape using a photolithography method to remove the conductor portion, and an opening is formed in the insulating layer 32 by laser processing using a UV-YAG laser in the removed portion. Residue denatured by the heat of the laser inside the hole is removed by desmear treatment. After the base plating is performed on the opening by electroless copper plating, a via 34 for connecting the wiring layer 31 and the wiring layer 41 is formed by performing electrolytic copper plating using a copper plating solution for filled vias to fill the through hole with copper. Form. Further, a conformal via that fills the remaining portion without completely filling the via may be formed.

  Insulating layers 22 and 42 and wiring layers 21 and 51 were formed in the same manner as the insulating layer 32 and wiring layers 31 and 41. Further, vias 24 and 44 were formed in the same manner as the via 34. Further, the wiring layers 21 and 51 were patterned in the same manner as the patterning of the wiring layers 31 and 41. In this way, a four-layer multilayer wiring board was prepared.

  Similarly, an insulating layer and a wiring layer were formed to form insulating layers 12, 52, wiring layers 11, 61 vias 14, 54, and a six-layer multilayer wiring board was produced. In the present embodiment, the stacking is performed sequentially, but a patterned wiring layer and an insulating layer may be prepared, and the stacking and interlayer connection may be performed collectively.

  A solder resist 105 was formed by printing on the outermost layer of the thus prepared six-layer wiring board. As the forming method, spray coating, dip coating, dry film type solder resist laminate, or the like can be used.

Thereafter, a surface treatment for mounting a bare semiconductor chip on the wiring layer 11 side was performed to obtain a semiconductor chip mounting side.
That is, first, in order to electrically connect the semiconductor chip and the multilayer printed wiring board, the wiring layers 11 and 61 were provided with openings of the solder resist 105 in the pad portions serving as connecting portions arranged. By putting the whole in a gold plating bath, the pad opening was selectively gold-plated. For the surface treatment of the openings, silver or palladium alloy plating may be used. In addition, in order to prevent these metals from diffusing into the underlying conductor or to increase the hardness, plating such as nickel or nickel alloy is performed before the plating such as gold, silver or palladium alloy. Also good.
Next, Sn-Ag-Cu solder was formed on the pads of the wiring layer 11 and then solder reflow was performed to form solder bumps for connection to the semiconductor chip.

  In the present invention, a polyimide material is used for all insulating layers. First, a polyimide base material with a double-sided copper foil was prepared, and via holes were formed by UV laser. Thereafter, the via hole was washed by permanganate, followed by non-electric plating and electrolytic plating. After plating, the thickness of copper was reduced to a desired value by chemical polishing treatment, and a pattern was formed on both sides simultaneously by photolithography and etching with ferric chloride. The opening of the present invention was also formed at the same time. The formation state of the opening will be described later.

Subsequently, a polyimide copper foil with an adhesive (copper / polyimide / adhesive) was placed on the top and bottom of the two-layer base material previously produced, and lamination was performed by a collective press. By the same method, via formation and patterning were performed to prepare a four-layer base material.
Thereafter, lamination, via formation, and patterning were further performed to prepare a 6-layer base material. Also, a solder resist pattern was formed on the outermost surface, and Ni / Au plating was performed as the surface treatment. Solder bumps were formed on the semiconductor chip side. The size of the substrate was 40 mm square.

  The state of the opening of each layer in Example 1 is shown below. The region in the layer was divided into two, the opening ratio of the central part was 30%, and the opening ratio of the outer peripheral part was 40%. Further, a non-opening region was formed in an X shape for FIG. 3A, and the individual shapes were arranged as radial diamonds for FIG. 6A. A region with an aperture ratio of 30% at the center was 20 mm square, and the width of the nonlinear region was 2 mm.

A six-layer multilayer wiring board of Example 2 was formed in the same manner as in Example 1 except that the directionality related to the arrangement of the openings and the shape of the openings in Example 1 was changed.
As shown in FIG. 6 (b), the individual openings in each of the multilayer wiring board regions are in the shape of an ellipse oriented in the vertical direction in the direction from the center of the surface of the multilayer wiring board to each side. The aperture ratio for each layer was defined. The cross-sectional state of the multilayer wiring board is schematically drawn as shown in FIG. 9, and the aperture ratio of each layer is 40% for the conductor layers 11 and 61, 30% for the conductor layers 21 and 51, and the conductor. The layers 31 and 41 were 20%.

Comparative example

  As a comparative example, a six-layer wiring board was formed in the same manner as in Example 1, except that the directionality related to the arrangement of the openings and the shape of the openings was changed with respect to Example 1. The aperture ratio was uniformly 30% in the multilayer wiring board, and the openings were evenly arranged in the plane of the multilayer wiring board.

  The multilayer wiring board manufactured as described above was evaluated for warpage and mounting properties before and after mounting. First, the amount of warpage before the mounting process was measured. The amount of warpage is calculated by calculating the virtual plane of the entire substrate, and calculating the difference between the point farthest from the stage surface within the substrate range and the closest surface with the laser displacement meter as the reference. The measurement was performed after removing the components. Ten sheets were measured, and the average value of warpage was 95 μm in Example 1, 100 μm in Example 2, and 160 μm in Comparative Example.

Thereafter, primary mounting was performed on the dummy chip, and the warpage was measured by the same method as before mounting. The warpage after mounting was 180 μm in Example 1, 195 μm in Example 2, and 280 μm in Comparative Example. In addition, regarding the solder joint failure, the occurrence was zero in all the 10 substrates in Example 1 and Example 2 (although it did not occur), but in the comparative example, for all 10 substrates. One has occurred.
As a result, according to the present invention, it was possible to effectively reduce the warpage and improve the mountability.

1A, 1B, 1C, 9I, 9II ... one of the divisions of the formation area of the openings 4A, 4B, 4C, 9A, 9B ... one of the divisions of the layers forming the openings 100 ... the substrate 11, 21, 31, 41, 51, 61 ... wiring layer 102, 12, 22, 32, 42, 52, 62 ... insulating layer 103, 13, 23, 33, 43, 53, 63 ... opening 14 24, 34, 44, 54 ... via 105 ... solder resist 106 ... signal layer
107: Power source or ground layer r: Radius of curvature

Claims (1)

A conductor layer and an insulating layer are laminated, and the conductor layer has a wiring layer and a power supply or ground layer, and an opening is formed in the power supply or ground layer so as to penetrate these in the thickness direction . In multilayer wiring boards ,
First multilayer wiring board, a percentage of the wiring layer of the opening, and wherein the first multilayer wiring board that the center side peripheral side has high low of the first plane of the conductor layer of the multilayer wiring substrate,
Third multilayer wiring board, the ratio of the opening occupying the wiring layer, the third multilayer wiring low in a layer located on the center side in the thickness direction of the substrate, formed higher in a layer located on the outside the semiconductor device characterized by the features of the third multilayer wiring board are combined as are.

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