JP7326879B2 - Semiconductor devices, electronic devices and moving bodies - Google Patents

Description

The present invention relates to semiconductor devices, electronic devices, and mobile bodies.

Patent Literature 1 describes a device that restores the original time scale by time scale modification (TSM) after changing the pitch of audio data by resampling.

JP-A-9-325794

However, in the device described in Patent Document 1, resampling and time scale conversion are performed by software processing, so a DSP with high processing capability is required, resulting in a large circuit scale.

One aspect of the semiconductor device according to the present invention is
an audio data storage unit that stores first audio data including a plurality of samples sampled in a first period;
a clock generator that generates a first clock signal and a second clock signal;
A time scale for converting the first audio data into second audio data in which part of the plurality of samples included in the first audio data are deleted or duplicated in synchronization with the first clock signal. a conversion unit;
The second audio data is sampled at the first period in synchronization with the second clock signal, and the third audio data includes a plurality of samples of a number different from that of the second audio data. A resampler, which is a dedicated circuit that converts to
and a register storing control information for controlling the operation of the time scale converter and the resampler.

In one aspect of the semiconductor device,
The third audio data may be data having the same number of samples as the first audio data, in which the pitch of the first audio data is changed.

In one aspect of the semiconductor device,
The audio data storage unit, the clock generation unit, the time scale conversion unit, the resampler and the register may be included in a one-chip integrated circuit device.

In one aspect of the semiconductor device,
the control information includes information for setting the operation mode of the semiconductor device to one of a plurality of operation modes including a first operation mode, a second operation mode, and a third operation mode;
the first operation mode is an operation mode in which the pitch is changed without changing the reproduction time of the first audio data;
the second operation mode is an operation mode in which the reproduction time is changed without changing the pitch of the first audio data;
The third operation mode may be an operation mode for changing the reproduction time and pitch of the first audio data.

One aspect of the semiconductor device is
A D/A converter that converts the third audio data into an analog signal may be included.

One aspect of the electronic device according to the present invention is
an aspect of the semiconductor device;
and a sound output unit that outputs sound based on the output signal from the semiconductor device.

One aspect of the moving object according to the present invention is
an aspect of the semiconductor device;
and a sound output unit that outputs sound based on the output signal from the semiconductor device.

1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment; FIG. FIG. 10 is a diagram showing an example of conversion of voice data when pitch is lowered; FIG. 3 is a diagram for explaining details of resampling in the example of FIG. 2; FIG. 10 is a diagram showing an example of conversion of voice data when raising the pitch; FIG. 5 is a diagram for explaining the details of resampling in the example of FIG. 4; FIG. 10 is a diagram showing a specific example of a semiconductor device; FIG. 4 is a diagram showing a configuration example of a semiconductor device according to a second embodiment; FIG. 10 is a diagram showing an example of conversion of audio data when pitch is lowered and playback time is shortened; FIG. 10 is a diagram showing an example of conversion of audio data in the case of increasing the pitch and extending the playback time; FIG. 10 is a diagram showing a configuration of a semiconductor device of a modified example; The figure which shows the conversion example of the audio|voice data in the case of lowering a pitch in a modification. The figure which shows the conversion example of the audio|voice data in the case of raising a pitch in a modification. FIG. 2 is a functional block diagram of the electronic device according to the embodiment; 1A and 1B are diagrams illustrating an example of an appearance of an electronic device according to an embodiment; FIG. The figure which shows an example of the moving body of this embodiment.

Preferred embodiments of the present invention will be described in detail below with reference to the drawings. It should be noted that the embodiments described below do not unduly limit the content of the present invention described in the claims. Moreover, not all the configurations described below are essential constituent elements of the present invention.

1. Semiconductor device 1-1. First Embodiment FIG. 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment. As shown in FIG. 1, the semiconductor device 1 of the first embodiment includes an audio data storage section 10, a clock generation section 20, a time scale conversion section 30, a resampler 40, and a register 50.

The audio data storage unit 10 stores first audio data D1 including a plurality of samples sampled at the first period Ts1. The audio data storage unit 10 may be a non-volatile memory in which the first audio data D1 is stored in advance, or for example, the first audio data received by the semiconductor device 1 from an external device via an interface circuit (not shown). A volatile memory that temporarily stores the audio data D1 may be used. The first audio data D1 may be, for example, pulse code modulated (PCM) audio data. Also, in order to reduce the size of the audio data storage unit 10, the first audio data D1 is compressed audio data such as adaptive differential pulse code modulated (ADPCM) audio data. There may be. The first period Ts1 is the reciprocal of the sampling frequency of the first audio data D1, and the sampling frequency may be at least twice the upper limit frequency of a predetermined audio band, for example, 15.625 kHz. There may be.

The clock generator 20 generates a first clock signal CK1 and a second clock signal CK2. The first clock signal CK1 is a clock signal for operating the time scale conversion section (TSM section) 30, and the second clock signal CK2 is a clock signal for operating the time scale conversion section 30. FIG. The clock generation unit 20 has an oscillation circuit (not shown) such as a crystal oscillation circuit, a ring oscillator, a CR oscillation circuit, etc., and generates a first clock signal CK1 and a second clock signal CK1 based on the output signal of the oscillation circuit. A signal CK2 may be generated.

In synchronization with the first clock signal CK1, the time scale conversion unit 30 transforms the first audio data D1 into a second audio data obtained by deleting or duplicating some of the plurality of samples included in the first audio data D1. Convert to data D2. For example, the deleted or duplicated sample may be part of a plurality of samples that make up a periodically repeating waveform. The second audio data D2 is audio data having the same pitch as the first audio data D1, but different in reproduction speed or reproduction time from the first audio data D1. Various known techniques can be applied to the process of converting the first audio data D1 into the second audio data D2, that is, the so-called time scale conversion process. For example, the time scale conversion unit 30 may perform time scale conversion processing by software processing. When the first audio data D1 is compressed audio data, the time scale conversion unit 30 performs time scale conversion processing on the first audio data D1 expanded by an audio data expansion unit (not shown). may be performed.

In synchronization with the second clock signal CK2, the resampler 40 performs hardware processing to sample the second audio data D2 at the first period Ts1, and samples the second audio data D2 in a number different from that of the second audio data D2. is converted into third audio data D3 containing samples of . Specifically, the resampler 40 assumes that a plurality of samples included in the second audio data D2 are sampled at a second period Ts2 different from the first period Ts1. A plurality of samples sampled at the first cycle Ts1 are obtained by interpolation processing and/or thinning processing based on , and are used as third audio data D3. Various known techniques can be applied to interpolation processing and/or thinning processing.

In this embodiment, the third audio data D3 is data with the same number of samples as the first audio data D1, in which the pitch of the first audio data D1 is changed. In other words, the third audio data D3 is audio data with a different pitch and the same reproduction time or reproduction speed as the first audio data D1.

The register 50 stores control information for controlling the operations of the time scale converter 30 and the resampler 40 . For example, the control information may include a start bit ST for causing the time scale converter 30 and resampler 40 to start processing. The time scale converter 30 and the resampler 40 start processing when the start bit ST changes from inactive to active, and stop when the processing ends.

The control information also includes ratio information SR for setting the ratio between the number of samples of the second audio data D2 and the number of samples of the first audio data D1, and the ratio information SR is sent to the time scale conversion unit 30 and the resampler 40. may be supplied. For example, when the ratio information SR indicates that the number of samples of the second audio data D2 is 75% of the number of samples of the first audio data D1, the time scale conversion unit 30 converts the first audio data D1 into , 25% of the N samples included in the first audio data D1 are deleted and converted into second audio data D2 including N×0.75 samples. Assuming that the resampler 40 samples N×0.75 samples included in the second audio data D2 at a second period Ts2 that is approximately 133% of the first period Ts1, , N×0.75 samples, N samples sampled at the first cycle Ts1 are obtained as third audio data D3.

The semiconductor device 1 may also include a D/A (Digital to Analog) converter 60 . When the semiconductor device 1 includes the D/A converter 60, the clock generator 20 generates the third clock signal CK3 for operating the D/A converter 60. FIG.

The D/A converter 60 converts the third audio data D3 into an analog audio signal VO. Specifically, the D/A converter 60 samples a plurality of samples included in the third audio data D3 at a first period Ts1 in synchronization with the third clock signal CK3 and converts them into analog values. to generate the audio signal VO. The start bit ST is also supplied to the D/A converter 60, and the D/A converter 60 starts processing when the start bit ST changes from inactive to active, and stops when processing ends.

Note that the semiconductor device 1 may include a low-pass filter 70 when it is necessary to reduce aliasing noise generated by resampling in the resampler 40 . When the resampling in the resampler 40 is downsampling, the low-pass filter 70 is provided in the preceding stage of the resampler 40, specifically in the signal path from the output of the time scale conversion unit 30 to the input of the resampler 40, It is also provided in a signal path after the resampler 40 , specifically, from the output of the resampler 40 to the input of the D/A converter 60 as necessary. Also, when the resampling in the resampler 40 is upsampling, the low-pass filter 70 is placed in the signal path after the resampler 40, specifically from the output of the resampler 40 to the input of the D/A converter 60. be provided. When the semiconductor device 1 includes the low-pass filter 70 , the clock generator 20 generates a fourth clock signal CK4 for operating the low-pass filter 70 and the start bit ST is also supplied to the low-pass filter 70 . The low-pass filter 70 starts processing in synchronization with the fourth clock signal CK4 when the start bit ST changes from inactive to active, and stops when the processing ends.

Note that the clock generator 20 generates the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 when the start bit ST changes from inactive to active. , the generation of the clock signal may be stopped after a predetermined period of time. In this case, the start bit ST may not be supplied to the time scale converter 30, resampler 40, D/A converter 60 and low-pass filter 70. FIG.

Further, a plurality of clock signals among the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 generated by the clock generation unit 20 may be common. .

Hereinafter, the processing performed by the time scale conversion unit 30 is referred to as "time scale conversion". The processing performed by the resampler 40 is called "resampling". Further, the processing performed by the D/A converter 60 is called "D/A conversion".

FIG. 2 is a diagram showing an example of the second audio data D2, the third audio data D3, and the audio signal VO when lowering the pitch of the first audio data D1. In the example of FIG. 2, the first audio data D1 is audio data of a constant frequency in which the same sine wave is repeated four times in a constant period of time, and its reproduction time is T1. Also, the ratio information SR is set to 75%.

First, one sine wave of the first audio data D1 containing N samples is removed by time scale conversion to generate the second audio data D2 of constant frequency in which the same sine wave is repeated three times. The number of samples of the second audio data D2 is N×0.75, and the reproduction time T2 of the second audio data D2 is shortened to 75% of the reproduction time T1 of the first audio data D1. On the other hand, since the frequency of the sine wave included in the second audio data D2 is the same as the frequency of the sine wave included in the first audio data D1, the pitch does not change before and after the time scale conversion. That is, the second audio data D2 is audio data having the same pitch as the first audio data D1 and having a playback time shortened to 75%.

Next, resampling generates the third audio data D3 containing about 1.33 times as many samples as the reciprocal of the ratio information SR of the number of samples of the second audio data D2. FIG. 3 is a diagram for explaining details of resampling in the example of FIG. FIG. 3 shows part of the third audio data D3 generated corresponding to part of the second audio data D2. In the example of FIG. 3, resampler 40 assumes that samples A1 to A5, etc. included in second audio data D2 are sampled at second period Ts2, which is approximately 133% of first period Ts1. Then, by interpolation processing and/or thinning processing, the samples B1 to B6 sampled at the first period Ts1 are obtained to generate the third audio data D3.

As shown in FIG. 2, the reproduction time of the third audio data D3 is approximately 133% of the reproduction time T2 of the second audio data D2, which is the same as the reproduction time T1 of the first audio data D1. On the other hand, the frequency of the sine wave included in the third audio data D3 is 75 times the frequency of the sine wave included in the second audio data D2, that is, the frequency of the sine wave included in the first audio data D1. %. That is, the third audio data D3 is audio data whose reproduction time is the same as that of the first audio data D1 and whose pitch is reduced to 75%.

Finally, by D/A conversion, an audio signal VO having the same reproduction time as the reproduction time of the third audio data D3, that is, the reproduction time T1 of the first audio data D1 is generated.

FIG. 4 is a diagram showing an example of the second audio data D2, the third audio data D3, and the audio signal VO when the pitch of the first audio data D1 is raised. In the example of FIG. 4, the first audio data D1 is audio data of a constant frequency in which the same sine wave is repeated four times in a constant period of time, and its reproduction time is T1. Also, the ratio information SR is set to 125%.

First, one sine wave of the first audio data D1 containing N samples is replicated by time scale conversion to generate the second audio data D2 of constant frequency in which the same sine wave is repeated five times. The number of samples of the second audio data D2 is N×1.25, and the reproduction time T2 of the second audio data D2 is extended to 125% of the reproduction time T1 of the first audio data D1. On the other hand, since the sine wave contained in the second audio data D2 has the same frequency as the sine wave contained in the first audio data D1, the pitch does not change before and after the time scale conversion. In other words, the second audio data D2 is audio data having the same pitch as the first audio data D1 and having the reproduction time extended by 125%.

Next, resampling generates the third audio data D3 containing 0.8 times as many samples as the reciprocal of the ratio information SR of the number of samples of the second audio data D2. FIG. 5 is a diagram for explaining details of resampling in the example of FIG. FIG. 5 shows part of the third audio data D3 generated corresponding to part of the second audio data D2. In the example of FIG. 5, the resampler 40 assumes that the samples A1 to A5, etc. included in the second audio data D2 are sampled at a second period Ts2 that is 80% of the first period Ts1. , interpolation processing and/or decimation processing, the samples B1 to B4, etc. sampled at the first period Ts1 are obtained to generate the third audio data D3.

As shown in FIG. 4, the reproduction time of the third audio data D3 is 80% of the reproduction time T2 of the second audio data D2 and is the same as the reproduction time T1 of the first audio data D1. On the other hand, the frequency of the sine wave contained in the third audio data D3 is 125 times the frequency of the sine wave contained in the second audio data D2, that is, the frequency of the sine wave contained in the first audio data D1. %. That is, the third audio data D3 is audio data whose reproduction time is the same as that of the first audio data D1 and whose pitch is raised to 125%.

Finally, by D/A conversion, an audio signal VO having the same reproduction time as the reproduction time of the third audio data D3, that is, the reproduction time T1 of the first audio data D1 is generated.

FIG. 6 is a diagram showing a specific embodiment of the semiconductor device 1. As shown in FIG. In FIG. 6, the same reference numerals are assigned to the same components as in FIG. In the example of FIG. 6, the semiconductor device 1 includes an audio data storage unit 10, a clock generation unit 20, a time scale conversion unit 30, a resampler 40, a register 50, a D/A converter 60, a low pass filter 70, a ROM (Read Only Memory) 110 , RAM (Random Access Memory) 120 , processor 130 and bus 200 .

Audio data storage unit 10 , time scale conversion unit 30 , resampler 40 , register 50 , D/A converter 60 , low pass filter 70 , ROM 110 , RAM 120 and processor 130 are connected to bus 200 .

The audio data storage unit 10 stores the above-described first audio data D1. The audio data storage unit 10 may be a non-volatile memory in which the first audio data D1 is stored in advance, or for example, the first audio data received by the semiconductor device 1 from an external device via an interface circuit (not shown). A volatile memory that temporarily stores the audio data D1 may be used.

The clock generator 20 generates the first clock signal CK1, the second clock signal CK2, the third clock signal CK3 and the fourth clock signal CK4. Furthermore, the clock generator 20 generates a sixth clock signal CK6.

The time scale conversion section 30 includes a micro control unit (MCU) 31 and a digital signal processor (DSP) 32 . The micro control unit 31 acquires and executes the time scale conversion program 111 stored in the ROM 110 via the bus 200 . The digital signal processor 32 operates according to instructions from the micro control unit 31, and transmits the first audio data D1 stored in the audio data storage unit 10 or the second audio data stored in the RAM 120 via the bus 200. D2 is obtained and the time scale conversion described above is performed to generate second audio data D2. Digital signal processor 32 then causes RAM 120 to store the generated second audio data D2 via bus 200 . Thus, the time scale conversion unit 30 performs time scale conversion by software processing based on the time scale conversion program 111 .

The resampler 40 acquires the second audio data D2 stored in the RAM 120 via the bus 200 and performs the above-described resampling to generate the third audio data D3. The resampler 40 then stores the generated third audio data D3 in the RAM 120 via the bus 200 . Unlike the time scale conversion unit 30, the resampler 40 does not perform software processing based on a program, but performs resampling by hardware processing. That is, the resampler 40 is realized by a dedicated circuit.

The D/A converter 60 acquires the third audio data D3 generated by the resampler 40, performs D/A conversion, and generates an audio signal VO which is an analog signal. Then, the audio signal VO is converted into audio by a speaker (not shown) connected to the semiconductor device 1 .

If resampling is performed by software processing, control is required to synchronize resampling performed by software processing and D/A conversion performed by hardware processing. Since the resampler 40 performs resampling by hardware processing, resampling and D/A conversion can be easily synchronized.

The low-pass filter 70 acquires the second audio data D2 stored in the RAM 120 via the bus 200, performs filtering, and transmits the filtered second audio data D2 to the RAM 120 via the bus 200. be memorized.

The processor 130 writes the aforementioned control information to the register 50 in response to an operation signal from an operation unit (not shown) connected to the semiconductor device 1, for example. The control information stored in register 50 is supplied to time scale converter 30, resampler 40, register 50, D/A converter 60 and low pass filter 70 via bus 200 to control the operation of each of these sections. be done. When the processor 130 writes the desired control information to the register 50, the time scale converter 30, the resampler 40, the D/A converter 60 and the low pass filter 70 operate to obtain the desired audio signal VO. , the processor 130 can be devoted to various kinds of processing necessary for equipment in which the semiconductor device 1 is incorporated, such as motor control and panel control.

As described above, the semiconductor device 1 of the first embodiment includes the audio data storage unit 10 that stores the first audio data D1 including a plurality of samples sampled at the first period Ts1, and the first A clock generator 20 for generating a clock signal CK1 and a second clock signal CK2, and a plurality of samples included in the first audio data D1 in synchronization with the first clock signal CK1. and a time scale conversion unit 30 that converts the second audio data D2 by deleting or duplicating a part of the first audio data D2 by hardware processing in synchronization with the second clock signal CK2. A resampler 40 that converts the resampler 40 into third audio data D3 containing a number of samples different from the number of the second audio data D2 sampled at a period Ts1 of , and the operations of the time scale conversion unit 30 and the resampler 40 are controlled. and a register 50 for storing control information to be executed.

The time scale conversion unit 30 generates the second audio data D2 in which the reproduction time is converted without converting the pitch of the first audio data D1, and the resampler 40 converts the pitch and the pitch of the second audio data D2. Since the third audio data D3 whose reproduction time is converted is generated, the pitch conversion of the first audio data D1 can be realized. Since the resampler 40 performs resampling by hardware processing, for example, as shown in FIG. Even when conversion is performed, the processing load is reduced by the amount of resampling, so a simple micro control unit 31 and digital signal processor 32 can be used. Therefore, according to the semiconductor device 1 of the first embodiment, pitch conversion of voice data can be performed with a relatively small circuit scale.

Further, according to the semiconductor device 1 of the first embodiment, the processor 130 writes desired control information to the register 50 as shown in FIG. Therefore, the processor 130 can concentrate on various processes necessary for equipment in which the semiconductor device 1 is installed.

Further, according to the semiconductor device 1 of the first embodiment, since the resampler 40 performs resampling by hardware processing, the semiconductor device 1 is a D/A converter that converts the third audio data D3 into the audio signal VO. 60, resampling and D/A conversion by hardware processing of the D/A converter 60 can be easily synchronized.

Further, according to the semiconductor device 1 of the first embodiment, the third audio data D3 is data having the same number of samples as the first audio data D1, in which the pitch of the first audio data D1 is changed. By setting the control information, the pitch-converted third audio data D3 can be generated without changing the reproduction time of the first audio data D1.

1-2. Second Embodiment Hereinafter, regarding the semiconductor device 1 of the second embodiment, the same reference numerals are given to the same configurations as in the first embodiment, and the same description as in the first embodiment will be omitted or simplified, and mainly the first embodiment will be described. Contents different from the form will be explained.

FIG. 7 is a diagram showing a configuration example of the semiconductor device 1 of the second embodiment. As shown in FIG. 7, the semiconductor device 1 of the second embodiment includes an audio data storage unit 10, a clock generation unit 20, a time scale conversion unit 30, a resampler 40, and a register as in the first embodiment. 50 and Moreover, the semiconductor device 1 of the second embodiment may include the D/A converter 60 and the low-pass filter 70 as in the first embodiment. Furthermore, the semiconductor device 1 of the second embodiment includes a selector 80 , a selector 90 and a control section 100 .

The audio data storage unit 10 stores first audio data D1 including a plurality of samples sampled at the first period Ts1, as in the first embodiment.

The clock generator 20 generates a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4, and further controls the controller 100 as in the first embodiment. A fifth clock signal CK5 is generated for operation.

The register 50 stores control information for controlling the operations of the time scale converter 30 and the resampler 40 . In the second embodiment, the control information is information for setting the operation mode of the semiconductor device 1 to one of a plurality of operation modes including a first operation mode, a second operation mode, and a third operation mode. It contains operation mode information MD. A first operation mode is an operation mode in which the pitch is changed without changing the reproduction time of the first audio data D1. A second operation mode is an operation mode in which the reproduction time is changed without changing the pitch of the first audio data D1. A third operation mode is an operation mode for changing the reproduction time and pitch of the first audio data D1.

Further, the control information includes first ratio information SR1 and second ratio information SR2 for setting the ratio between the number of samples of the second audio data D2 and the number of samples of the first audio data D1, and the time scale converter. A start bit ST for causing at least one of 30 and resampler 40 to start processing may be included.

The control unit 100 controls operations of the time scale conversion unit 30 , resampler 40 , D/A converter 60 , low pass filter 70 , selector 80 and selector 90 . Specifically, in synchronization with the fifth clock signal CK5, the control unit 100 generates a pulse signal based on the operation mode information MD, the first ratio information SR1, the second ratio information SR2, and the start bit ST. A first start signal ST1, a second start signal ST2, a third start signal ST3, a first selection signal SEL1, a second selection signal SEL2, and ratio information SR are generated. The time scale conversion unit 30 starts the process of generating the second audio data D2 based on the ratio information SR in response to the first start signal ST1, and stops when the process ends. The resampler 40 and the low-pass filter 70 start the process of generating the third audio data D3 based on the ratio information SR in response to the second start signal ST2, and stop when the process ends. The D/A converter 60 starts processing in response to the third start signal ST3, and stops when the processing ends.

The selector 80 selects and outputs the first audio data D1 or the second audio data D2 based on the first selection signal SEL1. Also, the selector 90 selects and outputs the third audio data D3 or the second audio data D2 based on the second selection signal SEL2.

When the first operation mode is set in the operation mode information MD, the control unit 100 outputs the first selection signal SEL1 that causes the selector 80 to select the first audio data D1 and the selector 90 to transmit the third audio data D1. A second selection signal SEL2 for selecting D3 is generated. Also, when the start bit ST changes from inactive to active, the controller 100 generates a first start signal ST1, a second start signal ST2 and a third start signal ST3. Also, the control unit 100 sets the first ratio information SR1 to the ratio information SR. As a result, the time scale converter 30, resampler 40, D/A converter 60, and low-pass filter 70 operate in the same manner as in the first embodiment. Therefore, the audio signal VO generated in the first operation mode is an audio signal whose pitch is changed without changing the reproduction time of the first audio data D1, as in the first embodiment.

Further, when the second operation mode is set in the operation mode information MD, the control unit 100 outputs the first selection signal SEL1 that causes the selector 80 to select the first audio data D1, and the second selection signal SEL1 that causes the selector 90 to select the second audio data D1. A second selection signal SEL2 for selecting the audio data D2 is generated. Also, when the start bit ST changes from inactive to active, the controller 100 generates a first start signal ST1 and a third start signal ST3. Also, the control unit 100 sets the first ratio information SR1 to the ratio information SR. As a result, the time scale converter 30 and the D/A converter 60 operate, and the resampler 40 and low-pass filter 70 do not operate. Therefore, the audio signal VO generated in the second operation mode is an audio signal in which the reproduction time is changed without changing the pitch of the first audio data D1.

Further, when the third operation mode is set in the operation mode information MD, the control unit 100 first generates the first selection signal SEL1 that causes the selector 80 to select the first audio data D1. Also, the control unit 100 generates the first start signal ST1 when the start bit ST changes from inactive to active. Also, the control unit 100 sets the first ratio information SR1 to the ratio information SR. As a result, the time scale converter 30 operates, and the resampler 40, D/A converter 60 and low-pass filter 70 do not operate. Then, the time scale conversion unit 30 generates the second audio data D2 in which the reproduction time is changed without changing the pitch of the first audio data D1.

When the generation of the second audio data D2 is completed, the control unit 100 next sends the first selection signal SEL1 that causes the selector 80 to select the second audio data D2 and the third audio data D3 to the selector 90. A second selection signal SEL2 for selection is generated. The control section 100 also generates a first start signal ST1, a second start signal ST2 and a third start signal ST3. Also, the control unit 100 sets the second ratio information SR2 to the ratio information SR. As a result, the time scale conversion unit 30, the resampler 40, the D/A converter 60, and the low-pass filter 70 operate to change the pitch without changing the reproduction time of the second audio data D2 selected by the selector 80. Then, third audio data D3 is generated. Here, the second audio data D2 selected by the selector 80 is the audio data obtained by changing the reproduction time without changing the pitch of the first audio data D1, as described above. D3 is audio data obtained by changing the reproduction time and pitch of the first audio data D1. Therefore, the audio signal VO generated in the third operation mode is an audio signal obtained by changing the reproduction time and pitch of the first audio data D1. Note that the reproduction time conversion rate and the pitch conversion rate are arbitrarily set by the first ratio information SR1 and the second ratio information SR2.

FIG. 8 shows an example of the second audio data D2, the third audio data D3, and the audio signal VO when the pitch of the first audio data D1 is lowered and the reproduction time is shortened in the third operation mode. It is a diagram. In the example of FIG. 8, the first audio data D1 is audio data of a constant frequency in which the same sine wave is repeated four times in a constant period of time, and its reproduction time is T1. Also, the first ratio information SR1 is set to 75%, and the second ratio information SR2 is set to 67%.

First, one sine wave of the first audio data D1 containing N samples is deleted by the first time scale conversion, and the second audio data D2 with a constant frequency in which the same sine wave is repeated three times is generated. be done. The number of samples of the second audio data D2 is N×0.75, and the reproduction time T2 of the second audio data D2 is shortened to 75% of the reproduction time T1 of the first audio data D1. On the other hand, since the frequency of the sine wave included in the second audio data D2 is the same as the frequency of the sine wave included in the first audio data D1, the pitch does not change before and after the time scale conversion. That is, the second audio data D2 is audio data having the same pitch as the first audio data D1 and having a playback time shortened to 75%.

Next, one sine wave of the second audio data D2 containing N×0.75 samples is removed by a second time scale conversion, and a second sound data D2 of constant frequency in which the same sine wave is repeated twice. Audio data D2 is generated. The number of samples of the second audio data D2 obtained by time scale conversion is N×0.75×0.67, and the reproduction time T3 of the second audio data D2 is equal to the reproduction time T1 of the first audio data D1. is shortened to 50% of On the other hand, the frequency of the sine wave included in the second audio data D2 is the same as the frequency of the sine wave included in the first audio data D1. That is, the second audio data D2 is audio data having the same pitch as the first audio data D1 and having a playback time shortened to 50%.

Next, by resampling, the third audio data D3 including 1.5 times the number of samples of the second audio data D2, which is the reciprocal of the second ratio information SR2, is generated. The reproduction time of the third audio data D3 is 150% of the reproduction time T3 of the second audio data D2 after time scale conversion, and is the same as the reproduction time T2 of the second audio data D2 before time scale conversion. , which is 75% of the reproduction time T1 of the first audio data D1. On the other hand, the frequency of the sine wave included in the third audio data D3 is 67 times the frequency of the sine wave included in the second audio data D2, that is, the frequency of the sine wave included in the first audio data D1. %. That is, the third audio data D3 is audio data in which the reproduction time is shortened to 75% and the pitch is reduced to 67% with respect to the first audio data D1.

Finally, by D/A conversion, an audio signal VO having the same reproduction time as the reproduction time T2 of the third audio data D3 is generated.

FIG. 9 shows an example of the second audio data D2, the third audio data D3, and the audio signal VO when the pitch of the first audio data D1 is increased and the reproduction time is extended in the third operation mode. It is a diagram. In the example of FIG. 9, the first audio data D1 is audio data of a constant frequency in which the same sine wave is repeated four times in a constant period of time, and its reproduction time is T1. Also, the first ratio information SR1 is set to 125%, and the second ratio information SR2 is set to 120%.

First, the first time scale conversion replicates one sine wave of the first audio data D1 containing N samples to generate the second audio data D2 with a constant frequency in which the same sine wave is repeated five times. be done. The number of samples of the second audio data D2 is N×1.25, and the reproduction time T2 of the second audio data D2 is extended to 125% of the reproduction time T1 of the first audio data D1. On the other hand, since the frequency of the sine wave included in the second audio data D2 is the same as the frequency of the sine wave included in the first audio data D1, the pitch does not change before and after the time scale conversion. In other words, the second audio data D2 is audio data having the same pitch as the first audio data D1 and having the reproduction time extended by 125%.

Next, a second time-scale conversion replicates one sine wave of the second audio data D2 containing N×1.25 samples, and a second constant-frequency second audio data D2 of the same sine wave repeated six times. Audio data D2 is generated. The number of samples of the second audio data D2 obtained by time scale conversion is N×1.25×1.20=N×1.5, and the reproduction time T3 of the second audio data D2 is equal to that of the first audio. It is extended to 150% of the reproduction time T1 of data D1. On the other hand, the frequency of the sine wave included in the second audio data D2 is the same as the frequency of the sine wave included in the first audio data D1. That is, the second audio data D2 is audio data having the same pitch as the first audio data D1 and having a reproduction time extended by 150%.

Next, by resampling, the third audio data D3 including about 0.83 times the number of samples of the second audio data D2, which is the reciprocal of the second ratio information SR2, is generated. The reproduction time of the third audio data D3 is approximately 83% of the reproduction time T3 of the second audio data D2 after time scale conversion, and is the same as the reproduction time T2 of the second audio data D2 before time scale conversion. , which is 125% of the reproduction time T1 of the first audio data D1. On the other hand, the frequency of the sine wave included in the third audio data D3 is 120 times the frequency of the sine wave included in the second audio data D2, that is, the frequency of the sine wave included in the first audio data D1. %. That is, the third audio data D3 is audio data whose reproduction time is extended by 125% and whose pitch is increased by 120% with respect to the first audio data D1.

Finally, by D/A conversion, an audio signal VO having the same reproduction time as the reproduction time T2 of the third audio data D3 is generated.

Although the configuration of the example of the semiconductor device 1 of the second embodiment is omitted from the drawing, the clock generator 20 is further added to the semiconductor device 1 of the first embodiment shown in FIG. , and the micro control unit 31 may further function as the above-described control section 100, for example.

According to the semiconductor device 1 of the second embodiment described above, the same effects as those of the semiconductor device 1 of the first embodiment are obtained. Furthermore, according to the semiconductor device 1 of the second embodiment, the first operation mode in which the pitch is changed without changing the reproduction time of the first audio data D1 based on the control information stored in the register 50; It is possible to select the second operation mode in which the reproduction time is changed without changing the pitch of the first audio data D1, or the third operation mode in which the reproduction time and pitch of the first audio data D1 are changed. , high versatility can be achieved.

1-3. Modification FIG. 10 is a diagram showing the configuration of a semiconductor device 1 of a modification. As shown in FIG. 10, the semiconductor device 1 of the modification includes an audio data storage unit 10, a clock generation unit 20, a time scale conversion unit 30, a resampler 40, and a register 50, as in the first embodiment. ,including.

The audio data storage unit 10 stores first audio data D1 including a plurality of samples sampled at the first period Ts1, as in the first embodiment.

The clock generator 20 generates a first clock signal CK1 and a second clock signal CK2, as in the first embodiment.

Synchronizing with the second clock signal CK2, the resampler 40 performs hardware processing to sample the first audio data D1 at the first period Ts1, and samples the first audio data D1 in a number different from that of the first audio data D1. is converted into second audio data D2 containing samples of . Specifically, the resampler 40 assumes that the plurality of samples included in the first audio data D1 are sampled at a second period Ts2 different from the first period Ts1, and assumes that the plurality of samples A plurality of samples sampled at the first cycle Ts1 are obtained by interpolation processing and/or thinning processing based on , and are used as the second audio data D2. Various known techniques can be applied to interpolation processing and/or thinning processing. When the first audio data D1 is compressed audio data, the resampler 40 performs interpolation processing and/or thinning on the first audio data D1 expanded by an audio data expansion unit (not shown). processing may be performed.

In synchronization with the first clock signal CK1, the time scale conversion unit 30 transforms the second audio data D2 into a third audio data obtained by deleting or duplicating some of the samples included in the second audio data D2. Convert to data D3. For example, the deleted or duplicated sample may be part of a plurality of samples that make up a periodically repeating waveform. The third audio data D3 is audio data having the same pitch as the second audio data D2, but different in reproduction speed or reproduction time from the second audio data D2. Various known techniques can be applied to the process of converting the second audio data D2 into the third audio data D3, that is, the so-called time scale conversion process. For example, the time scale conversion unit 30 may perform time scale conversion processing by software processing.

In this embodiment, the third audio data D3 is data with the same number of samples as the first audio data D1, in which the pitch of the first audio data D1 is changed. In other words, the third audio data D3 is audio data with a different pitch and the same reproduction time or reproduction speed as the first audio data D1.

The register 50 stores control information for controlling the operations of the time scale converter 30 and the resampler 40, as in the first embodiment. For example, the control information may include a start bit ST for causing the time scale converter 30 and resampler 40 to start processing. The time scale converter 30 and the resampler 40 start processing when the start bit ST changes from inactive to active, and stop when the processing ends.

Further, the control information includes ratio information SR between the number of samples of the third audio data D3 and the number of samples of the second audio data D2, and the ratio information SR is supplied to the time scale conversion unit 30 and the resampler 40. good too. For example, if the ratio information SR indicates that the number of samples of the third audio data D3 is 75% of the number of samples of the second audio data D2, the resampler 40 is included in the first audio data D1. Assuming that N samples were sampled at a second period Ts2 that is approximately 133% of the first period Ts1, interpolation and/or decimation based on the N samples yields the first period Approximately N×1.33 samples sampled at Ts1 are obtained and used as the second audio data D2. Then, the time scale conversion unit 30 transforms the second audio data D2 into a third audio data D2 containing N samples obtained by deleting 25% of approximately N×1.33 samples contained in the second audio data D2. Convert to audio data D3.

Further, the semiconductor device 1 may include a D/A converter 60, as in the first embodiment. When the semiconductor device 1 includes the D/A converter 60, the clock generator 20 generates the third clock signal CK3 for operating the D/A converter 60. FIG.

As in the first embodiment, the D/A converter 60 converts the third audio data D3 into an analog audio signal VO. Specifically, the D/A converter 60 samples a plurality of samples included in the third audio data D3 at a first period Ts1 in synchronization with the third clock signal CK3 and converts them into analog values. to generate the audio signal VO. The start bit ST is also supplied to the D/A converter 60, and the D/A converter 60 starts processing when the start bit ST changes from inactive to active, and stops when processing ends.

As in the first embodiment, the semiconductor device 1 may include the low-pass filter 70 when it is necessary to reduce aliasing noise generated by resampling in the resampler 40 . When the resampling in the resampler 40 is downsampling, the low-pass filter 70 is provided in the preceding stage of the resampler 40, specifically in the signal path from the output of the audio data storage unit 10 to the input of the resampler 40, If necessary, it is also provided in a signal path subsequent to the resampler 40 , specifically, from the output of the resampler 40 to the input of the time scale conversion section 30 . Further, when the resampling in the resampler 40 is upsampling, the low-pass filter 70 is provided in the subsequent stage of the resampler 40, specifically in the signal path from the output of the resampler 40 to the input of the time scale conversion unit 30. be done. When the semiconductor device 1 includes the low-pass filter 70 , the clock generator 20 generates a fourth clock signal CK4 for operating the low-pass filter 70 and the start bit ST is also supplied to the low-pass filter 70 . The low-pass filter 70 starts processing in synchronization with the fourth clock signal CK4 when the start bit ST changes from inactive to active, and stops when the processing ends.

As in the first embodiment, the clock generator 20 generates the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK3 when the start bit ST changes from inactive to active. The clock signal CK4 may be generated, and the generation of the clock signal may be stopped after a predetermined period of time has elapsed. In this case, the start bit ST may not be supplied to the time scale converter 30, resampler 40, D/A converter 60 and low-pass filter 70. FIG.

Further, as in the first embodiment, a plurality of clock signals out of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 generated by the clock generator 20 may be common.

FIG. 11 is a diagram showing an example of the second audio data D2, the third audio data D3, and the audio signal VO when the pitch of the first audio data D1 is lowered in the semiconductor device 1 of the modification. In the example of FIG. 11, the first audio data D1 is audio data of a constant frequency in which the same sine wave is repeated four times in a constant period of time, and its reproduction time is T1. Also, the ratio information SR is set to 75%.

First, by resampling, the second audio data D2 including approximately 1.33 times as many samples as the reciprocal of the ratio information SR of the number N of samples of the first audio data D1 is generated. The details of this resampling are the same as in the example of FIG. The reproduction time T2 of the second audio data D2 is approximately 133% of the reproduction time T1 of the first audio data D1. On the other hand, the frequency of the sine wave included in the second audio data D2 is 75% of the frequency of the sine wave included in the first audio data D1. That is, the second audio data D2 is audio data in which the reproduction time is extended to about 133% and the pitch is reduced to 75% of the first audio data D1.

Next, one sine wave of the second audio data D2 is removed by time scale conversion to generate third audio data D3 of constant frequency in which the same sine wave is repeated three times. The number of samples of the third audio data D3 is N, and the playback time of the third audio data D3 is 75% of the playback time T2 of the second audio data D2. On the other hand, since the frequency of the sine wave included in the third audio data D3 is the same as the frequency of the sine wave included in the second audio data D2, the pitch does not change before and after the time scale conversion. That is, the third audio data D3 is audio data that has the same pitch as the second audio data D2 and has a reproduction time shortened to 75%. As described above, the second audio data D2 is audio data whose reproduction time is extended to about 133% and the pitch is lowered to 75% of the first audio data D1. D3 is audio data whose reproduction time is the same as that of the first audio data D1 and whose pitch is lowered to 75%.

Finally, by D/A conversion, an audio signal VO having the same reproduction time as the reproduction time of the third audio data D3, that is, the reproduction time T1 of the first audio data D1 is generated.

FIG. 12 is a diagram showing an example of the second audio data D2, the third audio data D3, and the audio signal VO when the pitch of the first audio data D1 is raised in the semiconductor device 1 of the modification. In the example of FIG. 12, the first audio data D1 is audio data of a constant frequency in which the same sine wave is repeated four times in a constant period of time, and its reproduction time is T1. Also, the ratio information SR is set to 125%.

First, by resampling, the second audio data D2 including 0.80 times as many samples as the reciprocal of the ratio information SR of the sample number N of the first audio data D1 is generated. The details of this resampling are the same as in the example of FIG. The reproduction time T2 of the second audio data D2 is 80% of the reproduction time T1 of the first audio data D1. On the other hand, the frequency of the sine wave included in the second audio data D2 is 125% of the frequency of the sine wave included in the first audio data D1. That is, the second audio data D2 is audio data in which the reproduction time is shortened to 80% and the pitch is raised to 125% of the first audio data D1.

Next, one sine wave of the second audio data D2 is replicated by time scale conversion to generate third audio data D3 of constant frequency in which the same sine wave is repeated five times. The number of samples of the third audio data D3 is N, and the playback time of the third audio data D3 is 125% of the playback time T2 of the second audio data D2. On the other hand, since the frequency of the sine wave included in the third audio data D3 is the same as the frequency of the sine wave included in the second audio data D2, the pitch does not change before and after the time scale conversion. In other words, the third audio data D3 is audio data having the same pitch as the second audio data D2 and having the playback time extended by 125%. As described above, the second audio data D2 is audio data in which the reproduction time is shortened to 80% and the pitch is raised to 125% of the first audio data D1. is audio data whose reproduction time is the same as that of the first audio data D1 and whose pitch is raised to 125%.

Finally, by D/A conversion, an audio signal VO having the same reproduction time as the reproduction time of the third audio data D3, that is, the reproduction time T1 of the first audio data D1 is generated.

According to the semiconductor device 1 of the modified example described above, the same effects as those of the first embodiment are obtained.

Note that the selector 80, the selector 90, and the control unit 100 shown in the second embodiment may be added to the semiconductor device 1 of the modified example.

2. Electronic Apparatus FIG. 13 is a functional block diagram showing an example of the configuration of an electronic apparatus according to the present embodiment using the semiconductor device 1 described above. Also, FIG. 14 is a diagram showing an example of the appearance of a smartphone, which is an example of the electronic device of the present embodiment.

An electronic device 300 of this embodiment includes a semiconductor device 1 , an operation unit 330 , a storage unit 340 , a communication unit 350 , a display unit 360 and a sound output unit 370 . Note that the electronic device 300 of the present embodiment may have a configuration in which some of the constituent elements in FIG. 13 are omitted or changed, or other constituent elements are added.

The operation unit 330 is an input device including operation keys, button switches, and the like, and outputs an operation signal to the semiconductor device 1 in accordance with a user's operation. The semiconductor device 1 changes the aforementioned control information according to a signal input from the operation unit 330, for example.

The storage unit 340 stores programs, data, and the like for the semiconductor device 1 to perform various calculation processes and control processes. For example, a plurality of pieces of audio data are stored in the storage unit 340, and the semiconductor device 1 reads one of the plurality of pieces of audio data stored in the storage unit 340 and uses it as the first audio data D1. good too. The storage unit 340 is implemented by, for example, a hard disk, flexible disk, MO, MT, various memories, CD-ROM, DVD-ROM, or the like.

The communication unit 350 performs various controls for establishing data communication between the semiconductor device 1 and an external device of the electronic device 300 .

The display unit 360 is a display device configured by an LCD (Liquid Crystal Display) or the like, and displays various information based on input display signals. The display unit 360 may be provided with a touch panel that functions as the operation unit 330 . For example, the semiconductor device 1 may generate the display signal, or a semiconductor device (not shown) different from the semiconductor device 1 may generate the display signal.

Sound output unit 370 is configured by a speaker or the like, and outputs sound based on an audio signal that is an output signal from semiconductor device 1 .

The electronic device 300 of the present embodiment is equipped with the semiconductor device 1 capable of pitch-converting voice data while having a relatively small circuit scale, so that desired voice can be output at low cost. .

Various electronic devices can be considered as such an electronic device 300, for example, various household electric appliances such as rice cookers, IH cooking heaters, vacuum cleaners, washing machines, electronic clocks, mobile types, laptop types, and tablet types. such as personal computers, mobile terminals such as smartphones and mobile phones, digital cameras, inkjet ejection devices such as inkjet printers, storage area network equipment such as routers and switches, local area network equipment, mobile terminal base station equipment, Televisions, video cameras, video recorders, car navigation devices, real-time clock devices, pagers, electronic notebooks, electronic dictionaries, calculators, electronic game machines, game controllers, word processors, workstations, videophones, security TV monitors, electronic binoculars, POS terminals, electronic thermometers, sphygmomanometers, blood glucose meters, electrocardiogram measuring devices, ultrasonic diagnostic devices, medical devices such as electronic endoscopes, fish finders, various measuring devices, instruments for vehicles, aircraft, ships, etc., flight simulators , head-mounted displays, motion tracing, motion tracking, motion controllers, pedestrian dead reckoning (PDR: Pedestrian Dead Reckoning) devices, and the like.

3. Mobile Object FIG. 15 is a diagram showing an example of a mobile object according to the present embodiment using the semiconductor device 1 described above. A moving body 400 shown in FIG. 15 includes a semiconductor device 1 , controllers 440 , 450 and 460 , a battery 470 and a speaker 480 . It should be noted that the moving body of this embodiment may have a configuration in which some of the constituent elements shown in FIG. 15 are omitted, or other constituent elements are added.

The semiconductor device 1 , the controllers 440 , 450 , 460 and the speaker 480 operate with power supply voltage supplied from the battery 470 .

For example, controllers 440, 450, and 460 each perform various controls such as an attitude control system, rollover prevention system, and brake system.

Speaker 480 is a sound output unit that outputs sound based on an audio signal that is an output signal from semiconductor device 1 .

The moving body 400 of the present embodiment is equipped with the semiconductor device 1 capable of pitch-converting voice data while having a relatively small circuit scale, so that desired voice can be output at low cost. .

As such a moving body 400, various moving bodies are conceivable, and examples thereof include automobiles such as electric vehicles, aircraft such as jet planes and helicopters, ships, rockets, and artificial satellites.

The present invention is not limited to this embodiment, and various modifications can be made within the scope of the present invention.

The above-described embodiments and modifications are examples, and the present invention is not limited to these. For example, it is also possible to appropriately combine each embodiment and each modification.

The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations that have the same function, method and result, or configurations that have the same purpose and effect. Moreover, the present invention includes configurations obtained by replacing non-essential portions of the configurations described in the embodiments. In addition, the present invention includes a configuration that achieves the same effects or achieves the same purpose as the configurations described in the embodiments. In addition, the present invention includes configurations obtained by adding known techniques to the configurations described in the embodiments.

DESCRIPTION OF SYMBOLS 1... Semiconductor device 10... Audio data storage part 20... Clock generation part 30... Time scale conversion part 31... Micro control unit 32... Digital signal processor 40... Resampler 50... Register 60... D/ A converter 70 Low-pass filter 80 Selector 90 Selector 100 Control unit 110 ROM 111 Time scale conversion program 120 RAM 130 Processor 200 Bus 300 Electronic device DESCRIPTION OF SYMBOLS 330... Operation part 340... Storage part 350... Communication part 360... Display part 370... Sound output part 400... Mobile body 440, 450, 460... Controller, 470... Battery, 480... Speaker

Claims (7)

an audio data storage unit that stores first audio data including a plurality of samples sampled in a first period;
a clock generator that generates a first clock signal and a second clock signal;
A time scale for converting the first audio data into second audio data in which part of the plurality of samples included in the first audio data are deleted or duplicated in synchronization with the first clock signal. a conversion unit;
Synchronizing with the second clock signal , the second audio data is converted into third audio data sampled at the first period and including a plurality of samples of a number different from that of the second audio data. A resampler, which is a dedicated circuit for conversion,
and a register storing control information for controlling operations of the time scale converter and the resampler. 2. The semiconductor device according to claim 1, wherein said third audio data is data of the same number of samples as said first audio data, the pitch of said first audio data being changed. 3. The semiconductor device according to claim 1, wherein said audio data storage section, said clock generation section, said time scale conversion section, said resampler, and said register are included in a one-chip integrated circuit device. the control information includes information for setting the operation mode of the semiconductor device to one of a plurality of operation modes including a first operation mode, a second operation mode, and a third operation mode;
the first operation mode is an operation mode in which the pitch is changed without changing the reproduction time of the first audio data;
the second operation mode is an operation mode in which the reproduction time is changed without changing the pitch of the first audio data;
4. The semiconductor device according to claim 1, wherein said third operation mode is an operation mode for changing reproduction time and pitch of said first audio data. 5. A D/A converter for converting said third audio data into an analog signal.
The semiconductor device according to any one of 1. A semiconductor device according to any one of claims 1 to 5;
An electronic device, comprising: a sound output unit that outputs sound based on an output signal from the semiconductor device. A semiconductor device according to any one of claims 1 to 5;
and a sound output unit that outputs sound based on the output signal from the semiconductor device.

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