JPS6083988A - Signal expander - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

(Technical Field) The present invention relates to a signal amplifying device (Zuru 2) that can obtain a double or more magnified signal >'3 with a simple configuration. When enlarging 2i8 or more and displaying it in OR'1'''jQ, a method called "reading twice" is used. Figure 1 shows a conventional system that reads twice; 6' is an electrical configuration diagram showing a part of 6'. In the figure, 101 (a ROM in which image data is stored; 102 is a shift register with parallel input and serial output that stores the output data of the ROM 101; and 103 is a shift register with parallel input and serial output). This is a serial input/parallel output shift register that stores the output data of the register 102. In the case of normal output (equal magnification), the ROM 101 basically stores the data as shown in FIG. 2 (a)) and the same cycle as the readout signal [ltsuk] 1 (see Fig. 2 (b)) is given, and in synchronization with the rising edge of the readout signal, the ROM1
01 to parallel data P1 as shown in FIG. 2(c) is output. Here, the shift register 102 stores this data P1 and outputs the serial data P2 in response to the clock T2, and the shift register 103 stores the serial data P2 and outputs the serial data P2.
3 and outputs parallel data P3, but since this is a normal output case, the above clock T2
and clock T3 have a one-to-one correspondence, and the serial data P
? is read only once. Therefore, from the shift register 103, the image data l)I read out from the ROM 101 becomes data 1)3 as is, and is outputted at cycles 111 of the basic clock To. On the other hand, in the case of double reading (double enlargement), the period of the read clock Ti is 218 as shown in Figure 2 (-), that is, the period obtained by multiplying the period 1yJ of the basic clock To by the enlargement 41%. , iM4 column data), Ll, Figure 2 (/4\)
J, sea urchin 4Tru. Also, clock-1-2, "l' 3
Therefore, the output of the shift register 102 is read twice as shown in FIG.・Register 10
3 is enlarged twice and a data P3 as shown in FIG. 2 is output. By the way, such a conventional device j,',i lJ,' J
, 5 is converted to serial as described above /j'
It is safe to read t'-ta 1-) 2 with the high-speed double reading clock -3. To do this, the basics are 1" + l J, 38 (using a fast pulse of 43 or higher)
If it's iJ, it won't work, ROM a output clock 1-1
It is necessary to separately install a clock circuit using a 1/1EPO crystal oscillator. ', lyri circuit (!, set

[Doing so is wasteful and inefficient. (Object of the Invention) An object of the present invention is to realize a signal enlarging device that can obtain enlarged image data (enlarged signal) with a simple configuration. (Structure of the Invention) The present invention that achieves this object includes a ROM in which signal data is stored, at least two data selectors that receive the output of the ROM in parallel, and a timing pulse that drives them. The present invention is characterized in that it is configured to control the outputs of each of the data selectors and obtain expanded signal data from a combination of the outputs. (Example) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Fig. 3 is an electrical configuration diagram showing an embodiment of the present invention. In the figure, 1 indicates the area where image data is stored. ROM, 2.
Reference numeral 3 designates a latch circuit that receives the parallel output of the ROM 1 and stores the .tau.-row. , l<OM 1, for example, [)()~I)717)F3jitsu1- is used. Latch circuit 2 is used for storing -11, °I of i'+, latch circuit 3 is 11
, C)) - Evening:, l Ir? Other than Kaito 011T ÷ 3
．． D; I'l1 used for lj storage, knob circuit 2
．． The illumination of 3 is carried out by the first switching switch SW At the Nirefta, 1, 2, 1° 1 expansion data is obtained from the combination U of the outputs of these data selectors and stored in the data register 6. 7 is an oscillator that generates clock pulses, and an oscillator for the 81J nib. Receives the output of 7 (pull 1, /2 frequency divider (・1, 1
For example, in addition to crystal oscillators, timer ICs, etc. should also be used to avoid the problem of upper frequency limits.
<It depends on how you use it. The frequency division of the oscillator 7 is repeated.
(Clock pulse generation circuit is configured +l sW
? 1, L 55 Oscillator 7 or frequency divider 8 output I+
11114'1. The second VJ exchange switch that selects htfi (there is one, and this selection switch, Izzi SW
2) Select t+, /,=ri=(E mink signal is RO
M1. It is input to the wrap circuit 2.3 (Figure 1! v') and the data selector 4.5. This timing signal is
The signal is input to the data selector 4 as an XY selection signal to the SA input terminal and to the data selector 5 at the S[1 input terminal, respectively, to perform XY selection. As for the XYifl selection mode, for example, X selection can be used at 1'', and Y selection can be used at 0''. Note that DBI to DB3 are data buses. The operation between stations configured in this way is as follows. In the case of normal output selection, switch, switch SVV
+ is set to the X1 side, and S W 2 is set to the Noonru side. In this state, when reading the basic clock To or ROMl, the clock r1 occurs, and the image in ROMi is FJ+7-.
Output the data to the data bus D B l.
The j jlQ column data is latched into the latch circuit 2 by the timing clock [I] from the clock pulse generation circuit at the time when the data is established. The data is then output to the data bus DB2. In addition, it is also possible to set the changeover switch to SW+, SW2, etc. . Next, the behavior when selecting the 2-8 horn (for 'l < ,, I
I light 1゜In this case, selector switch SW'll, l,
SW2 is set to the 218 side, and SW2 is set to the 218 side. Gl), J timing boot II. The mark shown at 1b1 in Figure 2 (Similar to 3, To is basically ri[]tsuku, l” + IJROM
: Ai output clock, in this case [yo2 (f'j (
:;"C out ``There is 1 tsuku C. This T + 1'' tsuku is put into ROM1 by hand, and II OM
]-1 in data bus 1.1 is output onto node bus D131. ) +3. After j'-ta is established in J,
When the timing clock [1] from the clock pulse light 71 circuit is reached, data is latched into the latch circuit 3. At this time, the belt 1 circuit 2 is switched to C- by the selector switch SW1.
It doesn't work because it's either '1' or '11-'. Therefore, the data is stored only in the latch circuit 33. The γ-data taken into the latch circuit 3 is transferred to the data bus I)B
Output on x. , R41J in FIG. 4, the data D+1~ established on the data bus DB3 in this way
1) Shows 7. And this data is data selector 4
．． 5 is commonly input. The input for each data selector is
As shown in the figure 1. ”, the sea urchin is divided into X-manpower and Y-manpower,
The X input of the data selector 4 is manually input with l)o''D3 bit data, and the Y input is manually input with D4 to D7 bit data, and the data selector 5 is also input with l1JJ.These data selectors 4 and 5 is the double readout L:
One signal T1 is inputted and serves as an XY selection signal. That is, as shown in -[4 in FIG. 4, when it is at the "1" level, the X input data is transmitted to the output side, and when it is at the "0" level, the Y input data is transmitted to the output side. 1, that is, when X input is selected, DODo as shown in 1-)5.
DI DI D2 'D2 DS DS is output and stored in data register 6, Y input selection [I\- is D4
D4 DS, DS, Ds DG D? 'Dv is output and stored in the data register 6. At this point, data register 6 contains Do Do'D+ DI D2 D2 DS DS D
4 D41,)s Ds Da DG D? +)? 2 times enlarged data is obtained.
, the twins will repeat the same action 4 times, as shown in Figure 4. -F) E's explanation was about expanding (i:j @ data to 211X, but expanding η to 3 times
) or can be constructed in the same way. Fig. 5 is a block diagram showing an embodiment of the present invention in which 3 times enlarged data is included. Adding the same symbol () to Figure 11 +5 - (,11)'
14 is a data selector that receives the output of ROM1 in parallel, and 15 is a data register that receives the output J of each data selector.
Equation 111: Get the power of the three people x, y, and z, and get the power of the three people! is <111 i; due to the selection signals SA and SB.
) 1, that is, each 1-ta selector is the SA large input Wl j
' and 88 human power OA++ child, SA Shintaldo Ss Shinyumi's silk [ゝ1tJ (x, Y. / is selected 1, Fig. 6 1.12, SA, 5
811” + Wj 1 small diagram showing the relationship between X, Y, and Z selections (
There are 12 examples iJ, SA=・1. Se=・0 throat,
The data is selected and transmitted to the output side. These J, Eel, SA, and 3B signals can be generated using a ternary counter. Basically, the input pulse is J (if one pulse is used). The operation of the apparatus constructed as described above will be explained with reference to the timing diagram p-1- which shows the operation of each part in FIG. Two Dos are input to the X input of the data selector 11,
For Y input, D2. l) 3 is input, 2 DSs are input to the X input, - furthermore, DG and DI are input to the There are two inputs: L)L. Also, two 1] 1 are input to the X input of the data selector 13,
Two D4s are applied to the Y input, and l)6 to the 7 input. D
? is entered. Further, two D2's are input to the X input of the data selector 14, D→, 1]5 are input to the Y input, and two [)7's are input to the 7 manual input. The ro in Fig. 7 is basically a ROM read [], and T+ is a ROM read [J], and in this case, it is a triple read (-). Picture (
data bus I) 11+ l-4=1
Output. After the music number τ1 data P+ reaches 1111' in the data bust, the SA (+ffi signal rs and the SB signal T6 enter their respective data selectors.SA = 0, S
[10 Noso, as is clear from Figure 6, X is luck I
I<=:Reru. Therefore, X people/J for each data selector
(/output) is transferred to the J side, and the L is stored in the data register 15.
J, 'l',) o l:) (l D (11 I
D+ DI D2 8 pins 1- of D2 are stored. 5
When A=1,5a=O, Y) baItI! LL", and the data register 15 contains D21.)31')31-
)31. )-1D4 4])5 8 bits are SA/
When it becomes 0, SB -1, it becomes /selection mode and data selector 1! '] is l)s Ds D6D6De +)
? +, )? +, )? ε1 pits are stored respectively. This 11.1' point ()-ta register 15 contains 3
Double enlarged data 1)1. I feel 4c for being called 111. Hereinafter, the same operation will be repeated as shown in FIG. As described above, according to the present invention, by using a plurality of )-1 talerectors, the number can theoretically be expanded to as many as 18. Types of data selectors include those that convert from 2 lines to 1 line (see 4.5 in Figure 33), those that convert from 4 lines to 1 line (see 11 to 14 in Figure 5), or those that convert from 8 lines to 1 line (see 11 to 14 in Figure 5). There are some that convert to one line. By appropriately combining these data selectors, it is possible to expand the data of the integer i8. When the data is expanded, the CRT-Kasa display device shows (-[
An image enlarged to an integral multiple of Q will be displayed. In the above description, the data stored in the ROM is exemplified as image data, but it is not necessarily limited to image data, and other types of data may be used. Further, the number of bits handled for data need not be limited to 8 bits, and may be any number of bits. (Effects of the Invention FA) As explained above, according to the present invention, by using a number of data selectors corresponding to the data expansion rate, the outputs of these data selectors are combined to easily expand the signal expansion data. ! 1. /, 17. It can be disciplined by children.

[Brief explanation of the drawing]

Figure 1 is an electrical configuration diagram of a conventional station 11°7 (partial) that performs 21 readings, Figure 2 is a timing chart to explain the operation of the 1p, z> device, and Figure 3 is a Figure 4 is an electrical block diagram showing one embodiment of the invention, and Figure 4 is a timing chart showing its operation. Figure 6 is an electrical block diagram showing another embodiment of the invention. Yes, Y. FIG. 7 is an explanatory diagram showing the switching of the selection, and FIG. 7 shows the timing of the operation. 1...ROM 2.3...Flip circuit 4.5.11
~14...Data [! Retata 6.15... Data register 7... Oscillator 8... Frequency divider SW1. SW2...Switching switch f DB+~DB3...Data bus

Claims (1)

[Claims] 1) At least two data selectors that receive the output of the OM in parallel, such as a ROM in which signal data is stored, and that generate timing pulses to drive them.
The cock pulse light circuit is configured to have one circuit, and is expanded from the combination of the outputs of the four outputs of each data selector to obtain a data selector. To・''ru (1.I')'jL humanoid d0