JP7287947B2 - ダイレクト・メモリ・アドレス変換の効率的なテストのための集積回路、およびコンピュータ実装方法 - Google Patents
ダイレクト・メモリ・アドレス変換の効率的なテストのための集積回路、およびコンピュータ実装方法 Download PDFInfo
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- JP7287947B2 JP7287947B2 JP2020506774A JP2020506774A JP7287947B2 JP 7287947 B2 JP7287947 B2 JP 7287947B2 JP 2020506774 A JP2020506774 A JP 2020506774A JP 2020506774 A JP2020506774 A JP 2020506774A JP 7287947 B2 JP7287947 B2 JP 7287947B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
- G06F11/2635—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers using a storage for the test inputs, e.g. test ROM, script files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/287—Multiplexed DMA
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
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- Computing Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Debugging And Monitoring (AREA)
- Bus Control (AREA)
- Memory System (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
Claims (17)
- 集積回路であって、
複数の変換入力を含む変換テーブル(TVT)であって、前記複数の変換入力のそれぞれが、前記集積回路に接続された複数のエージェントのうちの1つに対するダイレクト・メモリ・アクセス(DMA)アドレスを変換するための変換バリデーション入力(TVE)を含む、前記変換テーブルと、
前記変換テーブルにランダム発生信号を供給するランダムDMAモード(RDM)回路であって、テスト・モード中に前記変換テーブルの入力をランダムに選択し、前記変換テーブルの複数の変換入力から全てを選択する、前記RDM回路と、
を備える、集積回路。 - 前記集積回路に接続された単一のエージェントだけがあるとき、前記RDM回路が、前記変換テーブルの複数の変換入力の全てからランダムに選択する、請求項1に記載の集積回路。
- 前記RDM回路が、
マルチプレクサの指定された入力に接続されたランダム発生器信号と、
前記指定された入力を選択する前記マルチプレクサの選択入力と、
テスト中に前記変換テーブルの入力をランダムに選択するために、前記テスト・モード中に前記ランダム発生器信号を供給する前記マルチプレクサの出力と
を備える、請求項1に記載の集積回路。 - 前記変換テーブルが、変換制御入力(TCE)を含むテーブルを指し示す前記複数のエージェントのそれぞれに対する変換バリデーション入力を含む変換バリデーション・テーブルであり、前記RDM回路が、前記変換制御入力を含むテーブルにおける変換制御入力を指し示す変換バリデーション入力をランダムに選択する、請求項1に記載の集積回路。
- 前記RDMが、変換バリデーション入力をランダムに選択することによって前記変換制御入力をランダムに選択する、請求項4に記載の集積回路。
- 前記変換テーブルの各入力におけるDMAアドレスを変換する前記TVEが、変換テーブル・アドレスと、変換制御入力ツリーの深さと、変換制御入力を含むテーブル・サイズと、入出力ページ・サイズとを含む、請求項5に記載の集積回路。
- 前記エージェントが、中央処理装置と、少なくとも1つのグラフィックス処理ユニットとを備える、請求項1に記載の集積回路。
- 前記集積回路が、リンク処理ユニットの一部である、請求項1に記載の集積回路。
- 前記リンク処理ユニットが、中央処理装置を有する前記集積回路上に作製される、請求項8に記載の集積回路。
- コンピュータの処理により集積回路をテストするコンピュータ実装方法であって、
変換テーブル(TVT)に複数の変換入力をロードすることであって、前記複数の変換入力のそれぞれが、前記集積回路に接続された複数のエージェントのうちの1つに対するダイレクト・メモリ・アクセス(DMA)アドレスを変換するための変換バリデーション入力(TVE)を含む、前記ロードすることと、
前記変換テーブルにランダム発生信号を供給し、テスト・モードで前記集積回路に接続された単一のエージェントを使用して、変換情報を有する前記変換テーブルの入力をランダムに選択することによって、前記変換テーブルのすべての変換入力をテストし、単一のエージェントを使用してアドレス変換の複数の連続テストを実行すること、
を含む、方法。 - マルチプレクサの入力にランダム信号を提供することと、
前記マルチプレクサへの選択入力を使用して前記ランダム信号を選択することと、
前記テスト・モード中に前記変換テーブルの入力をランダムに選択するために前記マルチプレクサから前記変換テーブルに前記ランダム信号を提供することと
をさらに含む、請求項10に記載の方法。 - 前記ランダム信号が4ビットであり、前記変換テーブルが16の入力を含む、請求項11に記載の方法。
- 前記変換テーブルが、変換制御入力(TCE)を含むテーブルを指し示す前記複数のエージェントのそれぞれに対する変換バリデーション入力を含む変換バリデーション・テーブル(TVT)である、請求項10に記載の方法。
- 前記変換バリデーション入力が、変換テーブル・アドレス(TTA)と、変換制御入力ツリーの深さと、変換制御入力を含むテーブル・サイズと、入出力ページ・サイズとを含む、請求項13に記載の方法。
- 前記エージェントが、中央処理装置と、少なくとも1つのグラフィックス処理ユニットとを備える、請求項10に記載の方法。
- 集積回路上のリンク処理ユニットの一部として実施される、請求項10に記載の方法。
- 前記リンク処理ユニットが、中央処理装置を有する前記集積回路上に作製される、請求項16に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US15/675,717 US10169185B1 (en) | 2017-08-12 | 2017-08-12 | Efficient testing of direct memory address translation |
US15/675,717 | 2017-08-12 | ||
PCT/IB2018/055908 WO2019034960A1 (en) | 2017-08-12 | 2018-08-06 | EFFECTIVE TEST OF DIRECT MEMORY ADDRESS TRANSLATION |
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JP2020529683A JP2020529683A (ja) | 2020-10-08 |
JP2020529683A5 JP2020529683A5 (ja) | 2021-02-12 |
JP7287947B2 true JP7287947B2 (ja) | 2023-06-06 |
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US (4) | US10169185B1 (ja) |
JP (1) | JP7287947B2 (ja) |
CN (1) | CN110945485B (ja) |
DE (1) | DE112018004144T5 (ja) |
GB (1) | GB2578412B (ja) |
WO (1) | WO2019034960A1 (ja) |
Families Citing this family (2)
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US10169185B1 (en) * | 2017-08-12 | 2019-01-01 | International Business Machines Corporation | Efficient testing of direct memory address translation |
US11074194B2 (en) | 2019-02-21 | 2021-07-27 | International Business Machines Corporation | Managing direct memory access |
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JP2013539098A (ja) | 2010-08-04 | 2013-10-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | I/oメッセージの影響を受ける1つ又は複数個のパーティション化可能なエンドポイントを決定するデータ処理システム |
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JP2882426B2 (ja) * | 1991-03-29 | 1999-04-12 | 株式会社アドバンテスト | アドレス発生装置 |
US8843727B2 (en) * | 2004-09-30 | 2014-09-23 | Intel Corporation | Performance enhancement of address translation using translation tables covering large address spaces |
US7444493B2 (en) | 2004-09-30 | 2008-10-28 | Intel Corporation | Address translation for input/output devices using hierarchical translation tables |
US20060284876A1 (en) * | 2005-06-15 | 2006-12-21 | Low Yun S | Method and apparatus for programming an input/output device over a serial bus |
US20080168208A1 (en) * | 2007-01-09 | 2008-07-10 | International Business Machines Corporation | I/O Adapter LPAR Isolation In A Hypertransport Environment With Assigned Memory Space Indexing a TVT Via Unit IDs |
JP2010244165A (ja) * | 2009-04-02 | 2010-10-28 | Renesas Electronics Corp | 半導体集積回路、及び半導体集積回路の制御方法 |
US8386747B2 (en) * | 2009-06-11 | 2013-02-26 | Freescale Semiconductor, Inc. | Processor and method for dynamic and selective alteration of address translation |
JP5782740B2 (ja) * | 2011-02-21 | 2015-09-24 | 富士電機株式会社 | スイッチング電源の制御用半導体装置 |
US8386679B2 (en) * | 2011-04-12 | 2013-02-26 | International Business Machines Corporation | Dynamic allocation of a direct memory address window |
US9378150B2 (en) * | 2012-02-28 | 2016-06-28 | Apple Inc. | Memory management unit with prefetch ability |
US9811472B2 (en) | 2012-06-14 | 2017-11-07 | International Business Machines Corporation | Radix table translation of memory |
US9600419B2 (en) | 2012-10-08 | 2017-03-21 | International Business Machines Corporation | Selectable address translation mechanisms |
US9792222B2 (en) | 2014-06-27 | 2017-10-17 | Intel Corporation | Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure |
US10026500B2 (en) * | 2015-11-13 | 2018-07-17 | International Business Machines Corporation | Address translation stimuli generation for post-silicon functional validation |
US10169185B1 (en) * | 2017-08-12 | 2019-01-01 | International Business Machines Corporation | Efficient testing of direct memory address translation |
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- 2018-08-06 DE DE112018004144.1T patent/DE112018004144T5/de active Pending
- 2018-08-06 GB GB2002808.0A patent/GB2578412B/en active Active
- 2018-08-06 CN CN201880048578.0A patent/CN110945485B/zh active Active
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JP2013539098A (ja) | 2010-08-04 | 2013-10-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | I/oメッセージの影響を受ける1つ又は複数個のパーティション化可能なエンドポイントを決定するデータ処理システム |
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JP2020529683A (ja) | 2020-10-08 |
US10169185B1 (en) | 2019-01-01 |
DE112018004144T5 (de) | 2020-04-23 |
US10481991B2 (en) | 2019-11-19 |
CN110945485A (zh) | 2020-03-31 |
US20190050314A1 (en) | 2019-02-14 |
WO2019034960A1 (en) | 2019-02-21 |
CN110945485B (zh) | 2023-08-29 |
US10489261B2 (en) | 2019-11-26 |
US20190050315A1 (en) | 2019-02-14 |
GB202002808D0 (en) | 2020-04-15 |
GB2578412A (en) | 2020-05-06 |
US10169186B1 (en) | 2019-01-01 |
GB2578412B (en) | 2020-11-11 |
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