JP7238270B2 - Wafer processing tape and semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a wafer processing tape and a method of manufacturing a semiconductor device.

A general method for manufacturing a semiconductor device includes a step of attaching a wafer processing tape having elasticity and adhesiveness to a semiconductor wafer, and cutting the semiconductor wafer on the wafer processing tape to divide it into a plurality of chips. a step of expanding the wafer processing tape to widen the intervals between the plurality of chips; and a step of picking up the plurality of chips. As a wafer processing tape used in the above semiconductor device manufacturing method, an adhesive film (dicing tape) having a base layer and an adhesive layer, and an adhesive layer (die bonding film) provided on the adhesive layer of the adhesive film ) and a dicing die-bonding film are proposed.

The step of cutting the semiconductor wafer is generally performed using a dicing blade, and when the dicing die-bonding film is used, the semiconductor wafer and the die-bonding film are cut together. However, in such a method, defects such as chip chipping and chip cracking are likely to occur as the thickness of the wafer to be cut is reduced.

On the other hand, in recent years, so-called stealth dicing has been proposed as a method for cutting a semiconductor wafer, in which a laser processing apparatus is used to cut the wafer without contacting the wafer. As an example of a method for cutting a semiconductor wafer by stealth dicing, Patent Document 1 describes (1) a semiconductor wafer to which a dicing tape is attached via a die bonding film, and a laser beam focused on the inside thereof. A step of forming a modified region by multiphoton absorption in the inside of the semiconductor wafer by irradiating the semiconductor wafer, and forming a portion to be cut in the modified region; and cutting and dividing the semiconductor wafer and die bond film along predetermined cutting portions.

According to the method for cutting a semiconductor wafer disclosed in Patent Document 1, the semiconductor wafer and the die bond film are cut without contacting the semiconductor wafer by expanding the dicing tape after irradiating the semiconductor wafer with a laser beam. be able to. Therefore, it is possible to eliminate defects such as chip chipping and chip cracking, which are likely to occur when a dicing blade is used. The cutting method by stealth dicing is particularly effective when the thickness of the wafer is reduced to 50 μm or less, for example.

Japanese Patent No. 4358502 JP 2009-164556 A Japanese Patent No. 5298588 JP 2017-005160 A

As a method for improving the cuttability of a semiconductor wafer and a die bond film by stealth dicing, Patent Document 2 discloses that expansion is performed under a low temperature condition of -15 to 5 ° C. to suppress elongation of the die bond film and reduce stress. discloses a method for increasing the When the expansion is performed under low-temperature conditions, elongation of the die-bonding film can be suppressed. In addition, in relation to the stealth dicing method, various developments are being made on wafer processing tapes. However, when the adhesion of the die-bonding film to the adhesive layer becomes insufficient under low-temperature conditions, or when the expanding speed is increased or the amount of expansion is increased in order to ensure the cuttability of the semiconductor wafer and the die-bonding film, Due to the impact and increased stress at the time of splitting, the peripheral portion of the die-bonding film tends to separate from the adhesive layer and scatter. If the die-bonding film scatters and adheres to the wafer, it hinders the pick-up operation or lowers the yield, so improvements are desired.

As a method for preventing the die-bonding film from scattering in the expanding step, there is a method of increasing the adhesion of the die-bonding film to the adhesive layer to increase the holding power against the impact and stress increase during division. However, when the adhesive strength is increased, the chip becomes difficult to peel off during the pick-up process, and there is a possibility that pick-up failure or chip cracking may occur. There is also a method of slowing down the expansion speed and reducing the amount of expansion to prevent the die-bonding film from scattering. However, in that case, it is difficult to ensure good cuttability of the die-bonding film, and much time and effort are required to optimize the expansion conditions.

Further, Patent Document 3 discloses that the die-bonding film has a notch or a notch at the outer peripheral edge to disperse the stress and prevent the die-bonding film from scattering. However, if there is a notch or notch in the outer peripheral edge, there is a possibility that the outer peripheral edge will be bent when the die-bonding film is pre-cut or attached to the dicing tape. On the other hand, Patent Document 4 discloses that scattering is prevented by reducing the diameter of the die-bonding film. However, if the diameter of the die-bonding film is small, there is a concern that the die-bonding film may not be attached to the entire semiconductor wafer if misalignment occurs during attachment to the semiconductor wafer.

In view of such a background, one aspect of the present invention aims to provide a wafer processing tape and a method for manufacturing a semiconductor device that can suppress scattering of an adhesive layer when the wafer processing tape is expanded. and

A wafer processing tape according to one aspect of the present invention is a wafer processing tape that is used by being attached to a semiconductor wafer, and includes an adhesive film having a base layer and an adhesive layer provided on the base layer; and a circular adhesive layer provided on the adhesive layer of the film to which the semiconductor wafer is attached, and the adhesive layer is formed with cuts inside the outer peripheral edge of the adhesive layer.

With this wafer processing tape, the semiconductor wafer can be separated into a plurality of semiconductor chips by expanding the wafer processing tape while the semiconductor wafer is attached to the adhesive layer. At this time, since cuts are formed in the adhesive layer, cracks progress from the cuts. Therefore, it is possible to disperse the stress generated in the adhesive layer, and control the direction of occurrence and progress of cracks generated in the adhesive layer. Thereby, scattering of the adhesive layer can be suppressed. Moreover, since the incision is formed inside the outer peripheral edge of the adhesive layer, cracks progressing from the incision can be prevented from reaching the outer peripheral edge of the adhesive layer and scattering fragments of the adhesive layer. can be suppressed.

In addition, before expanding the wafer processing tape, by forming lines to be divided on the semiconductor wafer by a method such as stealth dicing or blade half-cut dicing, when the wafer processing tape is expanded, the semiconductor wafer can be separated into multiple semiconductor chips.

The incision may be formed outside the wafer bonding planned region to which the semiconductor wafer of the adhesive layer is to be bonded. In this wafer processing tape, since the notch is formed outside the wafer bonding planned area, when the wafer processing tape is expanded in a state where the semiconductor wafer is bonded to the adhesive layer, the wafer processing tape is separated. It is possible to suppress cracking of the adhesive layer on each semiconductor chip.

Incidentally, the stress generated in the adhesive layer when the wafer processing tape is expanded increases with increasing distance from the center of the adhesive layer, ie, closer to the outer edge. Therefore, from the viewpoint of stress dispersion, it is preferable that the formation position of the cut is closer to the outer peripheral edge of the adhesive layer.

Therefore, the outer tip of the notch, which is positioned closest to the outer peripheral edge of the adhesive layer, is positioned outside the intermediate position between the outer peripheral edge of the adhesive layer and the outer peripheral edge of the adhesive layer, to which the semiconductor wafer is to be attached. may be located in In this wafer processing tape, since the outer tip of the notch is located outside the middle position between the outer periphery of the wafer bonding area and the outer periphery of the adhesive layer, when the wafer processing tape is expanded, The stress generated in the adhesive layer can be distributed appropriately. Thereby, scattering of the adhesive layer can be further suppressed.

D is the distance from the wafer bonding area where the semiconductor wafer of the adhesive layer is to be bonded to the outer peripheral edge of the adhesive layer, and from the outer peripheral edge of the adhesive layer to the outer tip of the notch located closest to the outer peripheral edge side of the adhesive layer. is d1, the relationship 0.05≤(d1/D)≤0.5 may be satisfied. In this wafer processing tape, since the relationship of 0.05≦(d1/D)≦0.5 is satisfied, cracks progressing from the incisions reach the outer periphery of the adhesive layer, scattering fragments of the adhesive layer. It is possible to appropriately disperse the stress generated in the adhesive layer when the wafer processing tape is expanded while suppressing the deformation.

D is the distance from the wafer sticking area of the wafer processing tape to which the semiconductor wafer is stuck to the outer edge of the adhesive layer, and the inner tip of the notch located closest to the wafer sticking area side from the outer edge of the wafer sticking area. d2, the relationship 0.1≦(d2/D)≦0.7 may be satisfied. Since this wafer processing tape satisfies the relationship of 0.1≦(d2/D)≦0.7, it suppresses cracking of the adhesive layer on each separated semiconductor chip, while suppressing the occurrence of cracks in the adhesive layer. The stress generated in the adhesive layer when the tape is expanded can be distributed appropriately. Further, even if the position of the semiconductor wafer with respect to the wafer processing tape is shifted due to a manufacturing error or the like, it is possible to prevent the notches from being arranged on the semiconductor wafer.

The cut may be inclined with respect to the radial direction of the adhesive layer. In this wafer processing tape, since the incisions are inclined with respect to the radial direction of the adhesive layer, cracks progressing from the incisions are suppressed from reaching the outer peripheral edge of the adhesive layer and the wafer bonding area. can do.

The notch may be formed in an X shape. In this wafer processing tape, since the cuts are formed in an X shape, cracks can be propagated from the four tips of the cuts. Thereby, the stress generated in the adhesive layer when the wafer processing tape is expanded can be appropriately dispersed.

The cut may be formed in an I-shape inclined in the circumferential direction of the adhesive layer. In this wafer processing tape, since the cuts are formed in an I-shape inclined in the circumferential direction of the adhesive layer, cracks can progress from the two ends of the cuts. Thereby, the stress generated in the adhesive layer when the wafer processing tape is expanded can be appropriately dispersed.

A plurality of cuts may be formed in the circumferential direction of the adhesive layer. In this wafer processing tape, since a plurality of cuts are formed in the adhesive layer in the circumferential direction, the stress generated in the adhesive layer when the wafer processing tape is expanded can be dispersed appropriately.

In addition, when each of the plurality of cuts is formed in an I-shape inclined in the circumferential direction of the adhesive layer, compared to the case where each of the plurality of cuts is formed in an X-shape, the adjacent cuts It is possible to secure a sufficient distance between the tips of the inserts. As a result, it is possible to prevent adjacent cuts from being connected by a crack progressing from each cut, so that scattering of fragments of the adhesive layer can be suppressed.

A plurality of cuts may be formed at regular intervals in the circumferential direction of the adhesive layer. In this wafer processing tape, since a plurality of notches are formed at equal intervals in the circumferential direction of the adhesive layer, the stress generated in the adhesive layer when the wafer processing tape is expanded can be dispersed appropriately. can.

A plurality of cuts may be formed on the same circumference. In this wafer processing tape, since the plurality of cuts are formed on the same circumference, the plurality of cuts can be easily formed.

A plurality of cuts may be formed on two or more different concentric circles. In this wafer processing tape, since a plurality of cuts are formed on two or more different concentric circles, the generation and direction of cracking occurring in the adhesive layer can be more finely controlled.

A plurality of cuts may overlap when viewed from the radial direction of the adhesive layer. In this wafer processing tape, since the plurality of cuts overlap when viewed from the radial direction of the adhesive layer, the number of cracks generated in the adhesive layer when the wafer processing tape is expanded can be increased. As a result, it is possible to disperse the stress generated in the adhesive layer, and to more finely control the generation and propagation direction of cracks generated in the adhesive layer.

A plurality of cuts may not overlap when viewed from the radial direction of the adhesive layer. In this wafer processing tape, since the plurality of cuts do not overlap when viewed from the radial direction of the adhesive layer, the cuts can be easily formed, and cracks progressing from each cut can cause adjacent cuts to crack. can be prevented from being connected. As a result, scattering of fragments of the adhesive layer 3 can be suppressed.

A plurality of cuts may be formed in the same shape. In this wafer processing tape, since the plurality of cuts have the same shape, it is possible to easily control the generation and progress of cracks in the adhesive layer.

A plurality of cuts may be formed in two or more different shapes. In this wafer processing tape, since the plurality of cuts are formed in two or more different shapes, it is possible to finely control the generation and progress of cracks in the adhesive layer.

The interval between adjacent cuts may be 2 mm or more and 40 mm or less. In this wafer processing tape, since the interval between adjacent cuts is 2 mm or more and 40 mm or less, it is possible to prevent the adjacent cuts from being connected by cracks progressing from each cut and scattering fragments of the adhesive layer. At the same time, the stress generated in the adhesive layer when the wafer processing tape is expanded can be appropriately dispersed.

A method of manufacturing a semiconductor device according to one aspect of the present invention is a method of manufacturing a semiconductor device using any of the wafer processing tapes described above, wherein the adhesive layer of the wafer processing tape is attached to a semiconductor wafer. It comprises a sticking step, an expanding step of separating the semiconductor wafer into a plurality of semiconductor chips by expanding the wafer processing tape, and a picking up step of picking up the semiconductor chips from the adhesive film.

In this semiconductor device manufacturing method, the semiconductor wafer is formed into a plurality of semiconductor chips by performing an expanding step of expanding the wafer processing tape after performing a bonding step of bonding the adhesive layer of the wafer processing tape to the semiconductor wafer. separate into At this time, since cuts are formed in the adhesive layer, cracks progress from the cuts. Therefore, it is possible to disperse the stress generated in the adhesive layer, and control the direction of occurrence and progress of cracks generated in the adhesive layer. Thereby, scattering of the adhesive layer can be suppressed. In addition, since the cut is formed inside the outer peripheral edge of the adhesive layer, it is possible to prevent cracks progressing from the cut from reaching the outer peripheral edge of the adhesive layer and scattering pieces of the adhesive layer. can do. As a result, peeling of the outer peripheral edge of the adhesive layer can be suppressed, so scattering of the adhesive layer can be further suppressed.

In addition, in the step prior to the expanding step, the semiconductor wafer can be separated into a plurality of semiconductor chips in the expanding step by forming dividing lines on the semiconductor wafer by a method such as stealth dicing or blade half-cut dicing. can be done.

According to one aspect of the present invention, scattering of the adhesive layer when the wafer processing tape is expanded can be suppressed.

1 is a plan view showing an example of a wafer processing tape according to an embodiment; FIG. FIG. 2 is a schematic cross-sectional view taken along line II-II shown in FIG. 1; FIG. 3(a) is a plan view showing an example of the wafer processing tape from which the release tape has been removed, and FIG. 3(b) is a bottom view showing an example of the wafer processing tape from which the release tape has been removed. be. FIG. 4 is a schematic cross-sectional view taken along line IV-IV shown in FIG. 3(a); FIG. 5(a) is a diagram showing the sticking process, FIG. 5(b) is an expanding process, and FIG. 5(c) is a diagram showing the heat shrinking process. It is a partially enlarged view of the laminated body shown to Fig.4 (a). It is a partially enlarged view of the laminated body shown to Fig.4 (a). FIGS. 8(a) and 8(b) are diagrams showing modifications of the cut. FIGS. 9(a) and 9(b) are diagrams showing modifications of the cut.

Preferred embodiments of the present invention will be described in detail below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant explanations are omitted. Further, in this specification, a numerical range indicated using "to" indicates a range including the numerical values before and after "to" as the minimum and maximum values, respectively.

[Schematic configuration of tape for wafer processing]
First, the schematic configuration of the wafer processing tape according to this embodiment will be described. The wafer processing tape according to this embodiment is a tape that is used by being attached to a semiconductor wafer (not shown) when manufacturing a semiconductor device. A wafer processing tape is usually formed in a long length and wound into a roll.

As shown in FIGS. 1 to 4, the wafer processing tape 1 includes an adhesive film 2 having a substrate layer 11 and an adhesive layer 12 provided on the substrate layer 11, and an adhesive layer 12 on the adhesive film 2. and an adhesive layer 3 to which the semiconductor wafer is attached. Note that the adhesive film 2 and the adhesive layer 3 are also referred to as a laminate 5 in the following description.

The wafer processing tape 1 also includes a long release tape (protective film) 4 attached to one surface of the laminate 5 on the side of the adhesive layer 3 . A part or the whole of one surface of the release tape 4 on the laminate 5 side is subjected to release treatment with a release agent. The release tape 4 is peeled off from the wafer processing tape 1 (the laminate 5 of the adhesive film 2 and the adhesive layer 3) when it is attached to the semiconductor wafer. Therefore, the wafer processing tape 1 may not necessarily include the release tape 4, and may be composed of only the laminate 5 of the adhesive film 2 and the adhesive layer 3.

The adhesive layer 3 is a die bond film used for die bonding of semiconductor chips. The adhesive layer 3 is formed in a circular shape with a diameter larger than that of the semiconductor wafer. The adhesive layer 3 has a central wafer bonding area 3a to be bonded to the semiconductor wafer, and an outer edge area 3b outside the wafer bonding area 3a. The outer edge area 3 b is an area between the wafer bonding planned area 3 a and the outer edge 3 c of the adhesive layer 3 .

The adhesive film 2 is a dicing tape that is bonded to a wafer ring arranged around a semiconductor wafer and used for dicing semiconductor chips. The adhesive film 2 is formed in a circular shape with a diameter larger than that of the adhesive layer 3 . The outer edge of the adhesive film 2 protrudes outside the adhesive layer 3 and is directly superposed on the surface of the release tape 4 . A pair of edge portions 6 formed of the same film as the adhesive film 2 is provided on each of both side portions of the release tape 4 . A pair of edge portions 6 are provided apart from the adhesive film 2 . The adhesive film 2 and the pair of edge portions 6 are formed by pre-cutting the film forming the adhesive film 2 .

[Method for manufacturing a semiconductor device]
Next, a method for manufacturing a semiconductor device will be described. The semiconductor device manufacturing method is performed using the wafer processing tape 1 described above.

In the method of manufacturing a semiconductor device, first, a dicing process is performed to form lines to be divided on a semiconductor wafer. In the dicing process, a support tape is attached to the surface of the semiconductor wafer, and lines to be cut are formed on the semiconductor wafer by stealth dicing, blade half-cut dicing, or the like. The planned dividing line is a line for dividing the semiconductor wafer into a plurality of semiconductor chips in the subsequent expanding process. Stealth dicing forms a modified region inside the semiconductor wafer by multiphoton absorption by irradiating the inside of the semiconductor wafer with focused light and a laser beam. It is a way to Blade half-cut dicing is a method of forming lines to be cut by half-cutting a semiconductor wafer with a dicing blade.

Next, a back grinding process is performed to grind the back surface of the semiconductor wafer.

Next, as shown in FIG. 5A, a bonding step of bonding the adhesive layer 3 of the wafer processing tape 1 to the semiconductor wafer 20 is performed. In the attaching step, the wafer ring 30 is placed around the semiconductor wafer 20 with the support tape 22 attached. Then, after peeling off the release tape 4 from the wafer processing tape 1, the outer edge portion of the adhesive film 2 of the wafer processing tape 1 is attached to the wafer ring 30, and the wafer of the adhesive layer 3 of the wafer processing tape 1 is removed. The area 3 a to be attached is attached to the semiconductor wafer 20 . After that, the support tape 22 is peeled off from the semiconductor wafer 20 .

Next, as shown in FIG. 5B, an expanding step is performed in which the semiconductor wafer 20 is separated into a plurality of semiconductor chips 21 by expanding the wafer processing tape 1 . In the expanding step, the wafer ring 30 and the adhesive film 2 are sandwiched and fixed between the fixing member 34 and the stage 31 . Then, under a low temperature condition of -15 to 5.degree. Then, the semiconductor wafer 20 is separated along the line to be cut, and the adhesive layer 3 is also separated for each semiconductor chip 21 .

Next, as shown in FIG. 5(c), the push-up member 32 is lowered to remove slack in the wafer processing tape 1, and a heat shrink process is performed to stably maintain the spacing between the semiconductor chips 21. Next, as shown in FIG. In the heat shrinking process, the wafer processing tape 1 is slightly expanded by the push-up member 32 to maintain the spacing between the semiconductor chips 21, and then the push-up member 32 is lowered. Then, a heater 33 is used to apply warm air of 90 to 120° C. to the portion between the semiconductor chip 21 region of the adhesive film 2 and the wafer ring 30 . As a result, the adhesive film 2 is heat shrunk and the wafer processing tape 1 is tensed.

Next, a pick-up step of picking up the semiconductor chip 21 from the adhesive film 2 is performed. In the pick-up process, the semiconductor chip 21 is picked up from the adhesive film 2 after reducing the adhesive force of the adhesive film 2 by, for example, irradiating the adhesive film 2 with ultraviolet rays. As a result, the semiconductor chip 21 to which the adhesive layer 3 is attached is obtained.

[Detailed Configuration of Wafer Processing Tape]
Next, the detailed configuration of the wafer processing tape 1 will be described.

As shown in FIG. 3, in the adhesive layer 3 of the wafer processing tape 1, cuts 15 are formed inside the outer peripheral edge 3c of the adhesive layer 3. As shown in FIG. The notches 15 are for dispersing the stress generated in the adhesive layer 3 by positively generating cracks when the wafer processing tape 1 is expanded. The incision 15 is preferably formed by a full cut penetrating the adhesive layer 3, but may be formed by a half cut that cuts halfway without penetrating the adhesive layer 3. good. As for the timing of forming the incision 15, it is preferable to perform it at the same time as the adhesive layer 3 is pre-cut into a circle with a mold or the like without increasing the number of steps. After the wafer processing tape 1 is attached to the semiconductor wafer 20, for example.

The formation position of the notch 15 is not particularly limited, but the notch 15 is preferably formed outside the wafer bonding planned area 3a. However, since the outer edge of the semiconductor wafer 20 is not used as the semiconductor chip 21, the notch 15 may be formed inside the wafer bonding planned area 3a.

By the way, the stress generated in the adhesive layer 3 when the wafer processing tape 1 is expanded increases with increasing distance from the center of the adhesive layer 3, that is, closer to the outer peripheral edge 3c. For this reason, it is preferable from the viewpoint of stress dispersion that the formation position of the cut 15 is closer to the outer peripheral edge 3 c of the adhesive layer 3 . From this point of view, as shown in FIG. It is preferably located outside the intermediate position 3d of .

Further, as shown in FIG. 6, the distance from the wafer bonding planned area 3a to the outer peripheral edge 3c of the adhesive layer 3 is defined as D, and the end of the cut 15 located closest to the outer peripheral edge 3c side of the adhesive layer 3 is the outside. The distance from the outer edge 3c of the adhesive layer 3 to the outer tip 15a of the notch 15 is d1. In this case, it is preferable to satisfy the following formula (1).
0.05≦(d1/D)≦0.5 (1)

By satisfying 0.05≦(d1/D), it is possible to prevent the outer tip 15a of the cut 15 from coming too close to the outer peripheral edge 3c of the adhesive layer 3 . As a result, it is possible to prevent cracks progressing from the cut 15 from reaching the outer peripheral edge 3c of the adhesive layer 3 and scattering fragments of the adhesive layer 3. As shown in FIG. In this case, it is more preferable to satisfy 0.08≦(d1/D), and it is particularly preferable to satisfy 0.1≦(d1/D).

On the other hand, by satisfying (d1/D)≦0.5, it is possible to prevent the outer tip 15a of the cut 15 from being too far from the outer peripheral edge 3c of the adhesive layer 3 . Thereby, the stress generated in the adhesive layer 3 when the wafer processing tape 1 is expanded can be appropriately dispersed. In this case, it is more preferable to satisfy (d1/D)≦0.4, and it is particularly preferable to satisfy (d1/D)≦0.35.

As described above, by satisfying 0.05≦(d1/D)≦0.5, it is possible to suppress the scattering of fragments of the adhesive layer caused by cracks progressing from the cut reaching the outer periphery of the adhesive layer. At the same time, the stress generated in the adhesive layer when the wafer processing tape is expanded can be appropriately dispersed. In this case, it is more preferable to satisfy 0.08≦(d1/D)≦0.4, and it is particularly preferable to satisfy 0.1≦(d1/D)≦0.35.

Further, as shown in FIG. 6, the distance from the wafer-prepared region 3a to the outer peripheral edge 3c of the adhesive layer 3 is defined as D, and the cut 15 closest to the wafer-prepared region 3a (outer peripheral edge 3c of the adhesive layer 3). The tip located on the opposite side of the cut 15 is defined as an inner tip 15b, and the distance from the wafer bonding planned region 3a to the inner tip 15b of the notch 15 is d2. In this case, it is preferable to satisfy the following formula (2).
0.1≦(d2/D)≦0.7 (2)

By satisfying 0.1≦(d2/D), it is possible to prevent the inner tip 15b of the notch 15 from being too close to the wafer bonding planned region 3a. As a result, it is possible to suppress cracking of the adhesive layer 3 on each separated semiconductor chip 21 . Moreover, even if the position of the semiconductor wafer 20 with respect to the wafer processing tape 1 is shifted due to a manufacturing error or the like, it is possible to prevent the notches 15 from being arranged on the semiconductor wafer 20 . In this case, it is more preferable to satisfy 0.15≦(d2/D), and it is particularly preferable to satisfy 0.2≦(d2/D).

On the other hand, by satisfying (d2/D)≦0.7, it is possible to prevent the inner tip 15b of the notch 15 from being too far from the wafer bonding planned region 3a. Thereby, the stress generated in the adhesive layer 3 when the wafer processing tape 1 is expanded can be appropriately dispersed. In this case, it is more preferable to satisfy (d2/D)≦0.6, and it is particularly preferable to satisfy (d2/D)≦0.5.

As described above, by satisfying the relationship of 0.1≦(d2/D)≦0.7, the wafer processing tape can be expanded while suppressing cracks in the adhesive layer on each separated semiconductor chip. It is possible to appropriately disperse the stress generated in the adhesive layer when the adhesive layer is applied. Further, even if the position of the semiconductor wafer with respect to the wafer processing tape is shifted due to a manufacturing error or the like, it is possible to prevent the notches from being arranged on the semiconductor wafer. In this case, it is more preferable to satisfy the relationship 0.15≦(d2/D)≦0.6, and it is particularly preferable to satisfy the relationship 0.2≦(d2/D)≦0.5.

The size of the incision 15 is not particularly limited, and can be appropriately selected according to the size of the semiconductor wafer 20 to which the wafer processing tape 1 is attached, the diameter of the adhesive layer 3, and the like. When the size of the semiconductor wafer 20 to which the wafer processing tape 1 is attached is 12 inches and the diameter of the adhesive layer 3 is 320 mm, the size of the incision 15 is, for example, a size that fits within a square of 2 to 7 mm. It can be said.

The shape of the incision 15 is not particularly limited, and may be X-shaped, I-shaped, +-shaped, −-shaped, U-shaped, V-shaped, W-shaped, or the like. From the viewpoint of isotropically dispersing the stress, an X shape, a positive shape, or the like is preferable.

Here, when the cut 15 has a shape that is inclined with respect to the radial direction R of the adhesive layer 3, the crack that progresses from the cut 15 is formed in the outer peripheral edge 3c of the adhesive layer 3 and the wafer bonding planned region 3a. can be prevented from reaching

Moreover, when the cut 15 is formed in an X shape, the crack can be propagated from the four tips of the cut 15 . Thereby, the stress generated in the adhesive layer when the wafer processing tape 1 is expanded can be appropriately dispersed.

Moreover, when the cut 15 is formed in an I-shape inclined in the circumferential direction C of the adhesive layer 3 , cracks can be propagated from the two tips of the cut 15 . Thereby, the stress generated in the adhesive layer 3 when the wafer processing tape 1 is expanded can be appropriately dispersed.

The number of cuts 15 is not particularly limited, but from the viewpoint of efficiently dispersing the stress generated in the adhesive layer 3, a plurality of cuts 15 is preferable. Further, the number of cuts 15 can be appropriately selected according to the size of the semiconductor wafer to which the wafer processing tape 1 is to be adhered, the diameter of the adhesive layer 3, and the like. When the size of the semiconductor wafer to which the wafer processing tape 1 is to be applied is 12 inches and the diameter of the adhesive layer 3 is 320 mm, the number of cuts 15 can be, for example, about 30-150. By setting the number of cuts 15 to a predetermined number (for example, 30) or more, the stress generated in the adhesive layer 3 can be efficiently dispersed, and the number of cuts 15 is set to a predetermined number (for example, 150) or less. As a result, it is possible to prevent the adjacent cuts 15 from being connected by cracks progressing from the cuts 15 and scattering fragments of the adhesive layer 3 .

When a plurality of cuts 15 are formed, the plurality of cuts 15 may not be arranged at equal intervals in the circumferential direction C of the adhesive layer 3, but the stress generated in the adhesive layer 3 can be efficiently removed. From the viewpoint of dispersion, it is preferable that they are arranged at equal intervals in the circumferential direction C of the adhesive layer 3 .

Also, as shown in FIG. 7, when a plurality of cuts 15 are formed, the interval P between adjacent cuts 15 is not particularly limited, but is preferably 2 mm or more and 40 mm or less.

Since the interval P between the adjacent cuts 15 is 2 mm or more, the adjacent cuts 15 can be prevented from coming too close to each other. As a result, it is possible to suppress scattering of fragments of the adhesive layer 3 caused by connecting adjacent cuts 15 due to cracks progressing from each cut 15 . In this case, the interval P between adjacent cuts 15 is more preferably 5 mm or more, particularly preferably 8 mm or more.

On the other hand, since the interval P between the adjacent cuts 15 is 40 mm or less, it is possible to prevent the adjacent cuts 15 from being too far apart. Thereby, the stress generated in the adhesive layer 3 when the wafer processing tape 1 is expanded can be appropriately dispersed. In this case, the interval P between adjacent cuts 15 is more preferably 30 mm or less, particularly preferably 20 mm or less.

As described above, by setting the interval P between the adjacent cuts 15 to be 2 mm or more and 40 mm or less, the adjacent cuts 15 are connected by cracks progressing from each cut 15, and the scattering of fragments of the adhesive layer 3 can be prevented. While suppressing the stress, the stress generated in the adhesive layer 3 when the wafer processing tape 1 is expanded can be appropriately dispersed. In this case, the interval P between adjacent cuts 15 is more preferably 5 mm or more and 30 mm or less, and particularly preferably 8 mm or more and 20 mm or less.

Further, when a plurality of cuts 15 are formed in the adhesive layer 3 in the circumferential direction C, each of the plurality of cuts 15 is formed in the adhesive layer as in the wafer processing tape 1A shown in FIG. 3 is preferably formed in an I shape inclined in the circumferential direction C. In this case, compared to the case where each of the plurality of cuts is formed in an X shape, it is possible to sufficiently secure the distance between the tips of adjacent cuts 15 . As a result, it is possible to prevent adjacent cuts 15 from being connected by cracks progressing from each cut 15, so that scattering of fragments of the adhesive layer 3 can be restrained.

Also, the plurality of cuts 15 may be formed on the same circumference as in the wafer processing tape 1B shown in FIG. 8(b). They may be formed on different concentric circles. When a plurality of cuts 15 are formed on the same circumference, a plurality of cuts 15 can be easily formed. On the other hand, when a plurality of cuts 15 are formed on two or more different concentric circles, the occurrence and propagation direction of cracks occurring in the adhesive layer 3 can be more finely controlled.

Also, the plurality of cuts 15 may be overlapped when viewed from the radial direction R as in the wafer processing tape 1C shown in FIG. 9(a). , they do not have to overlap when viewed from the radial direction R. When a plurality of cuts 15 overlap when viewed from the radial direction R, the number of cracks generated in the adhesive layer 3 when the wafer processing tape 1 is expanded can be increased. As a result, the stress generated in the adhesive layer 3 can be dispersed, and the generation and propagation direction of cracks generated in the adhesive layer 3 can be more finely controlled. On the other hand, when the plurality of cuts 15 do not overlap when viewed from the radial direction R, the cuts 15 can be easily formed, and adjacent cuts 15 are connected by cracks progressing from each cut 15. can be suppressed. As a result, scattering of fragments of the adhesive layer 3 can be suppressed.

Moreover, the plurality of cuts 15 may be formed in the same shape, or may be formed in two or more different shapes. When the plurality of cuts 15 have the same shape, it is possible to easily control the generation and progress of cracks in the adhesive layer 3 . On the other hand, when a plurality of cuts are formed in two or more different shapes, it is possible to finely control the generation and progress of cracks in the adhesive layer 3 .

As described above, in the wafer processing tape 1 according to the present embodiment, by expanding the wafer processing tape 1 with the semiconductor wafers 20 attached to the adhesive layer 3, the semiconductor wafers 20 are formed into a plurality of semiconductor chips. 21 can be separated. At this time, since the cut 15 is formed in the adhesive layer 3 , the crack progresses from the cut 15 . For this reason, the stress generated in the adhesive layer 3 can be dispersed, and the generation and propagation direction of cracks generated in the adhesive layer 3 can be controlled. Thereby, scattering of the adhesive layer 3 can be suppressed. Moreover, since the cut 15 is formed inside the outer peripheral edge 3c of the adhesive layer 3, the crack progressing from the cut 15 reaches the outer peripheral edge 3c of the adhesive layer 3, It is possible to suppress the scattering of fragments of

Further, if the cut 15 is formed outside the wafer bonding planned region 3a, when the wafer processing tape 1 is expanded with the semiconductor wafer 20 bonded to the adhesive layer 3, the wafer processing tape 1 is separated. Moreover, it is possible to suppress cracking of the adhesive layer 3 on each semiconductor chip 21 .

Further, when the outer tip 15a of the notch 15 is positioned outside the intermediate position 3d between the wafer bonding planned region 3a and the outer peripheral edge 3c of the adhesive layer 3, when the wafer processing tape 1 is expanded, The stress generated in the adhesive layer 3 can be appropriately dispersed. Thereby, scattering of the adhesive layer 3 can be further suppressed.

Further, when a plurality of cuts 15 are formed in the adhesive layer 3 in the circumferential direction C, the stress generated in the adhesive layer 3 when the wafer processing tape 1 is expanded can be dispersed appropriately. In this case, since each of the plurality of cuts 15 is formed in an I-shape inclined in the circumferential direction C of the adhesive layer 3, compared to the case where each of the plurality of cuts 15 is formed in an X-shape. Therefore, a sufficient distance between the tips of the adjacent cuts 15 can be ensured. As a result, it is possible to prevent adjacent cuts 15 from being connected by cracks progressing from each cut 15, so that scattering of fragments of the adhesive layer 3 can be restrained.

In the method for manufacturing a semiconductor device according to the present embodiment, after performing the attaching step of attaching the adhesive layer 3 of the wafer processing tape 1 to the semiconductor wafer 20, the expanding step of expanding the wafer processing tape 1 is performed. , separates the semiconductor wafer 20 into a plurality of semiconductor chips 21 . At this time, since the cut 15 is formed in the adhesive layer 3 , the crack progresses from the cut 15 . For this reason, the stress generated in the adhesive layer 3 can be dispersed, and the generation and propagation direction of cracks generated in the adhesive layer 3 can be controlled. Thereby, scattering of the adhesive layer 3 can be suppressed. Moreover, since the cut 15 is formed inside the outer peripheral edge 3c of the adhesive layer 3, cracks progressing from the cut 15 reach the outer peripheral edge 3c of the adhesive layer 3, causing the adhesive layer 3 to crack. It is possible to suppress scattering of fragments. For this reason, after that, by performing a pickup step of picking up the semiconductor chip 21 from the adhesive film 2, the scattered adhesive layer 3 is not attached, and the semiconductor chip 21 with the adhesive layer 3 attached on one side is removed. can be obtained.

The wafer processing tape and the semiconductor device manufacturing method of the present invention are not limited to the embodiments described above, and can be modified as appropriate without departing from the gist of the present invention.

For example, in a method of manufacturing a semiconductor device, if a semiconductor wafer can be divided into a plurality of semiconductor chips by expanding a wafer processing tape in an expanding step, a dividing line is formed on the semiconductor wafer by any method and at any timing. You may For example, a dicing process may be performed after the attaching process.

Examples of the present invention will be described below. However, the present invention is not limited to these examples.

(Example 1)
Wafer processing tape manufactured by Hitachi Chemical Co., Ltd. with an adhesive layer (die bond film) thickness of 20 μm, an adhesive film (dicing tape) thickness of 110 μm, and an adhesive layer diameter of 320 mm (model number FH-9011-20 ) was prepared, and the diameter of the semiconductor wafer to be attached to the wafer processing tape, that is, the diameter of the area to be attached to the wafer was set to 300 mm. Then, a minus-shaped cut of 4 mm was formed in the wafer processing tape using a cutting device. The outer tip of the incision closest to the outer peripheral edge of the adhesive layer was positioned 5 mm from the outer peripheral edge of the adhesive layer.

Next, the protective film was peeled off from the wafer processing tape, and the semiconductor wafer was adhered to the area to be adhered to the wafer. As this semiconductor wafer, a support tape was previously attached to the surface, stealth diced into 10 mm×10 mm, and the back surface was polished to a thickness of 30 μm. Next, the support tape is peeled off from the semiconductor wafer, and using a die separator (model number DDS-2300) manufactured by Disco Co., Ltd., the wafer processing tape is expanded and heat-shrinked under the following conditions, and the wafer processing of Example 1 is performed. I got a tape for

[Expand condition]
Cooling temperature: -15°C, cooling time: 120 seconds, expansion amount: 12 mm, expansion speed: 200 mm/s, retention time after expansion: 10 seconds [Heat shrink conditions]
Heater temperature: 220°C, heater rotation speed: 5°/s, expansion amount: 7 mm
(Example 2)
The conditions were the same as in Example 1, except that the shape of the incision was a 4 mm square x shape, and the outer tip of the incision closest to the outer peripheral edge of the adhesive layer was positioned 3 mm from the outer peripheral edge of the adhesive layer. As a result, a wafer processing tape of Example 2 was obtained.

(Example 3)
The conditions were the same as in Example 1, except that the shape of the incision was a 4 mm square x shape, and the outer tip of the incision closest to the outer peripheral edge of the adhesive layer was positioned 2 mm from the outer peripheral edge of the adhesive layer. As a result, a wafer processing tape of Example 3 was obtained.

(Example 4)
A wafer processing tape of Example 3 was obtained under the same conditions as in Example 3, except that the number of cuts was 72.

(Example 5)
A wafer processing tape of Example 5 was obtained under the same conditions as in Example 4, except that the outer tip of the incision closest to the outer peripheral edge of the adhesive layer was positioned 1 mm from the outer peripheral edge of the adhesive layer. rice field.

(Comparative example 1)
A wafer processing tape of Comparative Example 1 was obtained under the same conditions as in Example 1, except that no slits were formed in the adhesive layer.

(Comparative example 2)
Wafer processing of Comparative Example 2 was performed under the same conditions as in Example 1, except that the number of cuts was 72, and the outer tip of the cuts closest to the outer peripheral edge of the adhesive layer was the outer edge of the adhesive layer. I got a tape for

(Evaluation of scattering property of adhesive layer)
A semiconductor wafer was attached to each of the wafer processing tapes of Examples 1 to 5 and Comparative Examples 1 and 2, and after each wafer processing tape was expanded, the outer peripheral portion of the adhesive layer of each wafer processing tape was visually observed. Observed. A: No fragments of the adhesive layer scattered; B: Slightly scattered fragments of the adhesive layer; C: Scattered fragments of the adhesive layer; D is the object. Table 1 shows the evaluation results.

(Separability evaluation of adhesive layer)
After the scattering property evaluation described above, the semiconductor wafer (a plurality of divided semiconductor chips) was observed with a microscope from above to evaluate whether or not the adhesive layer was divided. Microscopic observation was performed on the entire surface of the semiconductor wafer. A case where the adhesive layer was separated was rated as A, and a case where there was a portion where the adhesive layer was not separated was rated as B. Table 1 shows the evaluation results.

(Evaluation of pick-up property)
After the tearability evaluation described above, the adhesive film was irradiated with ultraviolet light at an illumination intensity of 100 mW/cm ² and an irradiation dose of 200 mJ/cm ² to cure the adhesive layer of the adhesive film and reduce the adhesive force. After that, 100 divided semiconductor chips with an adhesive layer were subjected to a pickup height of 200 μm, a pickup speed of 1 mm / s, and a multi-pin push-up (number of pins: 9) using a DB800-HSD manufactured by Hitachi High-Technologies Corporation. I picked up on the condition. A was assigned to those that could be picked up without any problem, and B was assigned to those having a pick-up failure. Table 1 shows the evaluation results.

As shown in Table 1, Examples 1 to 5 had better scattering properties than Comparative Examples 1 and 2. Specifically, in Examples 1 and 2, scattering of the adhesive layer occurred slightly, but in Examples 3 to 5, scattering of the adhesive layer did not occur, and the results were good. On the other hand, in Comparative Example 1, considerable scattering of the adhesive layer occurred. In Comparative Example 2, fragments of the triangular adhesive layer with a small area were scattered due to the cut formed in the outer peripheral edge of the adhesive layer. The splitting and picking up properties were good regardless of the presence or absence of cuts.

Reference Signs List 1, 1A, 1B, 1C, 1D... Wafer processing tape, 2... Adhesive film, 3... Adhesive layer, 3a... Area to be adhered to wafer, 3b... Outer edge area, 3c... Outer edge, 3d... Intermediate position, 4... Release tape 5 Laminate 6 Edge 11 Base layer 12 Adhesive layer 15 Incision 15a Outer tip 15b Inner tip 20 Semiconductor wafer 21 Semiconductor chip 22... Support tape 30... Wafer ring 31... Stage 32... Member 33... Heater 34... Fixing member C... Circumferential direction R... Radial direction P... Interval between adjacent cuts.

Claims (20)

A wafer processing tape for separating a semiconductor wafer into a plurality of semiconductor chips by being attached to a semiconductor wafer and expanding the tape,
an adhesive film having a substrate layer and an adhesive layer provided on the substrate layer;
A circular adhesive layer provided on the adhesive layer of the adhesive film and to which the semiconductor wafer is attached,
A linear cut is formed in the adhesive layer inside the outer peripheral edge of the adhesive layer,
Wafer processing tape. The incision is formed outside a wafer attachment area of the adhesive layer to which the semiconductor wafer is attached.
The wafer processing tape according to claim 1. The outer tip of the notch, which is located closest to the outer peripheral edge of the adhesive layer, is located at an intermediate position between the outer peripheral edge of the adhesive layer and the outer peripheral edge of the adhesive layer, to which the semiconductor wafer is to be attached. located outside the
The wafer processing tape according to claim 1 or 2. D is the distance from the wafer bonding area of the adhesive layer to which the semiconductor wafer is to be bonded to the outer peripheral edge of the adhesive layer, and the cut is closest to the outer peripheral edge of the adhesive layer from the outer peripheral edge of the adhesive layer. When the distance to the outer tip located at is d1,
0.05≦(d1/D)≦0.5
satisfy the relationship of
The wafer processing tape according to any one of claims 1 to 3. D is the distance from the wafer bonding area of the wafer processing tape to which the semiconductor wafer is to be bonded to the outer peripheral edge of the adhesive layer; When the distance to the inner tip located on the side is d2,
0.1≦(d2/D)≦0.7
satisfy the relationship of
A wafer processing tape according to any one of claims 1 to 4. The cut is inclined with respect to the radial direction of the adhesive layer,
The wafer processing tape according to any one of claims 1 to 5. The notch is formed in an X shape,
A wafer processing tape according to any one of claims 1 to 6. The cut is formed in an I shape inclined in the circumferential direction of the adhesive layer,
A wafer processing tape according to any one of claims 1 to 6. A plurality of the cuts are formed in the circumferential direction of the adhesive layer,
A wafer processing tape according to any one of claims 1 to 8. The plurality of cuts are formed at equal intervals in the circumferential direction of the adhesive layer,
The wafer processing tape according to claim 9. The plurality of cuts are formed on the same circumference,
The wafer processing tape according to claim 9 or 10. The plurality of cuts are formed on two or more different concentric circles,
The wafer processing tape according to claim 9 or 10. The plurality of cuts overlap when viewed from the radial direction of the adhesive layer,
The wafer processing tape according to any one of claims 9-12. The plurality of cuts do not overlap when viewed from the radial direction of the adhesive layer,
The wafer processing tape according to any one of claims 9-12. The plurality of cuts are formed in the same shape,
The wafer processing tape according to any one of claims 9-14. The plurality of cuts are formed in two or more different shapes,
The wafer processing tape according to any one of claims 9-14. The interval between the adjacent cuts is 2 mm or more and 40 mm or less,
The wafer processing tape according to any one of claims 9-16. The cut does not reach the surface of the adhesive film opposite to the adhesive layer,
The wafer processing tape according to any one of claims 1-17. The notch is not formed on the surface of the adhesive film opposite to the adhesive layer,
The wafer processing tape according to any one of claims 1-18. A method for manufacturing a semiconductor device using the wafer processing tape according to any one of claims 1 to 19,
an attaching step of attaching the adhesive layer of the wafer processing tape to the semiconductor wafer;
an expanding step of separating the semiconductor wafer into a plurality of semiconductor chips by expanding the wafer processing tape;
A pickup step of picking up the semiconductor chip from the adhesive film,
A method of manufacturing a semiconductor device.

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