JP7208854B2 - Method for manufacturing wiring board with cavity - Google Patents

Description

The present disclosure relates to a method of manufacturing a wiring board with cavities having cavities for housing electronic components.

Patent Document 1 describes a method for manufacturing a wiring board with a cavity, in which an insulating layer is laminated on a conductor layer, and the insulating layer is irradiated with a laser to expose the conductor layer as a bottom surface to form a cavity. It is

JP 2006-19441 A (paragraph [0049], FIG. 6)

Compared to the above-described conventional manufacturing method, it is required to improve productivity while reducing unevenness of the inner peripheral surface of the cavity.

A wiring board with a cavity according to claim 1, which has been made to solve the above-mentioned problems, comprises: laminating an insulating layer on a conductor layer forming a conductor circuit layer and a plane layer; and forming a cavity exposing a layer as a bottom surface, wherein the cavity is formed by irradiating a laser onto the insulating layer while shifting the laser by a predetermined pitch. and making the processing diameter of the laser larger when forming an inner portion of the cavity surrounded by the outer peripheral portion than when forming the outer peripheral portion of the cavity.

Sectional view of a wiring board with a built-in electronic component according to an embodiment of the present disclosure Cross-sectional view around electronic components in wiring board with built-in electronic components Cross-sectional view of wiring board with cavity Cross-sectional view around cavity of wiring board with cavity (A) Flat end view of the periphery of the cavity of the wiring board with the cavity, (B) Enlarged flat end view of the opening edge of the cavity of the wiring board with the cavity Cross-sectional view showing manufacturing process of wiring board with cavity Cross-sectional view showing manufacturing process of wiring board with cavity Cross-sectional view showing manufacturing process of wiring board with cavity Cross-sectional view showing manufacturing process of wiring board with cavity Cross-sectional view showing manufacturing process of wiring board with cavity Flat end view showing manufacturing process of wiring board with cavity Flat end view showing manufacturing process of wiring board with cavity Cross-sectional view showing manufacturing process of wiring board with built-in electronic components Cross-sectional view showing manufacturing process of wiring board with built-in electronic components Cross-sectional view showing manufacturing process of wiring board with built-in electronic components Cross-sectional view showing manufacturing process of wiring board with built-in electronic components Cross-sectional view showing manufacturing process of wiring board with built-in electronic components Cross-sectional view showing manufacturing process of wiring board with built-in electronic components Cross-sectional view showing manufacturing process of wiring board with built-in electronic components

As shown in FIG. 1, a wiring board 100 with a built-in electronic component according to an embodiment of the present disclosure is a wiring board 10 with a cavity (see FIG. 3), an outer buildup insulating layer 21 and an outer buildup conductor layer 22 are laminated on both front and back surfaces of the structure, and the outer buildup conductor layer 22 is covered with a solder resist layer 29 . Solder-resist layer 29 constitutes surface F (front surface) (100F) and surface B (back surface) (100B) of wiring board 100 with a built-in electronic component.

As shown in FIG. 3, in wiring board 10 with a cavity, build-up insulating layers 15 and build-up conductor layers 16 are alternately arranged on F surface 11F, which is the front surface of core substrate 11, and B surface 11B, which is the back surface. It has a multi-layered structure.

Core conductor layers 12 are formed on both the front and back surfaces of the core substrate 11 . The buildup insulating layer 15 is made of an insulating material, and the buildup conductor layer 16 is made of metal (for example, copper).

The core conductor layer 12 on the front side and the core conductor layer 12 on the back side are connected by through-hole conductors 13 passing through the core substrate 11 . The through-hole conductor 13 is formed by plating the wall surface of the through-hole 13A penetrating the core substrate 11 with, for example, copper.

The innermost buildup conductor layer 16 closest to the core substrate 11 and the core conductor layer 12 are connected by via conductors 17 penetrating the innermost buildup insulating layer 15 . Also, adjacent buildup conductor layers 16, 16 in the stacking direction are connected by via conductors 18 penetrating the buildup insulating layer 15 located between the buildup conductor layers 16, 16. As shown in FIG.

A second buildup conductor layer 16B positioned second from the outside among the buildup conductor layers 16 laminated on the F surface 11F side of the core substrate 11 is formed with a conductor circuit layer 31B and a plane layer 31A. there is The plane layer 31A is a ground layer that is solidly connected to the ground. Plain layer 31A is arranged near the center of wiring board 10 with a cavity, and conductor circuit layers 31B are arranged so as to sandwich plane layer 31A from both sides.

A first buildup conductor layer 16A arranged on the outermost side of the buildup conductor layers 16 laminated on the F surface 11F side of the core substrate 11 has conductors connected to the conductor circuit layer 31B via the via conductors 18. A circuit layer 35 is formed. A protective layer 34 is laminated on the first buildup conductor layer 16A. The protective layer 34 is made of the same material as the buildup insulating layer 15 . Protective layer 34 constitutes surface F 10</b>F, which is the front surface of wiring board 10 with a cavity, and surface B 10</b>B, which is the rear surface of wiring board 10 with a cavity. Protective layer 34 may not be formed on the back surface of wiring board 10 with a cavity.

As shown in FIG. 3, wiring board 10 with cavity is formed with cavity 30 having opening 30A on F surface 10F. The cavity 30 penetrates the outermost first buildup insulating layer 15A and the protective layer 34, and exposes the plane layer 31A as a bottom surface.

As shown in FIG. 4, the area of the opening 30A of the cavity 30 is smaller than the area of the plane layer 31A, and the outer peripheral portion of the plane layer 31A protrudes outside the cavity 30. As shown in FIG. In other words, the plane layer 31A constitutes the entire bottom surface of the cavity 30. As shown in FIG. A roughened layer 36 is formed on the surface of the portion of the plain layer 31A that is exposed as the bottom surface of the cavity 30 .

As shown in FIG. 1, cavity 30 accommodates electronic component 80 as described above, and electronic component 80 is electrically connected to a semiconductor element mounted on surface F (100F) of wiring board 100 with a built-in electronic component. be done. As shown in FIG. 2, an adhesive layer 33 is formed on the plane layer 31A exposed as the bottom surface of the cavity 30, and the electronic component 80 is mounted on the adhesive layer 33. As shown in FIG. Due to the roughened layer 36 on the surface of the plane layer 31A exposed as the bottom surface of the cavity 30, peeling of the adhesive layer 33 from the plane layer 31A is further suppressed. In addition, the resin forming the outer buildup insulating layer 21 is buried between the outer edge of the cavity 30 and the electronic component 80 .

As shown in FIG. 2 , on F-plane solder resist layer 29</b>F forming F-plane 100</b>F of wiring board 100 with a built-in electronic component, F-plane outer buildup located on F-plane 100</b>F side of outer buildup conductor layer 22 is formed. A plurality of openings 27 are formed to expose a portion of the conductor layer 22F as the conductor pads 23 . Specifically, as the conductor pads 23, a first conductor pad 23A arranged outside the cavity 30 when viewed in the thickness direction and a second conductor pad 23B overlapping the electronic component 80 are formed. As the openings 27, a plurality of first openings 27A exposing the first conductor pads 23A and a plurality of second openings 27B exposing the second conductor pads 23B are formed.

The conductor pads 23 are connected to the conductor circuit layer 35 of the first buildup conductor layer 16A or the electronic component 80 via via conductors 25 . Specifically, first conductor pads 23A are connected to conductor circuit layer 35 through first via conductors 25A, and second conductor pads 23B are connected to electrode terminals 80A of electronic component 80 through second via conductors 25B. (see FIG. 2).

The first via conductor 25A is formed by filling the first via forming hole 45A passing through the outer buildup insulating layer 21 and the protective layer 34 with plating, and the second via conductor 25B passes through the outer buildup insulating layer 21. The second via forming holes 45B are filled with plating.

As shown in FIG. 2, an F-surface plated layer 41 is formed on the first conductor pads 23A and the second conductor pads 23B. The F-side plated layer 41 on the first conductor pad 23A fills the inside of the first opening 27A and protrudes outside the F-side solder resist layer 29F in a bump shape. Similarly, the F-side plated layer 41 on the second conductor pad 23B also fills the inside of the second opening 27B and protrudes outside the F-side solder resist layer 29F.

As shown in FIG. 1, in wiring board 100 with a built-in electronic component, B-side solder-resist layer 29B on B-side 100B side includes part of B-side outer buildup conductor layer 22B on B-side 100B side as a third conductor pad. A plurality of third openings 28 exposed as 24 are formed.

Third conductor pad 24 is connected to first buildup conductor layer 16A on surface B 10B of wiring board 10 with cavity via third via conductor 26 . The third via conductor 26 is formed by filling a third via formation hole 46 passing through the outer buildup insulating layer 21 and the protective layer 34 with plating. As shown in FIG. 1 , a B-side plated layer 42 is formed on the third conductor pad 24 .

As shown in FIG. 5A, in wiring board 10 with a cavity of the present embodiment, cavity 30 has a substantially rectangular shape when viewed from the thickness direction. In the F surface 10F of the wiring board 10 with a cavity, the outer edge of the cavity 30 has a shape in which arc portions 50 protruding outward are arranged along the entire circumference at a predetermined pitch P1 (FIG. 5). (B)). In this embodiment, the pitch P1 is 20 to 80%, more preferably 25 to 75%, of the diameter D1 of the fictitious circle C1 including the arc portion 50. FIG. Also, the diameter D1 of the circle C1 is 120 μm or less. The pitch P1 here is the distance between the centers of adjacent circular arc portions 50 (circles C1).

As shown in FIG. 5(B), in the present embodiment, a curve L (for example, indicated by a thick line in FIG. 5(B)) along the outer edge of the cavity 30 (that is, the arc portion 50) is traced by a pitch P1. 1.01 times or more and 1.13 times or less of the pitch P1.

In addition, in this embodiment, the inner peripheral surface of the cavity 30 is inclined so that the cross section of the cavity 30 becomes smaller toward the bottom surface side (the plane layer 31A side). The inner peripheral surface of the cavity 30 may rise so as to be substantially perpendicular to the plane layer 30A.

The structures of wiring board 10 with a cavity and wiring board 100 with a built-in electronic component have been described above. Next, a method of manufacturing wiring board 10 with a cavity and wiring board 100 with a built-in electronic component will be described. First, a method for manufacturing wiring board 10 with a cavity will be described.

Wiring board 10 with a cavity is manufactured as follows.
(1) As shown in FIG. 6A, a through hole 13A is formed in the core substrate 11 by, for example, drilling. The core substrate 11 is composed of an insulating base material 11K made of epoxy resin or BT (bismaleimide triazine) resin and reinforcing material such as glass cloth. A copper foil (not shown) is laminated.

(2) The core conductor layer 12 is formed on the F surface 11F and the B surface 11B of the core substrate 11 by electroless plating treatment, plating resist treatment, and electrolytic plating treatment, and the through hole conductor is formed on the inner surface of the through hole 13A. 13 are formed (see FIG. 6B).

(3) As shown in FIG. 7A, a buildup insulating layer 15 is laminated on the core conductor layer 12 and a buildup conductor layer 16 is laminated on the buildup insulating layer 15 . Specifically, a resin film containing no core material is laminated as the build-up insulating layer 15 on the core conductor layer 12 from the F surface 11F side and the B surface 11B side of the core substrate 11 . Then, the resin film (buildup insulating layer 15 ) is irradiated with a laser (for example, a CO 2 laser) to form a via forming hole penetrating through the buildup insulating layer 15 . Then, electroless plating, plating resist treatment, and electrolytic plating are performed to fill the via forming holes with electrolytic plating to form via conductors 17 , and a predetermined pattern of buildup is formed on buildup insulating layer 15 . A conductor layer 16 is formed. A prepreg (B-stage resin sheet obtained by impregnating a core material with resin) may be used as the build-up insulating layer 15 instead of the resin film. In this case, the prepreg and the copper foil are laminated on the core conductor layer 12 from the F surface 11F side and the B surface 11B side of the core substrate 11, and then hot pressed. Then, the copper foil on the buildup insulating layer 15 (prepreg) is irradiated with a laser (for example, a CO2 laser) to form a via formation hole penetrating the copper foil and the buildup insulating layer 15 . After that, electroless plating, plating resist treatment, and electrolytic plating are performed in the same manner as in the case of using a resin film to form via conductors 17 and buildup conductor layers 16 .

(4) Buildup insulating layers 15 and buildup conductor layers 16 are alternately laminated on the F surface 11F side and the B surface 11B side of the core substrate 11 in the same manner as in the process of FIG. 7A (FIG. 7A). (B), in which only the F surface 11F side is shown.The same shall apply to FIGS. At that time, via conductors 18 are formed to penetrate buildup insulating layers 15 , and buildup insulating layers 16 , 16 adjacent in the stacking direction are connected by via conductors 18 .

(5) As shown in FIG. 8A, a buildup insulating layer 15 is laminated, and a buildup conductor layer 16 is laminated on the buildup insulation layer 15 to form a second buildup conductor layer 16B. is formed. At that time, a conductor circuit layer 31B connected to the inner buildup conductor layer 16 via the via conductors 18 and a solid plain layer 31A are formed on the second buildup conductor layer 16B.

(6) As shown in FIG. 8B, the buildup insulating layer 15 and the buildup conductor layer 16 are laminated on the second buildup conductor layer 16B to form the first buildup insulating layer 15A and the first buildup conductor layer 16B. A buildup conductor layer 16A is formed. At that time, only the first buildup insulating layer 15A is laminated on the plane layer 31A. A conductor circuit layer 35 is formed on the first buildup conductor layer 16A to be connected to the conductor circuit layer 31B through via conductors 18 penetrating the first buildup insulating layer 15A.

(7) As shown in FIG. 9A, a protective layer 34 made of the same material as the buildup insulating layer 15 is laminated on the first buildup conductor layer 16A. At this time, the first buildup insulating layer 15A and the protective layer 34 are laminated on the plane layer 31A.

(8) As shown in FIGS. 9B and 11, the protective layer 34 is irradiated with a laser (for example, a CO2 laser). As a result, a recess 55 is formed that penetrates the protective layer 34 and the first buildup insulating layer 15A and exposes the plane layer 31A as a bottom surface. In this embodiment, the concave portion 55 is formed in a substantially rectangular shape when viewed from the thickness direction of the core substrate 11 . In forming the concave portion 55, the laser irradiation locations are shifted by a predetermined pitch P0 in two directions perpendicular to each other, and the laser is irradiated at each irradiation location for a predetermined time (that is, intermittently irradiated). . As a result, when viewed from the thickness direction, on the surface of the protective layer 34, the outer edge of the concave portion 55 has a shape in which outwardly bulging arc portions 56 are arranged along the entire circumference at a pitch P0 (see FIG. 11). ). In this embodiment, the pitch P0 is 20 to 80% of the processing diameter D0 (spot diameter), which is the diameter of the laser projected onto the insulating layer (protective layer 34) irradiated with the laser. set. In addition, in FIGS. 11 and 12, a circle C0, which is the outer diameter of the laser-machined hole having the machining diameter D0, is represented by a chain double-dashed line. The pitch P0 is the distance between the centers of adjacent circles C0.

(9) As shown in FIGS. 10 and 12, a laser (for example, CO2 laser) is applied to the opening edge of the recess 55 over the entire circumference. As a result, the protective layer 34 on the plane layer 31A and the first buildup insulating layer 15A are removed in a substantially rectangular frame shape to form an outer peripheral portion R1 exposing the plane layer 31A. The cavity 30 is formed by the above. The area of the range irradiated with the laser, that is, the opening area of the cavity 30 is smaller than the area of the plane layer 31A, and the entire bottom surface of the cavity 30 is formed only by the plane layer 31A.

In forming the outer peripheral portion R1, the laser is irradiated onto the insulating layer for a predetermined time each time the edge of the opening of the recess 55 is shifted by a predetermined pitch P1. At this time, in the present embodiment, the pitch P1 is 20 to 80% ( more preferably 25 to 75%). Further, when forming the outer peripheral portion R1 of the cavity 30, the length of the curve L (for example, the portion shown in bold in FIG. 12) obtained by tracing the outer edge of the cavity 30 by the pitch P1 is equal to the pitch P1. The outer edge of the cavity 30 is formed to be 1.01 times or more and 1.13 times or less. Further, in the present embodiment, the processing diameter D1 is smaller than the laser processing diameter D0 when forming the recess 55 (that is, the inner portion surrounded by the outer peripheral portion R1 of the cavity 30) (for example, , the machining diameter D1 is 0.2 to 0.8 times the machining diameter D0). Furthermore, in the present embodiment, the pitch P1 when forming the outer peripheral portion R1 is made smaller than the pitch P0 when forming the recesses 55 . In this embodiment, two types of masks 61 (for example, made of copper) having different diameters of the through holes 61A through which the laser passes are used when forming the recess 55 and when forming the outer peripheral portion R1. ) is used to vary the laser processing diameter. The formation of the concave portion 55 and the formation of the outer peripheral portion R1 are performed using the common laser irradiation section 62 under the same laser irradiation conditions (performed by common laser irradiation). In addition, in FIG. 12, a circle C1 indicating the outer shape of the laser-machined hole having the machining diameter D1 is represented by a chain double-dashed line. The pitch P1 is the distance between the centers of adjacent circles C1.

(10) The plain layer 31A exposed as the bottom surface of the cavity 30 is desmeared, and a roughened layer 36 is formed on the surface of the plain layer 31A by roughening. Note that the conductor circuit layer 31B included in the second buildup conductor layer 16B is protected by the protective layer 34 during the desmear treatment. Thus, wiring board 10 with a cavity shown in FIG. 3 is completed.

The above is the description of the method for manufacturing wiring board 10 with a cavity. Next, a method for manufacturing electronic component built-in wiring board 100 using wiring board 10 with a cavity will be described.

Wiring board 100 with a built-in electronic component is manufactured as follows.
(1) As shown in FIG. 13A, an adhesive layer 33 is laminated on the plain layer 31A exposed as the bottom surface of the cavity 30, and an electronic component 80 is placed on the adhesive layer 33, followed by heat curing. , CZ processing is performed.

(2) Outer buildup insulating layer 21 made of the same material as buildup insulating layer 15 is laminated on F surface 10F and B surface 10B of wiring board 10 with a cavity (see FIG. 13B). , only the F surface 10F side is shown.The same applies to FIG. 15.). At this time, the resin forming outer buildup insulating layer 21 is filled between the opening end (outer edge) of cavity 30 and electronic component 80 .

(3) A laser (for example, a CO2 laser) is irradiated from the F surface 10F side of wiring board 10 with a cavity to form first via formation holes 45A in outer buildup insulating layer 21 and protective layer 34 ( 14(A)), a laser (for example, a CO2 laser) is irradiated from the B surface 10B side of the wiring board 10 with a cavity to form the third via forming hole 46 (see FIG. 14(B)). Next, a laser (for example, an ultraviolet laser) is irradiated from the F surface 10F side of wiring board 10 with a cavity to form second via formation holes 45B in outer buildup insulating layer 21 (see FIG. 15 ( A)). Then, the first buildup conductor layer 16A and the electronic component 80 exposed by the via forming holes 45A, 45B, 46 are desmeared.

(4) Electroless plating treatment, plating resist treatment, and electrolytic plating treatment are performed, and on the F surface 10F side of wiring board 10 with a cavity, first via formation holes 45A and second via formation holes 45B are formed into first via formation holes 45A and 45B. The conductor 25A and the second via conductor 25B are formed (see FIG. 15B), and the third via conductor 26 is formed in the third via forming hole 46 on the side B 10B of the wiring board 10 with a cavity. be. Further, on the outer buildup insulating layer 21, an outer buildup conductor layer 22 (an F-plane outer buildup conductor layer 22F and a B-plane outer buildup layer 22B) is formed.

(5) As shown in FIG. 16, a solder resist layer 29 is laminated on the outer buildup conductor layer 22 from both the F surface 10F side and the B surface 10B side of the wiring board 10 with a cavity, and lithography processing is performed. A first opening (27A) is formed in the F-plane solder resist layer (29F) on the F-plane (10F) side of the wiring board (10) with a cavity to expose a part of the F-plane outer buildup conductor layer (22F) as a first conductor pad (23A), A third opening 28 that exposes a part of the B-surface outer buildup conductor layer 22B as the third conductor pad 24 is formed in the B-surface solder resist layer 29B on the B-surface 10B side.

(6) As shown in FIG. 17, by irradiating a laser (for example, an ultraviolet laser) from the F-plane 10F side of wiring board 10 with a cavity, a part of F-plane outer buildup conductor layer 22F is formed into a second layer. A second opening 27B is formed to expose as a two-conductor pad 23B. Then, desmear treatment is applied to the second conductor pads 23B.

(7) As shown in FIG. 18, the F-side solder resist layer 29F is covered with a resin protective film 43. Then, as shown in FIG. Then, electroless plating is performed on the B-side 10B side of wiring board 10 with a cavity, and B-side plated layer 42 is formed on third conductor pad 24 . The second conductor pads 23B and the first conductor pads 23A are protected by the resin protective film 43 during the electroless plating process.

(8) As shown in FIG. 19, the resin protective film 43 covering the F-side solder-resist layer 29F is removed, and the B-side solder-resist layer 29B is covered with the resin protective film 43 . 18, the F surface 10F side of the wiring board 10 with a cavity is electrolessly plated to form an F surface plated layer 41 on the first conductor pads 23A and the second conductor pads 23B. be done. At that time, the B-side plated layer 42 is protected by the resin protective film 43 .

(9) Resin protective film 43 covering B-side solder resist layer 29B is removed to complete wiring board 100 with a built-in electronic component shown in FIG.

Next, the effect of the wiring board 10 of the wiring board 10 with a cavity of this embodiment will be described.

In wiring board 10 with a cavity of the present embodiment, when viewed from the thickness direction, the outer edge of cavity 30 has a shape in which arc portions 50 protruding outward are arranged at a predetermined pitch P1. The length of the curve L obtained by tracing the outer edge of the cavity 30 by the pitch P1 is 1.01 times or more and 1.13 times or less of the pitch P1. Thereby, the unevenness of the inner peripheral surface of the cavity 30 can be reduced. The pitch P1 is 20 to 80% of the diameter of the imaginary circle C1 including the arc portion 50 (more preferably 25 to 75% of the diameter of the circle C1). Thereby, the unevenness of the inner peripheral surface of the cavity 30 can be further reduced. Moreover, since the diameter of the circle C1 including the arc portion 50 is 120 μm or less, the irregularities of the inner peripheral surface of the cavity 30 can be further reduced.

In the method for manufacturing wiring board 10 with a cavity according to the present embodiment, the processing diameter, which is the diameter of the laser beam projected onto protective layer 34, is set to be larger than the outer peripheral portion R1 of cavity 30. When forming a portion inside R1 (that is, when forming the recess 55), it is made larger. Therefore, it is possible to speed up the formation of the inner portion of the outer peripheral portion R1 of the cavity 30 while reducing the unevenness of the inner peripheral surface of the cavity, thereby improving the productivity. Moreover, in the present embodiment, the pitch P1 for forming the outer peripheral portion R1 of the cavity 30 is made smaller than the pitch P0 for forming the inner portion of the outer peripheral portion R1, so that the unevenness of the inner peripheral surface of the cavity 30 can be reduced. It is possible to make it smaller. In addition, when forming the outer peripheral portion R1 of the cavity 30, by setting the pitch P1 to 20 to 80% of the processing diameter D1, it is possible to improve productivity while reducing the unevenness of the inner peripheral surface of the cavity. becomes.

In the present embodiment, the formation of the outer peripheral portion R1 of the cavity 30 and the formation of the inner portion of the outer peripheral portion R1 are performed by the common laser irradiation section 62, so compared to the case where these formations are performed by separate laser irradiation sections. Therefore, formation of the cavity 30 is facilitated. Further, in the present embodiment, since the laser processing diameter is changed by the mask 61 when forming the cavity 30, the laser processing diameter can be easily changed.

[Other embodiments]
(1) In the above embodiment, the inner portion (recess 55) of the outer peripheral portion R1 was formed before forming the outer peripheral portion R1 of the cavity 30. However, after forming the outer peripheral portion R1 of the cavity 30, the outer peripheral portion It may form the inner portion of R1.

(2) In the above-described embodiment, the laser processing diameter is changed between the outer peripheral portion R1 of the cavity 30 and the inner portion of the outer peripheral portion R1 by changing the mask 61. This may be done by changing the output of the laser, or by changing to a different laser irradiation unit 62 .

(3) In forming the cavity 30, the pitch P0 when forming the recesses 55 may be the same as the pitch P1 when forming the outer peripheral portion R1, or may be smaller than the pitch P1.

(4) In the above embodiment, the pitch P1 for forming the outer peripheral portion R1 of the cavity 30 is 20 to 80% of the laser processing diameter D1, but may be outside this range. Further, in the above embodiment, the pitch P0 when forming the inner portion of the outer peripheral portion R1 of the cavity 30 was 20 to 80% of the laser processing diameter D0, but it may be outside this range. .

(5) In the above embodiment, the outer peripheral portion R1 of the cavity 30 and the inner portion of the outer peripheral portion R1 may have the same laser processing diameter. Also, the laser processing diameter D0 of the inner portion of the outer peripheral portion R1 of the cavity 30 may be smaller than the laser processing diameter D1 of the outer peripheral portion R1.

(6) In the above embodiment, the length of the curve L obtained by tracing the outer edge of the cavity 30 by the pitch P1 is 1.01 times or more and 1.13 times or less of the pitch P1. may be

REFERENCE SIGNS LIST 10 wiring board with cavity 15 build-up insulating layer 16 build-up conductor layer 30 cavity 31A plane layer 32B conductor circuit layer 34 protective layer 50 arc portion 55 concave portion 61 laser irradiation portion 62 mask 80 electronic component 100 wiring board with built-in electronic component

Claims (7)

laminating an insulating layer on a conductor layer forming a conductor circuit layer and a plane layer;
forming a cavity penetrating the insulating layer and exposing the plane layer as a bottom surface, the method comprising:
The formation of the cavity is performed by irradiating the insulating layer with a laser while shifting it by a predetermined pitch,
The processing diameter of the laser is made larger when forming an inner portion of the cavity surrounded by the outer peripheral portion than when forming the outer peripheral portion of the cavity. A method for manufacturing a wiring board with a cavity according to claim 1,
The pitch in forming the outer periphery of the cavity is smaller than the pitch in forming the inner portion of the cavity. A method for manufacturing a wiring board with a cavity according to claim 1 or 2,
In forming the cavity, the inner portion of the cavity is formed before the outer periphery of the cavity is formed. A wiring board with a cavity according to any one of claims 1 to 3,
The formation of the outer peripheral portion of the cavity and the formation of the inner portion of the cavity are performed by common laser irradiation. A method for manufacturing a wiring board with a cavity according to any one of claims 1 to 4,
When forming the outer peripheral portion of the cavity, the pitch is set to 20 to 80% of the machining diameter. A method for manufacturing a wiring board with a cavity according to any one of claims 1 to 4,
When forming the inner portion of the cavity, the pitch is 20-80% of the working diameter. A method for manufacturing a wiring board with a cavity according to any one of claims 1 to 6,
In forming the cavity, the processing diameter of the laser is changed using a mask.

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