JP7207784B2 - Membrane structures, devices and multilevel devices - Google Patents

Description

The present invention relates to film structures and devices, and more particularly to film structures, devices and multi-level devices containing quantized active monolayers.

Recently, higher specification performance is required in terms of hardware and software. For this reason, active research is being conducted into electronic devices that are faster, have a larger capacity, and have lower power consumption characteristics.

However, even if the existing MOSFET is miniaturized, there is a limit to miniaturization. This is because problems arise due to miniaturization itself. For example, as the density of devices on integrated circuits increases, high temperatures will be generated, which will cause problems that degrade device reliability.

Therefore, the approach through downscaling has a fundamental limitation in achieving characteristics of electronic devices required in the future.

Therefore, the inventors seek to solve the problems of the prior art through creative membrane structures, devices and multi-level devices that can be applied in future-oriented devices.

One technical problem to be solved by the present invention is to provide a film structure and device in which current flow is limited.

Another technical problem to be solved by the present invention is to provide a film structure and device including a quantized active monolayer.

Still another technical problem to be solved by the present invention is to provide a film structure and device including an active monolayer quantized in one or three axes.

Still another technical problem to be solved by the present invention is to provide a film structure and device having a superlattice structure.

Still another technical problem to be solved by the present invention is to provide a film structure and device having a quantum well structure.

Still another technical problem to be solved by the present invention is to provide a film structure and a device in which the current/gate voltage is equal to or higher than the threshold voltage and is equal to or lower than a predetermined slope.

Still another technical problem to be solved by the present invention is to provide a film structure and a device that are easy to manufacture.

Another technical problem to be solved by the present invention is to provide a multi-level device.

Another technical problem to be solved by the present invention is to provide a multilevel device with a simple manufacturing process.

The technical problem to be solved by the present invention is to provide an ultra-thin multi-level device.

The technical problems to be solved by the present invention are not limited to those described above.

A film structure according to an embodiment of the present invention is alternately stacked with at least one active monolayer having quantized energy levels in at least one axis and said at least one active monolayer. Although current flows through the active monolayer, although it contains at least one barrier, the quantized energy levels may limit current flow.

According to one embodiment, the active monolayer and the barrier may have a hybrid superlattice structure.

According to one embodiment, the active monolayer can have a two-dimensional layered structure.

According to one embodiment, the monolayer and the barrier stack may provide a quantum well structure.

According to one embodiment, when the active monolayer is composed of metal monoatoms or TMDCs (Transitionmetal dichalcogenide), the active monolayer can have quantized energy levels in the minor axis direction.

According to one embodiment, when the active monolayer is made of metal oxide, the active monolayer can have three-axis quantized energy levels.

According to one embodiment, current flow may be limited by the quantized energy level even if the strength of the field applied to the active monolayer increases.

A membrane structure according to an embodiment of the present invention comprises at least one active monolayer having a two-dimensional layered structure and at least one barrier layer alternately stacked with the at least one active monolayer. ), but the active monolayer and the barrier can have a hybrid superlattice structure.

A film structure according to an embodiment of the present invention comprises at least one active monolayer of a quantum well structure, said active monolayer having quantized energy levels in at least one axial direction. , the quantized energy level may limit the current flow through the active monolayer.

A device according to an embodiment of the present invention includes a gate electrode, a gate insulating film on one side of the gate electrode, at least one layer of active monolayer provided on one side of the gate insulating film, and At least one layer of barrier stacked alternately with the active monolayer, and a source electrode and a drain electrode through which current flows through the active monolayer when a gate voltage is applied to the gate electrode.

According to one embodiment, the active monolayer can have a quantized energy level in at least one axis.

According to one embodiment, the quantized energy level can limit the amount of current flowing through the active monolayer when the gate voltage is above the turn on voltage.

According to one embodiment, the current change between the source and drain electrodes with respect to the voltage applied to the gate electrode may be less than or equal to a predetermined slope due to the limitation of the amount of current flowing through the active monolayer.

According to one embodiment, when the active monolayer includes at least one of metal monatoms and TMDC, the active monolayer may have quantized energy levels in the minor axis direction.

When the active monolayer comprises a metal oxide, the active monolayer can have three axially quantized energy levels.

According to one embodiment, the active monolayer may include a plurality of crystalline regions and an amorphous region surrounding the crystalline regions.

According to one embodiment, the active monolayer may have energy levels quantized in three axial directions.

According to one embodiment, the barrier may be deposited between the active monolayer and the source and drain electrodes.

According to one embodiment, the active monolayer can have a structure sandwiched between the barriers.

According to one embodiment, the active monolayer has a predetermined thickness, and the predetermined thickness can be nano-sized.

A device according to an embodiment of the present invention includes a gate electrode, a gate insulating film on one side of the gate electrode, and at least one active monolayer provided on one side of the gate insulating film, wherein the Even if the gate voltage applied to the gate electrode increases, the increase in current through the active monolayer can be limited.

A multi-level device according to an embodiment of the present invention includes a gate electrode, a first active layer formed on one side of the gate electrode, a first TMDC (Transition metal dichalcogenide), and a first active layer formed on one side of the first active layer. , a second active layer including a second TMDC, source and drain electrodes provided on one side of the second active layer, and a barrier layer separating the first active layer and the second active layer.

A multi-level device according to an embodiment of the present invention comprises a gate electrode, a first active layer formed on one side of the gate electrode, a first active layer including a first metal monoatom, formed on one side of the first active layer, A second active layer containing a second metal monoatom, source and drain electrodes provided on one side of the second active layer, and a barrier layer separating the first active layer and the second active layer may be included.

According to one embodiment, the number of activated active layers among the first and second active layers may be controlled by a gate voltage applied to the gate electrode.

According to one embodiment, the first active layer, the barrier layer, the second active layer and the source and drain electrodes may be sequentially stacked.

According to one embodiment, the source and drain electrodes may be in electrical contact only with the second active layer.

According to one embodiment, the source electrode and the drain electrode may be electrically non-contact with the first active layer.

According to one embodiment, the first gate voltage range, the second gate voltage range, and the third gate voltage range applied to the gate electrode are divided into the first gate voltage range, the second gate voltage range, and the third gate voltage range in the increasing order of the gate voltage. A second and said third gate voltage range may be provided.

According to one embodiment, when a gate voltage within the first gate voltage range is applied to the gate electrode, only the first active layer is activated, and a gate voltage within the third gate voltage range is applied to the gate electrode. The first and second active layers may be activated when is applied.

According to one embodiment, the first active layer may be in a saturation state within the second gate voltage range.

According to one embodiment, when a gate voltage in the first gate voltage range or the second gate voltage range is applied to the gate electrode, current flowing through the first active layer may cause the second active layer to collapse on the gate electrode. can be masked.

According to one embodiment, the first and second active layers may include TMDC monolayers.

A method for manufacturing a multilevel device according to an embodiment of the present invention comprises depositing a first active layer including a first TMDC, depositing a barrier layer on one side of the first active layer, and depositing a barrier layer on one side of the barrier layer. depositing a second active layer comprising a second TMDC in the .

According to one embodiment, depositing an active layer of at least one of depositing the first active layer and the second active layer includes depositing the TMDC monolayer, wherein depositing the TMDC monolayer comprises: A first chalcogen deposition step of dosing and purging a chalcogen source gas, increasing the pressure in the chamber by providing a metal precursor source gas comprising a transition metal precursor with the outlet of the chamber closed. a metal precursor source gas pressure dosing for adsorbing the transition metal precursor to the substrate; a first main purging step for purging after the metal precursor source gas pressure dosing; After one main purging step, a reactant gas dosing step of providing a reactant gas, a second main purging step of purging after the reactant gas dosing step, and a second chalcogen deposition step of dosing and purging the chalcogen source gas. can.

A method for manufacturing a multi-level device according to an embodiment of the present invention comprises depositing a first active layer including a first metal monoatom, depositing a barrier layer on one side of the first active layer, and depositing the barrier layer. depositing a second active layer comprising a second metal monoatom on one side of the .

According to one embodiment, at least one active layer depositing step of depositing the first active layer and the second active layer comprises: a metal precursor source containing a metal precursor with an outlet of the chamber closed; source gas pressure dosing for increasing the pressure in the chamber by providing a gas to adsorb the metal precursor onto the substrate; a first main purge for purging after the source gas pressure dosing step; A main purging step, a reaction gas dosing step of providing a reaction gas after the first main purging step, and a second main purging step of purging after the reaction gas dosing step may be included.

A film structure according to an embodiment of the present invention is alternately stacked with at least one active monolayer having quantized energy levels in at least one axis and said at least one active monolayer. At least one layer of barrier may be included.

According to one embodiment, the stack of said monolayer and said barrier may provide a quantum well structure, wherein the active monolayer has quantized energy levels in at least one axis so that the gate voltage current flow may be limited despite the swing of .

Also, although the active monolayer has a two-dimensional layered structure, it has a hybrid superlattice structure, which may improve stability.

In addition, since the manufacturing process of the membrane structure according to an embodiment of the present invention can be performed in a low temperature process, excellent process stability can be provided.

Also, a hybrid superlattice structure can be easily provided by the manufacturing process of the membrane structure according to an embodiment of the present invention.

A multi-level device according to one embodiment of the present invention can provide multi-level conductivity.

A multi-level device according to an embodiment of the present invention can provide a simple manufacturing method.

A multi-level device according to an embodiment of the present invention can provide easy active layer thickness control.

A multi-level device according to an embodiment of the present invention can provide ultra-thin properties.

The effects of the present invention are not limited to the effects described above, and can be made clearer by the following description.

1 is a drawing for explaining a device according to a first embodiment of the present invention; 1 is a drawing for explaining a device according to a first embodiment of the present invention; 1 is a drawing for explaining a device according to a first embodiment of the present invention; FIG. 4 is a diagram for explaining in detail the active monolayer according to the first embodiment of the present invention; FIG. FIG. 4 is a diagram for explaining in detail the active monolayer according to the first embodiment of the present invention; FIG. FIG. 4 is a drawing for explaining a method of manufacturing a device according to the first embodiment of the present invention; FIG. FIG. 4 is a drawing for explaining a method of manufacturing a device according to the first embodiment of the present invention; FIG. FIG. 4 is a drawing for explaining a method of manufacturing a device according to the first embodiment of the present invention; FIG. FIG. 4 is a drawing for explaining a method of manufacturing a device according to the first embodiment of the present invention; FIG. FIG. 4 is a diagram for explaining operating characteristics of the device according to the first embodiment of the present invention; FIG. FIG. 4 is a diagram for explaining operating characteristics of the device according to the first embodiment of the present invention; FIG. FIG. 4 is a diagram for explaining operating characteristics of the device according to the first embodiment of the present invention; FIG. FIG. 5 is a drawing for explaining a device according to a second embodiment of the present invention; FIG. FIG. 5 is a drawing for explaining a device according to a second embodiment of the present invention; FIG. FIG. 5 is a diagram for explaining operating characteristics of a device according to a second embodiment of the present invention; FIG. FIG. 5 is a diagram for explaining operating characteristics of a device according to a second embodiment of the present invention; FIG. FIG. 5 is a diagram for explaining operating characteristics of a device according to a second embodiment of the present invention; FIG. FIG. 8 is a drawing for explaining a device according to a third embodiment of the present invention; FIG. FIG. 8 is a drawing for explaining a device according to a third embodiment of the present invention; FIG. FIG. 8 is a diagram for explaining operating characteristics of a device according to a third embodiment of the present invention; FIG. FIG. 8 is a diagram for explaining operating characteristics of a device according to a third embodiment of the present invention; FIG. FIG. 8 is a diagram for explaining operating characteristics of a device according to a third embodiment of the present invention; FIG. 1 is a diagram for explaining a multi-level device according to a first embodiment of the present invention; FIG. 4A to 4C are diagrams for explaining a method of manufacturing a multi-level device according to the first embodiment of the present invention; FIG. 4 is a diagram for explaining characteristics of a multi-level device according to the first embodiment of the present invention; FIG. Figure 3 illustrates a multi-level device according to a second embodiment of the invention; 6 is a flow chart for explaining a method of manufacturing a multi-level device according to a second embodiment of the present invention; FIG. 5 is a diagram for explaining characteristics of a multi-level device according to a second embodiment of the present invention; FIG. 4 is the result of measuring the surface coverage by the pressure dosing step. Figure 2 illustrates a WS2 thin film produced according to one embodiment of the present invention; Figure 2 illustrates a WS2 thin film produced according to one embodiment of the present invention; Figure 2 illustrates a WS2 thin film produced according to one embodiment of the present invention; Figure 2 illustrates a WS2 thin film produced according to one embodiment of the present invention;

Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. However, the technical idea of the present invention is not limited to the embodiments set forth herein, and may be embodied in other forms. Rather, the embodiments presented are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the invention to those skilled in the art. .

When a component is referred to herein as being on top of another component, it may be formed directly on the other component or with a third component interposed therebetween. It means that you may Also, in the drawings, the thickness of films and regions are exaggerated for effective description of technical content.

Also, although the terms first, second, third, etc. have been used in various embodiments herein to describe various components, these components should not be limited by such terms. not. These terms are only used to distinguish one component from another. Thus, what is referred to as the first component in any one embodiment may be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiments. Also, the term "and/or" is used herein to include at least one of the elements listed before and after.

The singular references herein include the plural unless the context clearly dictates otherwise. Also, terms such as "including" or "having" are intended to indicate the presence of any feature, number, step, component, or combination thereof described in the specification, It should not be understood as excluding the possibility of the presence or addition of one or more other features, figures, steps, components or combinations thereof. In addition, the term "connection" is used herein to include both indirect and direct connection of multiple components.

In addition, in describing the present invention below, if it is determined that a specific description of related known functions or configurations may unnecessarily obscure the gist of the present invention, the detailed description will be provided. are omitted.

A film according to an embodiment of the present invention comprises at least one active monolayer having quantized energy levels in at least one axial direction and at least one layer alternating with said at least one active monolayer. Although current flows through the active monolayer, current flow may be limited by the quantized energy levels.

At this time, since the active monolayer has a quantized energy level in at least one axial direction, the amount of current flowing through the active monolayer can be limited.

If the active monolayer includes at least one of metal monatoms and TMDC, the active monolayer can have quantized energy levels along the short axis. Alternatively, when the active monolayer comprises a metal oxide, the active monolayer can have three axially quantized energy levels. In this case, despite field swings, the intensity of the current flowing through the active monolayer may be constant. That is, current saturation can be provided.

Current saturation characteristics can be understood as a unique effect according to one embodiment of the present invention. Hereinafter, for a detailed description, a first embodiment utilizing metal oxide as an active monolayer will be described with reference to FIGS. 1 to 12. FIG.

1 to 3 are drawings for explaining a device according to a first embodiment of the present invention.

Referring to FIGS. 1-3, a device 100a according to a first embodiment of the present invention includes a substrate (not shown), a gate electrode 120, a first barrier 130, an active monolayer 140, a second barrier 150 and a source electrode. At least one of 160 and drain electrode 162 may be included. A membrane structure including at least one of an active monolayer and a barrier may be referred to. Each configuration will be described below.

The substrate is not limited in kind, and may be made of at least one of a silicon substrate, a glass substrate, and a flexible substrate, for example.

The gate electrode 120 is configured to receive a gate voltage, and may be made of a conductive material, such as a metal material.

The gate insulating layer 125 functions as a dielectric layer, and may be made of at least one insulating material, for example, a silicon-based insulating material or a metal oxide-based insulating material. The thickness of the gate insulating layer 125 may be determined according to the operating range of the applied gate voltage. For example, when the operating range of the gate voltage is low, the thickness of the insulating layer 130 may be thinner than when the operating range of the gate voltage is high.

At least one of the first and second barriers 130, 150 may comprise at least one of an organic material, an inorganic material, and an organic-inorganic composite. When the barrier is an organic material, the barrier may include at least one of 4MP (4-mercaptophenol) and Zn4MP (Zinc 4-mercaptophenol), and when the barrier is an organic-inorganic composite, the barrier can include 4MP with an Al linker, ie Al4MP.

In the following, for convenience of explanation, it is assumed that the first and second barriers 130, 150 are Zn4MP.

The barrier can protect the active monolayer. For example, when other layers are formed after the active monolayer 140 is formed, the second barrier 150 may cause the active monolayer 140 to be unintentionally doped, or the active monolayer 140 may be unintentionally doped or a precursor from the deposition of the other layer may become the active layer. Penetration into the monolayer 140 can be minimized.

The active monolayer 140 may comprise a metal oxide such as ZnO. Also, according to one embodiment, the active monolayer 140 may have a two-dimensional layered structure. At this time, the two-dimensional layered structure of the active monolayer 140 can form a superlattice structure through predetermined lamination.

According to one embodiment, the thickness of the active monolayer 140 may be within a range exhibiting FET (Field Effect Transistor) characteristics. For example, when the active monolayer 140 includes zinc oxide, it may have a thickness of 1.5 nm or more. If the zinc oxide thickness is less than 1.5 nm, the zinc oxide may destroy FET characteristics. Also, the active monolayer may have a thickness of 20 nm or less. If the thickness of the active monolayer is thicker than 20 nm, the increase in operating voltage may lead to a disadvantage in terms of power consumption. In addition, since the gate insulating film 125 must be thicker in order to withstand a large gate voltage, it does not meet the trend of device miniaturization.

With continued reference to FIG. 1, at least one active monolayer and at least one barrier layer may be alternately stacked. A barrier may then be provided on at least one side of the active monolayer. If barriers are provided on both one side and the other side of the active monolayer, the active monolayer may have a structure sandwiched between said first and second barriers. From another point of view, at least one surface of the active monolayer 140 can be in direct contact with the barrier. That is, one surface of the active monolayer 140 may be in surface contact with the first barrier 130 and the other surface may be in surface contact with the second barrier 150 . In the following, for convenience of explanation, it is assumed that the first barrier 130 and the second barrier 150 are positioned on both sides of the active monolayer 140, respectively.

According to an example, each of the first barrier 130, the active monolayer 140, and the second barrier 150 can have a thickness of several nanometers.

According to one embodiment, the active monolayer and barriers adjacent to the active monolayer may form a hybrid superlattice structure. A superlattice structure may improve stability.

Also, according to one embodiment, the active monolayer may have a quantum well structure through the barrier by forming an adjacent interface with the active monolayer.

According to one example, the active monolayer 140 includes an amorphous region (AM_R) and a plurality of crystalline regions NC_R surrounded by the amorphous region AM_R, as illustrated in FIGS. It can be formed in layers. That is, the active monolayer may include both an amorphous region AM_R and a crystalline region NC_R.

At this time, each of the crystalline regions NC_R may be formed in a nano-size to have a quantum confinement effect. Specifically, the crystalline regions NC_R may have a size of several nm, for example, about 3 nm, and the average distance between the crystalline regions may be about 2.5 nm. In other words, the crystalline regions NC_R may be separated from each other by an average distance of about 2.5 nm, and the crystalline regions NC_R may have an isolated island shape surrounded by the amorphous regions AM_R. Also, the crystalline region NC_R may be randomly distributed in two dimensions within the amorphous region AM_R. Accordingly, the crystalline regions NC_R can provide a quantum confinement effect in three axial directions. That is, the crystalline region NC_R can provide a quantum confinement effect not only in the thickness direction but also in the planar direction.

Where the current saturation region (Vs region in FIG. 12) can be generated by triaxial quantization of the active monolayer. Reference will be made to FIGS. 4 and 5 for a specific description.

4 and 5 are diagrams for explaining in detail the active monolayer according to the first embodiment of the present invention.

Referring to FIG. 4, the amorphous region AM_R of the active monolayer 140 may have many localized states. Alternatively, the crystalline regions NC_R of the active monolayer 140 may have fewer discrete localized states than the states caused by the amorphous regions AM_R. In this case, the specific energy state AM_E among the unevenly distributed energy states of the amorphous regions AM_R and the specific energy state NC_E among the unevenly distributed energy states of the crystalline regions NC_R are in resonance energy matching with each other. matching).

Hybridization by resonance energy matching can provide a quantized conduction state. The quantized conductivity state provides a conductive state, but can provide limited current transfer. The quantized conductivity states will be described in more detail with reference to FIG.

FIG. 5 illustrates the density of state (DOS) according to one embodiment of the invention. By the way, although the DOS simulation results use a program called VASP (Vienna ab initio simulation), the manufactured active monolayer is calculated by PBE (Perdew-Burke-Ernzerhof) exchange-correlation functional and PAW (projector-augmented waveform method) pseudo-pseudo can be obtained by doing

DOS in FIG. 5 shows the change in the number of electronic states due to the increase in electron energy. As illustrated in FIG. 5, the active monolayer 140 according to one embodiment of the present invention may have a valence band and a conduction band.

The valence band can be divided into an extended state and a maldistributed state according to a mobility edge. Also, the conduction band can be divided into an extended state and a maldistributed state by the mobility edge.

As illustrated in FIG. 5, the active monolayer 140 according to one embodiment of the present invention has a first electronic state in the low-level electronic energy range (approximately 2.8 eV to 2.9 eV) within the conduction band. and providing a second electronic state number at a high-level electron energy range (greater than or equal to about 3.2 eV) within the conduction band that is higher than the low-level electron energy range.

At this time, the first electronic state number curve in the low-level electron energy range and the second electronic state number curve in the high-level electron energy range may be discontinuous. In other words, the maximum electron energy value of the low-level electron energy range (about 2.9 eV) may be less than the minimum electron energy value of the high-level electron energy range (about 3.2 eV). Here, the maximum number of the first electronic states within the low-level electron energy range may be smaller than the minimum number of the second electronic states within the high-level electron energy range.

According to one embodiment, the low-level electron energy range and the high-level electron energy range may be provided at electron energies higher than the mobility edge in the conduction band (ie mobility edge quantization). This may mean that the energy level of the maldistributed state of the amorphous region AM_R of the active monolayer 140 and the energy level of the maldistributed state of the crystalline region are matched, but are matched above the mobility edge. Accordingly, the active monolayer 140 can provide a conductive state for the low-level electronic energy range and the high-level electronic energy range. At this time, the conduction state in the low-level electron energy range having the first electron state number on the mobility edge can be defined as a quantized extended state.

Also, it is possible to provide an unevenly distributed state (that is, the number of electronic states is 0) between the low-level electronic energy range and the high-level electronic energy range. This may mean that the crystalline region NC_R of the active monolayer has no energy states between said low-level electron energy range and said high-level electron energy range. Accordingly, resonance energies are not matched between the crystalline region NC_R and the amorphous region AM_R between the low-level electron energy range and the high-level electron energy range.

According to one embodiment, the low-level electron energy range can be provided by resonance energy matching of crystalline regions NC_R and amorphous regions AM_R of the active monolayer 140, as described above. At this time, since the crystalline region NC_R has a quantum confinement effect in three axial directions, a curve defined by the low-level electron energy range and the number of first electron states can have a very limited area. This may mean that there may be very limited carriers.

That is, since the active monolayer 140 has a limited number of electronic states in a low-level energy state, current saturation (Vs region in FIG. 12) can be provided.

Referring again to FIG. 1, the source and drain electrodes 160, 162 can contact the topmost barrier. From another point of view, the source and drain electrodes 160 , 162 can be in contact with the top second barrier 150 and not in contact with the first barrier 130 and the active monolayer 140 .

The device according to the first embodiment of the present invention has been described above from the structural point of view. A method for manufacturing a device according to the first embodiment of the present invention will now be described with reference to FIGS. 6 to 9. FIG.

6 to 9 are drawings for explaining the method of manufacturing the device according to the first embodiment of the present invention.

Referring to FIG. 9, the device manufacturing method according to the first embodiment of the present invention includes steps of preparing a substrate, a gate electrode and a gate insulating layer (S110), forming a first barrier (S120), forming an active mono At least one step of forming a layer (S130), forming a second barrier (S140), and forming source and drain electrodes (S150) may be included. Each stage will be described below.

(Step S110)
Step S110 is a preparatory step, and may include preparing a substrate, forming a gate electrode on the substrate, and forming a gate insulating layer on the gate electrode.

(Step S120)
A first barrier may be formed on the gate insulating layer. The first barrier may be manufactured through molecular layer deposition (MLD). For example, when depositing Zn4MP through the molecular layer deposition method, the molecular layer deposition method may include a DEZ precursor providing step, a purge step, a 4MP precursor providing step, and a purge step. Thereby, the first barrier 130 may be deposited.

(Step S130)
An active monolayer 140 may be deposited at step S130. Refer to FIG. 7 to specifically describe step S130.

FIG. 7 is a flowchart illustrating in detail step S130 according to one embodiment of the present invention.

Referring to FIG. 7, a method for manufacturing an active monolayer according to an embodiment of the present invention includes a source gas pressure dosing step (S210), a first main persing step (S220), a reaction gas dosing step (S230), and a second gas dosing step (S230). At least one step of the main parsing step (S240) may be included. Each stage will be described below.

(Step S210)
A source gas may be prepared for the source gas pressurized dosing step (S210). The source gas may be variously prepared according to the type of film to be deposited. For example, if the film to be deposited is a metal oxide, a corresponding metal precursor source gas can be prepared. For example, if the film to be deposited is zinc oxide (ZnO), the source gas may include DEZ (diethyl zinc).

The source gas may be provided with the outlet of the chamber closed. Accordingly, the pressure within the chamber may increase as the source gas flows into the chamber. In other words, the supply of the source gas increases the pressure in the chamber, so that the substrate can be adsorbed in a pressurized atmosphere of the source gas. Also, the increased chamber pressure may be maintained for a predetermined period of time. Accompanying this, substrate adsorption efficiency can be improved.

At this time, step S210 may exceed 0.03 Torr, preferably 0.1 Torr, or even 0.3 Torr or more. Also, the process temperature in step S210 may range from 80 degrees to 250 degrees. As an example, the process temperature can be 100-150 degrees.

(Step S220)
An inert gas may be used in the first main purging step (S220), and the inert gas may be, for example, argon (Ar) or nitrogen (N2) gas. The purging step may remove excess source gas that has not been adsorbed onto the surface of the substrate.

(Step S230)
In the reactive gas dosing step (S230), the reactive gas may react with the source gas to reduce the film to be deposited. For example, if the source gas includes DEZ, the reactant gas can consist of H2O.

(Step S240)
After the reaction gas dosing step, a second main purging step (S240) may be further performed. Excess gas that could not be adsorbed on the surface of the substrate can thereby be removed.

The steps S210 to S240 according to one embodiment of the present invention have been described above. The pressure dosing of step S210 will be described in detail below.

(Pressure dosing in step S210)
The source gas pressurized dosing step of step S210 may be performed in a pressurized atmosphere. In other words, the source gas pressurized dosing stage may be performed in a high pressure atmosphere, which may be abbreviated as the pressurization stage.

For convenience of explanation, the source gas pressure dosing step of step S210 will be described in detail, but it goes without saying that the step of dosing the reaction gas of step S230 is also performed.

The pressure dosing step according to one embodiment may be performed in a closed chamber in which the substrate is provided. For example, with the outflow valve of the chamber closed, the metal precursor source gas is supplied into the chamber (sub-pressure dosing stage) to induce a high pressure in the chamber and maintain the induced high pressure (sub-exposure dosing stage). stage) can be done. By maintaining the high pressure for a predetermined period of time, the high pressure atmosphere can induce the metal precursor source gas to adsorb onto the target surface.

That is, the pressure dosing step may include at least one of a sub-pressure dosing step, a sub-exposure step, and a sub-percing step. The sub-pressure dosing step can be understood as a step of providing a source gas with the outlet of the chamber closed to reach a predetermined pressure in the chamber. The sub-exposure step is a step of maintaining a predetermined pressure provided by the sub-pressure dosing step. For this, all inlets and outlets of the chamber can be closed. That is, the chamber can be sealed. The sub-parsing step may be performed after the sub-exposure step to remove the excessively supplied source gas.

At this time, the pressure of the sub-exposure step may be maintained constant as shown in FIG. 8 even if the number of sub-exposure steps increases, or may be increased as shown in FIG. Incidentally, the Y-axis of FIG. 17 illustrates pressure and the X-axis illustrates process steps.

According to one embodiment, the process temperature of step S210 may be between 80 degrees and 250 degrees. More specifically, the process temperature can be between 100 degrees and 150 degrees.

Also, each sub-step of step S210 may be performed at the same temperature, especially at a low temperature. Low temperature as meant herein can mean 250 degrees or less.

The active monolayer 140 may be deposited through steps S210 to S240 described above. At this time, the thickness of the deposited film can be controlled by the number of repetitions of steps S210 to S240. For example, when the film to be deposited is zinc oxide, steps S210 to S240 may be repeated so that the thickness of the film exceeds 1.5 nm. Also, when the film to be deposited is zinc oxide, steps S210 to S240 may be repeated so that the thickness of the film is 20 nm or less.

The active monolayer fabricated through steps S210-S240 can provide DOS simulation results, as illustrated in FIG. That is, it is possible to provide a quantized conductivity state, more specifically a quantized conductivity state at a higher energy than the mobility edge. As described above, the DOS simulation results use a program called VASP (Vienna ab initio simulation), but the manufactured active monolayer is combined with PBE (Perdew-Burke-Ernzerhof) exchange-correlation functional and PAW (projector-augmented waveform) pseudo-pseudomethod. can be obtained by calculating

(Step S140)
Referring again to FIG. 6, a second barrier 150 may be deposited over active monolayer 140 . Since step S140 corresponds to step S120, a detailed description thereof will be omitted.

(Step S150)
Source and drain electrodes 160 and 162 may be deposited on the second barrier 150 . That is, the source and drain electrodes 160 and 162 may contact the second barrier 150 . From another point of view, the source and drain electrodes 160 , 162 can be in non-contact with the first barrier 130 and the active monolayer 140 .

The device according to the first embodiment of the present invention can be manufactured through steps S110 to S150 described above.

The method of manufacturing the device according to the first embodiment of the present invention has been described above with reference to FIGS. The method of fabricating the device according to the embodiment of the present invention is advantageous in that the process is generally performed at low temperature and in that the hybrid superlattice structure can be easily fabricated.

Hereinafter, operation characteristics of the device according to the first embodiment of the present invention will be described with reference to FIGS. 10 to 12. FIG.

10 to 12 are diagrams for explaining the operating characteristics of the device according to the first embodiment of the present invention.

First, a device according to the first embodiment of the present invention was manufactured in order to examine the operating characteristics of the device according to the first embodiment of the present invention.

Zn4MP was deposited as the first barrier 130 through step S120 of the manufacturing method described above. More specifically, DEZ was provided at 30 mTorr pressure for 2 seconds and purged for 20 seconds. 4 MP was then applied at 10 mTorr pressure for 20 seconds and purged for 200 seconds. The process temperature was 120 degrees. Each step of step S120 was repeated for 25 cycles to deposit the first barrier 130 with a thickness of 10 nm.

After depositing the first barrier 130 through step S120, step S130 is performed according to the process illustrated in FIG. Referring to FIG. 10, DEZ was prepared as a source gas and H2O was prepared as a reaction gas. DEZ was provided through a sub-pressure dosing step by step S210. That is, in the first sub-pressurized dosing step, DEZ was supplied with the outlet of the chamber closed, and the atmosphere in the chamber was maintained at 1 Torr for 3 seconds and then purged for 15 seconds. Then, in the second sub-pressurized dosing step, DEZ was supplied with the outlet of the chamber closed, and the chamber was kept pressurized at 1 Torr for 3 seconds, and then purged again for 15 seconds. Subsequently, in the third sub-pressure dosing step, DEZ was supplied with the outlet of the chamber closed so that the pressure in the chamber reached 1 Torr and was maintained for 3 seconds. After that, the fourth sub-pressure dosing step was performed by purging for 15 seconds. The pressure in the chamber during the fourth sub-pressure dosing stage was 1 Torr. Accordingly, step S210 is performed. After step S210, steps S220 and S230 are performed. Since step S230 corresponds to step S210, a detailed description thereof will be omitted. After step S230, purge through step S240. Such a stage was defined as 1 cycle, and 15 cycles were performed. This allowed the deposition of a 3 nm thick active monolayer 140 . The vapor deposition process of the active monolayer 140 was also set to 110 to 120 degrees.

Then, the second barrier 150 is deposited again in step S130, and the source and drain electrodes 160 and 162 are deposited in step S140.

Thus, a device according to the first example of the present invention was manufactured.

Referring to FIG. 11, in the device according to the first embodiment of the present invention, the first and second barriers 130, 150 and the active monolayer 140 may have a quantum well structure. At this time, since the active monolayer 140 has a quantum confinement effect in three axial directions, current movement may be restricted.

Referring to FIG. 12, the device 100a manufactured according to the first embodiment of the present invention has a turn-on voltage around 1V. That is, a current flows between the source and drain electrodes 160 and 162 by applying a voltage of 1 V or more to the gate electrode 120 . At this time, as the gate voltage applied to the gate electrode 120 increases, the current flowing between the source and drain electrodes 160 and 162 increases. However, when the gate voltage is increased above 2V, a current saturation region (Vs) appears where the current between the source and drain electrodes 160, 162 is constant despite the increase in gate voltage. A constant current saturation region was clearly observed in both linear and log scales. That is, the current between the source and drain electrodes was saturated despite the gate voltage swing. It is interpreted that this is because the active monolayer 140 has a quantum confinement effect in three axial directions, as described with reference to FIGS. From another point of view, it can be interpreted that the active monolayer 140 is on DOS and there can be very limited carriers in the low-level electron energy range.

The device according to the first embodiment of the present invention has been described above with reference to FIGS. 1 to 12. FIG.

In describing the first embodiment of the present invention, it was assumed that active monolayer 140 comprised ZnO, a metal oxide. However, it goes without saying that the active monolayer 140 can consist of a material having a plurality of crystalline regions and amorphous regions surrounding the crystalline regions, and on DOS limited (discontinuous) rows on mobility edges. It goes without saying that it can consist of a material having a level electron energy range.

A device according to a second embodiment of the present invention will now be described with reference to FIGS. 13 to 17. FIG. The second embodiment of the present invention differs from the first embodiment of the present invention in that the active monolayer contains metal monoatoms. The second embodiment of the present invention will be described below with a focus on the points of difference, and the description of the parts common to the first embodiment will be omitted.

13 and 14 are drawings for explaining a device according to a second embodiment of the present invention.

Referring to FIGS. 13 and 14, the active monolayer 142 of the device 100b according to the second embodiment of the present invention can contain metal monoatoms. For example, the metal monoatom can be one of tungsten (W), molybdenum (Mo) and copper (Cu), but is not limited thereto.

The active monolayer 142 may also have a thickness of several nanometers. For example, the thickness of the active monolayer 142 may also be within a range exhibiting FET (Field Effect Transistor) characteristics. More specifically, the thickness of active monolayer 142 can be between 1.0 nm and 20 nm.

As described in the first embodiment, the active monolayer 142 according to the second embodiment may also have a quantum well structure and may have a hybrid superlattice structure. Also, the active mono layer 142 can have states that are quantized along at least one axis, eg, along the minor axis. Accordingly, the current flow can be restricted even at the turn-on voltage or higher. More specifically, the current slope between the source and drain electrodes with increasing gate voltage can be less than or equal to 15.1 nA/V.

FIG. 15 is a drawing for explaining a device manufacturing method according to a second embodiment of the present invention.

In order to examine the operation characteristics of the device according to the second embodiment, the device according to the second embodiment was manufactured by the device manufacturing method described with reference to FIGS. Except for the active monolayer 142, the manufacturing process conditions were the same as those of the device according to the first embodiment described with reference to FIG. A detailed process for forming the active monolayer 142 according to the second embodiment is shown in FIG.

Referring to FIG. 15, WF6 was prepared as a source gas in step S210. The process temperature in step S210 was set to 120 degrees. WF6 was provided in five sub-pressure dosings, although step S210 was performed. That is, during the first sub-pressure dosing, WF6 was supplied with the outlet of the chamber closed, and the chamber pressure was increased to 1.0 Torr. After that, the inlet of the chamber was also closed for 30 seconds, and WF6 was permeated at a pressure of 1.0 Torr. After that, it was sub-parsed for 30 seconds. Then, during the second sub-pressure dosing, WF6 was supplied with the outlet of the chamber closed, and the pressure in the chamber was increased again to 1.0 Torr. After that, the inlet of the chamber was also closed for 30 seconds, and WF6 was permeated at a pressure of 1.0 Torr. The fifth sub-pressurized dosing step and the fifth sub-permeation step were carried out in the same manner.

After that, the first main parsing (process temperature: 120 degrees) was performed for 30 seconds in step S220.

After that, Si2H6 was prepared as a reaction gas in step S230. The process temperature of step S230 was set to 120 degrees.

Although performing step S230, SiH6 was provided for five sub-pressure dosing and sub-exposure steps. At this time, process variables such as pressure and time were the same as those of WF6 dosing.

After that, the second main parsing (process temperature of 120 degrees) was performed for 30 seconds in step S240.

At this time, the height of the tungsten layer is controlled by repeatedly performing steps S210 to S240. In this experimental example, three cycles were repeated to produce a tungsten metal monoatomic layer with a thickness of 1 nm. This allowed the deposition of an active monolayer.

16 and 17 are diagrams for explaining the operating characteristics of the device according to the second embodiment of the present invention.

Referring to FIG. 16, in the device 100b according to the second embodiment of the present invention, the first and second barriers 130, 150 and the active monolayer 142 may have a quantum well structure. At this time, since the active monolayer 140 has a quantum confinement effect in the minor axis direction (eg, thickness direction), current movement may be restricted.

Referring to FIG. 17, the device manufactured according to the second embodiment of the present invention has a turn-on voltage around -5V. That is, a current flows between the source and drain electrodes 160 and 162 by applying a voltage of -5 V or more to the gate electrode 120 . At this time, as the gate voltage applied to the gate electrode 120 increases, the current flowing between the source and drain electrodes 160 and 162 increases. However, when the gate voltage is increased to about 7V or more, it can be seen that a region appears between the source and drain electrodes 160 and 162 where the increase in current is limited despite the increase in gate voltage. That is, it can be seen that the increase in the current between the source and drain electrodes was extremely limited to 15.1 nA/V despite the swing of the gate voltage. This is interpreted because the active mono layer 142 has energy levels that are quantized in the minor axis direction.

The device according to the second embodiment of the present invention has been described above with reference to FIGS. 13 to 17. FIG. A device according to a third embodiment of the present invention will now be described with reference to FIGS. 18-22. The third embodiment of the present invention is different from the first embodiment of the present invention in that the active monolayer includes TMDC (Transitionmetal dichalcogenide). The third embodiment of the present invention will be described below, focusing on the points of difference, and the description of the parts common to the first embodiment will be omitted.

18 and 19 are drawings for explaining a device according to a third embodiment of the present invention.

18 and 19, active monolayer 146 of device 100c according to a third embodiment of the present invention can include TMDC. For example, TMDC can be one of WS2 and MOS2, but is not limited thereto.

The active monolayer 146 may also have a thickness of several nanometers. The active monolayer 146 may also have a thickness of several nanometers. For example, the thickness of the active monolayer 142 may also be within a range exhibiting FET (Field Effect Transistor) characteristics. More specifically, the thickness of active monolayer 142 can be between 1.0 nm and 20 nm.

As described in the first embodiment, the active monolayer 146 according to the third embodiment can also have a quantum well structure and can have a hybrid superlattice structure. Also, the active mono layer 146 can have states that are quantized along at least one axis, eg, along the minor axis. Accordingly, the current flow can be restricted even at the turn-on voltage or higher. More specifically, the slope of the current between the source and drain electrodes with increasing gate voltage can be -0.2 nA/V or less.

FIG. 20 is a drawing for explaining a device manufacturing method according to a third embodiment of the present invention.

In order to examine the operating characteristics of the device according to the third embodiment, the device according to the third embodiment was manufactured by the device manufacturing method described with reference to FIGS. Except for the active monolayer 146, the manufacturing process conditions were the same as those of the device according to the first embodiment described with reference to FIG. A detailed process for forming the active monolayer 146 according to the third embodiment is shown in FIG.

Referring to FIG. 15, the chalcogen source gas was heated to over 100° C., provided for 30 seconds, and then purged for 30 seconds. As a result, the substrate was treated with S (sulfur).

After that, WF6 was prepared as a source gas in step S210. The process temperature in step S210 was set to 120 degrees. WF6 was provided in five sub-pressure dosings, although step S210 was performed. That is, during the first sub-pressure dosing, WF6 was supplied with the outlet of the chamber closed, and the chamber pressure was increased to 1.0 Torr. After that, the inlet of the chamber was also closed for 30 seconds, and WF6 was permeated at a pressure of 1.0 Torr. After that, it was sub-parsed for 30 seconds. Then, during the second sub-pressure dosing, WF6 was supplied with the outlet of the chamber closed, and the pressure in the chamber was increased again to 1.0 Torr. After that, the inlet of the chamber was also closed for 30 seconds, and WF6 was permeated at a pressure of 1.0 Torr. The fifth sub-pressurized dosing step and the fifth sub-permeation step were carried out in the same manner.

After that, the first main parsing (process temperature: 120 degrees) was performed for 30 seconds in step S220.

After that, Si2H6 was prepared as a reaction gas in step S230. The process temperature of step S230 was set to 120 degrees.

Although performing step S230, SiH6 was provided for five sub-pressure dosing and sub-exposure steps. At this time, process variables such as pressure and time were the same as those of WF6 dosing.

After that, the second main parsing (process temperature of 120 degrees) was performed for 30 seconds in step S240.

Thereby, the transition metal was vapor-deposited on the surface of the S (sulfur)-treated substrate. At this time, steps S210 to S240 are performed once. Thus, unlike the first and second examples, the cycle was not repeated.

Subsequently, the chalcogen source gas was heated to 100° C. or higher, provided for 30 seconds, and then purged for 30 seconds. This allowed the deposition of a 1 nm thick WS2 monolayer as the active monolayer 146 .

21 and 22 are diagrams for explaining the operating characteristics of the device according to the third embodiment of the present invention.

Referring to FIG. 21, in the device 100c according to the third embodiment of the present invention, the first and second barriers 130, 150 and the active monolayer 146 can have a quantum well structure. At this time, the active monolayer 146 has a quantum confinement effect in the minor axis direction (eg, thickness direction), so that current movement may be restricted.

Referring to FIG. 22, the device manufactured according to the third embodiment of the present invention has a turn-on voltage around 0V. That is, a current flows between the source and drain electrodes 160 and 162 by applying a voltage of about 0 V or higher to the gate electrode 120 . At this time, as the gate voltage applied to the gate electrode 120 increases, the current flowing between the source and drain electrodes 160 and 162 increases. However, it can be seen that when the gate voltage is increased to about −5 V or more, a region appears where the increase in current between the source and drain electrodes 160 and 162 is limited despite the increase in gate voltage. That is, it can be confirmed that the increase in the current between the source and drain electrodes was extremely limited to -0.2 nA/V despite the swing of the gate voltage. This is interpreted because the active mono layer 146 has quantized energy levels in the minor axis direction.

As described above, the film structures and devices according to the first to third embodiments of the present invention have superlattice structures and quantum well structures, and can have quantized energy levels in at least one axial direction. Accordingly, it is possible to provide a unique effect of restricting current movement even in a gate voltage section above the turn-on voltage and thus saturating the gate voltage.

In addition, in the description of the elements for the first to third embodiments, the description was made with reference to the transistor structure. Needless to say, it can also be applied to devices.

Because the membrane structures according to the first to third embodiments of the present invention limit the flow of current, the membrane structures according to the embodiments can provide multi-level properties. More specifically, when the film structures according to the embodiments are stacked, a non-gating region due to current saturation may occur between the turn-on voltages of the film structures. That is, the activation of the active monolayer of each membrane structure can be clearly demarcated. Accordingly, the film structure according to the embodiment of the present invention can be applied to multi-level devices. A multilevel device according to an embodiment of the present invention will now be described.

A multilevel device according to an embodiment of the present invention may have a structure in which a first active layer, a barrier layer and a second active layer are sequentially stacked. At this time, the number of activated active layers among the first and second active layers may be controlled by the gate voltage applied to the gate electrode of the multi-level device according to one embodiment.

Activation of the conductivity of the first and second active layers can be controlled by the magnitude of the gate voltage applied to the gate electrode. For example, a first gate voltage range, a second gate voltage range that is a region larger than the first gate voltage range, and a third gate voltage range that is a region larger than the second gate voltage range divide the cases where the gate electrode is applied. I will explain.

Incidentally, in this specification, the gate voltage is described based on the absolute value without distinguishing between positive and negative. Also, the first gate voltage range can be understood as R1 in FIGS. 25 and 28, the second gate voltage range as R2 in FIGS. 25 and 28, and the third gate voltage range as R3 in FIGS.

First, the lowest gate voltage in the first gate voltage range can be the first turn-on voltage. When a first turn-on voltage is applied to the gate electrode, the first active layer can be activated, ie turned-on. At this time, the second active layer may be deactivated, ie, in a turn-off state. Thereafter, as the voltage increases within the first gate voltage range, the magnitude of the current flowing between the source and drain electrodes may increase. That is, the current ratio between the source/drain electrodes may have a first slope as the gate voltage increases within the first gate voltage range.

For convenience of explanation, the application of the gate voltage in the second gate voltage range will be described later, and the application of the gate voltage in the third gate voltage range will be described first. When a gate voltage of a third gate voltage range, which is greater than the first and second gate voltage ranges, is applied, not only the first active layer but also the second active layer can be activated, ie turn-on. That is, the lowest gate voltage within the third gate voltage range can be the second turn-on voltage. Thereafter, as the gate voltage increases within a third gate voltage range, the magnitude of the current flowing between the source and drain electrodes may increase to a third slope. That is, the current ratio with increasing gate voltage within the third gate voltage range may have a third slope. At this time, when a gate voltage within the third gate voltage range is applied, both the first and second active layers are in a turn-on state. A larger current can flow than when the gate voltage is applied.

When a gate voltage within a second gate voltage range greater than the first gate voltage range and less than a third gate voltage range is applied to the gate electrode, only the first active layer may be activated, ie, turn-on. At this time, even if the gate voltage increases within the second gate voltage range, the degree of current transfer between the source/drain electrodes can be maintained. That is, when the gate voltage increases within the first gate voltage range, the magnitude of the current flowing between the source and the drain electrodes increases with a first slope, while the gate voltage increases within the second gate voltage range. The magnitude of the current flowing between the source and the drain electrodes may be smaller than the first and third slopes when λ increases. More specifically, when the gate voltage increases within a second gate voltage range, the current value between the source and drain electrodes may be constant. In other words, the second slope may be zero. Accordingly, a multilevel device according to an embodiment of the present invention can provide multilevel conductivity.

From a mechanism point of view, the first active layer can be turned-on when a gate voltage within the first gate voltage range is applied. In this case, the current flowing through the first active layer (the electrons in the source electrode tunnel through the second active layer and the barrier layer) shields the field due to the gate voltage from reaching the second active layer (shielding effect). ).

When a gate voltage in the second gate voltage range is applied, the current flowing through the first active layer still blocks the field due to the gate voltage from reaching the second active layer. Also, when the gate voltage of the second region is applied, the current between the source and drain electrodes is constant even if the gate voltage is increased due to the saturation of the first active layer. From another aspect, the barrier layer retards the gating of the second active layer with increasing gate voltage within the second gate voltage range and restricts the flow of electrons in the first active layer. can be maintained.

When a gate voltage in the third gate voltage range is applied, field penetration causes the gate voltage to extend into the second active layer. Accordingly, the second active layer can be turned on.

According to a first embodiment, the first active layer is preferably a TMDC monolayer so that the gate voltage reaches the second active layer by field penetration. If the first active layer is thicker, the magnitude of the current flowing through the first active layer increases. As a result, the shielding effect of the first active layer to prevent field permeation of the gate voltage into the second active layer is increased. In this case, an excessively high gate voltage is required to turn on the second active layer, which is disadvantageous in terms of power consumption. In addition, the thickness of the gate insulating film must be increased in order to withstand a large gate voltage. On the other hand, if the first active layer is a TMDC monolayer, the second active layer can be turned on within a normal gate voltage range, thus meeting the trend of power consumption and miniaturization.

A multi-level device according to an embodiment of the present invention will now be described in detail.

FIG. 23 is a diagram for explaining a multi-level device according to the first embodiment of the present invention.

Referring to FIG. 23, a multi-level device 300a according to the first embodiment of the present invention includes a substrate, a gate electrode 120, a gate insulating layer 125, a first active layer 142a, a barrier layer 132, a second active layer 142b, and a source electrode. 160 and drain electrode 162 .

As illustrated on the right side of FIG. 23, the first active layer 142a includes W, which is a metal monoatomic layer, the second barrier layer 132 includes ZnO, which is the first barrier layer, and 4MP, which is the second barrier layer. The second active layer 142b may include W, which is a metal monolayer.

That is, the multilevel device according to the first embodiment of the present invention can be based on the device according to the second embodiment of the present invention.

FIG. 24 is a diagram for explaining a method of manufacturing a multi-level device according to the first embodiment of the present invention.

Referring to FIG. 24, a method of manufacturing a multi-level device according to the first embodiment of the present invention includes steps of forming a gate electrode and a gate insulating layer on one side of the gate electrode (S310); depositing a first active layer containing a first metal monoatom on one side (S320); depositing a barrier layer on one side of the first active layer (S330); depositing a second metal on one side of the barrier layer (S330); The method may include at least one step of depositing a second active layer containing monatoms (S340) and forming source and drain electrodes on one side of the second active layer (S350). Each stage will be described in detail below.

(Step S310)
At step S310, a gate electrode and a gate insulating layer may be formed on a substrate on one side of the gate electrode. The gate electrode is a structure to which a gate voltage is applied and can be made of some material having conductivity, such as a metal. The gate insulating layer prevents leakage of a gate current applied to the gate electrode, and may be made of an insulating material, such as at least one of Al2O3, SiNx, and SiO2.

(Step S320)
A first active layer including a first metal monoatom may be deposited on one side of the gate insulating layer in step S320. Since step S320 corresponds to the process described with reference to FIG. 15, a detailed description thereof will be omitted. It goes without saying that the pressure dosing step described with reference to FIG. 7 can also be applied to step S320.

This may produce a first active layer comprising the first metal monoatoms. At this time, the thickness of the first active layer may be, for example, greater than 0.7 nm and less than 4 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm.

(Step S330)
At step S330, a barrier layer may be deposited on the first active layer. The barrier layer may be provided between a second active layer and a deposited first active layer, which will be described later.

At step S330, a barrier layer, such as an organic molecular layer and/or an inorganic molecular layer, may be formed through a molecular layer deposition method. In this case, step S330 may include a unit cycle of dosing and purging the organic precursor. One layer of organic molecules can be formed by a unit cycle. That is, the number of organic molecular layers to be deposited can be controlled by repeating the unit cycle.

In step S330, the pressure range may be 0.001-1 Torr, the process temperature range may be 80-200 degrees, especially the temperature range of the organic precursor may be 25-100 degrees.

This allows the desired thickness of the barrier layer to be deposited on the first active layer.

(Step S340 and Step S350)
Since step S340 corresponds to step S320, a detailed description thereof will be omitted. Source and drain electrodes may be formed after step S340.

A device having multi-level conductivity according to the first embodiment of the present invention can be manufactured through steps S310 to S350.

FIG. 25 is a diagram for explaining the characteristics of the multilevel device according to the first embodiment of the present invention.

First, for simulation, a multi-level device according to the first embodiment of the present invention was manufactured. At this time, the first active layer and the second active layer were manufactured according to step S320 (process conditions of FIG. 15). Also, the barrier layer formed between the first active layer and the second active layer consists of the first barrier layer and the second barrier layer. ZnO was formed as the first barrier layer. ZnO was also pressure dosed. That is, the ZnO metal precursor source gas, DEZ, was provided in five sub-pressure dosings. That is, during the first sub-pressure dosing, DEZ was supplied with the outlet of the chamber closed, and the chamber pressure was increased to 1.0 Torr. After that, the inlet of the chamber was also closed for 3 seconds and the DEZ was permeated at a pressure of 1.0 Torr. After that, it was sub-parsed for 30 seconds. Then, during the second sub-pressure dosing, DEZ was supplied with the outlet of the chamber closed, and the pressure in the chamber was increased again to 1.0 Torr. After that, the inlet of the chamber was also closed for 3 seconds and the DEZ was permeated at a pressure of 1.0 Torr. The fifth sub-pressurized dosing step and the fifth sub-permeation step were carried out in the same manner. After this, the first main parsing stage was performed for 15 seconds. Subsequently, H2O was provided for five sub-pressure dosing, sub-exposure steps. At this time, process parameters such as pressure and time were the same as those of DEZ dosing. After that, a second main persing step was performed to fabricate a first barrier layer.

A second barrier layer was formed on the first barrier layer. 4MP was deposited as a second barrier layer. For this purpose, 4MP was prepared as an organic precursor and argon was prepared as a persing gas. The pressure of the organic precursor dosing step was 200 mTorr for 20 seconds and the purging step lasted 60 seconds. The pressure in each step was 100 degrees. This deposited an organic barrier layer.

Thus, a multi-level device according to the second embodiment of the present invention was manufactured.

Referring to FIG. 25, it can be seen that the current between the source and drain electrodes increases when a gate voltage of -1.5 to 4 volts is applied to the gate electrode. That is, -1.5 to 4 volts can be understood as the first gate voltage range R1. As described above, it is interpreted that current is transferred by turning on the first active layer while the second active layer is turned off.

Also, it was confirmed that the amount of current between the source and drain electrodes did not change when a gate voltage of 4 to 7 volts was applied to the gate electrode. That is, 4-7 volts can be understood as the second gate voltage range R2. It is interpreted that this is because the first active layer is saturated while the second active layer is still in the turn-off state in the gate voltage range of 4-7 volts. In the gate voltage range of 4 to 7 volts, the gate field reaching the second active layer is blocked by the barrier layer and the first active layer so that the second active layer is not turned on. That is, current saturation occurs due to the quantized energy level in at least one axis of the active layer, and the second gate voltage range R2 may be generated by the current saturation.

Also, it was confirmed that the current between the source and drain electrodes increased again when a gate voltage of 7 V or more was applied to the gate electrode. That is, a gate voltage above 7 volts can be understood as a third gate voltage range R3. This translates to the gate voltage passing through the first active layer and the barrier layer to reach the second active layer at voltages above 7 volts.

FIG. 26 illustrates a multi-level device according to a second embodiment of the invention.

Referring to FIG. 26, a multi-level device 300b according to the second embodiment of the present invention includes a substrate, a gate electrode 120, a gate insulating layer 125, a first active layer 144a, a barrier layer 134, a second active layer 144b, and a source electrode. 160 and drain electrode 162 .

As shown, the device according to the second embodiment may have a structure in which a first active layer 144a, a barrier layer 134, and a second active layer 144b are sequentially stacked with the gate electrode 120 as a reference.

The source and drain electrodes 160, 162 may be in electrical contact with the second active layer 144b. In other words, the source and drain electrodes 160, 162 can be in electrical non-contact with the first active layer 144a and the barrier layer 134a.

As illustrated on the right side of FIG. 26, the first active layer 144a can include WS2TMDC, the second barrier layer 134 can include 4MP, and the second active layer 144b can include WS2TMDC.

That is, the multilevel device according to the second embodiment of the present invention can be based on the device according to the third embodiment of the present invention.

FIG. 27 is a flowchart for explaining a method of manufacturing a multilevel device according to the second embodiment of the present invention.

Referring to FIG. 27, a method of manufacturing a multi-level device according to a second embodiment of the present invention includes steps of forming a gate electrode and a gate insulating layer on one side of the gate electrode (S410); depositing a first active layer including a first TMDC on one side (S420); depositing a barrier layer on one side of the first active layer (S430); At least one step of depositing an active layer (S440) and forming source and drain electrodes on one side of the second active layer (S450) may be included.

Since steps S410 and S450 correspond to the manufacturing method of the multi-level device according to the first embodiment, detailed description thereof will be omitted. Since steps S420 and S440 correspond to those described with reference to FIG. 20, detailed description thereof will be omitted. Since step S430 corresponds to step S330 described with reference to FIG. 23, a detailed description thereof will be omitted.

Subsequently, the multi-level conductivity characteristics according to the second embodiment of the present invention will be explained. It was confirmed that the multilevel device manufactured under the conditions described with reference to FIG. 27 has multilevel conductivity on the IV curve, as shown in FIG.

Referring to FIG. 28, it can be seen that the current between the source and drain electrodes increases when a gate voltage of 4 to -19 volts is applied to the gate electrode. That is, 4 to -19 volts can be understood as the first gate voltage range R1. As described above, it is interpreted that current is transferred by turning on the first active layer while the second active layer is turned off.

In addition, it can be seen that the amount of current between the source and drain electrodes does not change when a gate voltage of -19 to -22 volts is applied to the gate electrode. That is, -19 to -22 volts can be understood as the second gate voltage range R2. It is interpreted that this is because the first active layer is saturated while the second active layer is still in the turn-off state in the gate voltage range of -19 to -22 volts. It is interpreted that the gate field reaching the second active layer is shielded by the barrier layer and the first active layer in the gate voltage range of -19 to -22 volts, and the second active layer is not turned on. That is, current saturation occurs due to the quantized energy level in at least one axis of the active layer, and the second gate voltage range R2 may be generated by the current saturation.

It was also confirmed that the current between the source and drain electrodes increased again when a gate voltage of -22 V or higher was applied to the gate electrode. That is, a gate voltage above -22 volts can be understood as a third gate voltage range R3. This translates to the gate voltage passing through the first active layer and the barrier layer to reach the second active layer at voltages above -22 volts.

The multi-level device according to the second embodiment of the present invention has been described above.

Hereinafter, the superiority of the process according to the embodiment of the present invention will be described. First, the superiority of the pressure dosing stage will be described.

FIG. 29 measures the surface coverage while increasing the chamber pressure with the metal precursor source gas while performing the pressure dosing step described with reference to FIG. 7 using tungsten hexafluoride gas as the source gas. This is the result of

Referring to FIG. 29, when the pressure is increased from 5 mTorr to 10 mTorr, 20 mTorr, 50 mTorr, 100 mTorr, 200 mTorr, 300 mTorr, 1000 mTorr, 2000 mTorr, 3000 mTorr, the surface coverage is 61%, 62.5%, 62, 65%, respectively. , 66.5%, 69.5%, 91.5%, 96.5%, 97.5%, and 99%.

That is, when the source gas dosing pressure was as low as 0.2 mTorr, the surface coverage was as low as about 70%. However, when the dosing pressure of the source gas was increased above 0.3 Torr, the surface coverage was found to be significantly better at about 90%.

Accordingly, it can be confirmed that the minimum pressure of the source gas pressurized dosing step is preferably 0.3 Torr or more.

As described above, when the pressure inside the chamber is increased by supplying the source gas while the chamber is closed, the adsorption rate of the source gas on the surface of the object increases significantly. Therefore, excellent film quality can be provided by pressure dosing according to an embodiment of the present invention.

A pressure dosing step can be applied to a device according to an embodiment of the invention and to a multi-level device according to an embodiment of the invention.

The WS2 characteristics of the device according to the third embodiment and the multi-level device according to the second embodiment will now be described.

As shown in FIGS. 30 and 31, XPS analysis was performed on WS2 of the device according to the third embodiment of the present invention and the multi-level device according to the second embodiment. The manufacturing process is the same as that described with reference to FIG.

Compared to the XPS peaks of tungsten, which is a transition metal (FIGS. 30(a) and 31(a)), WS2 produced according to an embodiment of the present invention clearly shows a peak due to S in addition to a peak due to W. was made (FIGS. 30(b) and 31(b)). Through this, it can be confirmed that WS2 was deposited.

Next, as shown in FIG. 32, Raman shift analysis was performed on WS2 manufactured according to an embodiment of the present invention.

As a result of the analysis, it was confirmed that the intensity ratio (I _2LA /IA _1g ) was 2.4 and the frequency difference (cm ⁻¹ ) between E _2g and A _1g was 62.5 (FIG. 32(b)). Based on the analysis results, it can be confirmed that the WS2 manufactured according to one embodiment of the present invention is a monolayer.

Next, as shown in FIG. 33, AFM analysis was performed on WS2 manufactured according to one embodiment of the present invention.

When tungsten, which is a transition metal, was deposited on a silicon substrate, a thickness deviation of 0.379 nm occurred (FIG. 33(a)). In this case, a thickness deviation of 0.736 nm occurred (FIG. 33(b)). A thickness deviation of 0.736 nm confirms that the WS2 fabricated according to one embodiment is a monolayer.

This confirms that the multi-level device manufactured according to one embodiment of the present invention has a monolayer TMDC active layer with high coverage.

Although the present invention has been described in detail using preferred embodiments, the scope of the invention should not be limited to the specific embodiments, but should be construed by the appended claims. It should also be understood by those skilled in the art that various modifications and variations can be made without departing from the scope of the present invention.

Claims (20)

at least one active monolayer having quantized energy levels along at least one axis; and at least one barrier stacked alternately with said at least one active monolayer;
a current flows through the active monolayer, the quantized energy level limiting current flow ;
The membrane structure , wherein the barrier includes at least one of an organic material and an organic-inorganic composite . 2. The membrane structure of claim 1, wherein said active monolayer and said barrier have a hybrid superlattice structure. 2. The membrane structure of claim 1, wherein said active monolayer has a two-dimensional layered structure. 2. The membrane structure of claim 1, wherein the stack of active monolayers and barriers provides a quantum well structure. 2. The film structure of claim 1, wherein the active monolayer has quantized energy levels along the minor axis when the active monolayer consists of metal monoatoms or TMDCs (Transitionmetal dichalcogenide). 2. The film structure of claim 1, wherein when the active monolayer comprises a metal oxide, the active monolayer has three axially quantized energy levels. 2. The membrane structure of claim 1, wherein the quantized energy level limits current flow even as the strength of the field applied to the active monolayer increases. a gate electrode, a gate insulating film on one side of the gate electrode, at least one active monolayer provided on one side of the gate insulating film;
at least one layer of barriers alternately stacked with the at least one active monolayer; and a source electrode and a drain electrode through which a current flows through the active monolayer when a gate voltage is applied to the gate electrode. ,
The device , wherein the barrier includes at least one of an organic material and an organic-inorganic composite . 9. The device of Claim 8, wherein the active monolayer has a quantized energy level in at least one axis. 10. The device of claim 9, wherein said quantized energy level limits the amount of current flowing through said active monolayer at said gate voltage above turn on voltage. 9. The device of claim 8, wherein when the active monolayer comprises at least one of metal monatoms and TMDC, the active monolayer has quantized energy levels in the minor axis direction. 9. The device of claim 8, wherein when the active monolayer comprises a metal oxide, the active monolayer has three axially quantized energy levels. 9. The device of claim 8, wherein said active monolayer comprises a plurality of crystalline regions and amorphous regions surrounding said crystalline regions. 14. The device of claim 13, wherein the active monolayer has three axially quantized energy levels. 9. The device of claim 8, wherein the barrier is laminated between the active monolayer and the source and drain electrodes . 9. The device of claim 8, wherein said active monolayer has a structure sandwiched between said barriers. 9. The device of claim 8, wherein said active monolayer has a predetermined thickness, said predetermined thickness being nano-sized. 9. The device of claim 8, wherein a gate voltage applied to said gate electrode controls the number of activated active monolayers of said at least one active monolayer . 9. The device of claim 8, wherein said source electrode and said drain electrode are in electrical contact only with one active monolayer of said at least one active monolayer . The gate voltage range applied to the gate electrode is divided into a first gate voltage range , a second gate voltage range and a third gate voltage range. 9. The device of claim 8, wherein a gate voltage range is provided.

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