JP7199913B2 - switching power supply - Google Patents

Description

The invention disclosed herein relates to switching power supplies.

2. Description of the Related Art Conventionally, switching power supplies that generate a desired output voltage from an input voltage have been put into practical use as power supply means for various applications.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

Japanese Patent Application Laid-Open No. 2014-233110

However, in a critical mode switching power supply that sets the on-timing of the output transistor by detecting that the coil current has decreased to a zero value or a value close to it, a ground fault (= ground terminal or a low potential equivalent to this) is applied to the current detection terminal. short-to-end), it erroneously detects that the coil current is always at zero value and immediately turns on the output transistor that was just turned off. Therefore, the OFF period of the output transistor is almost eliminated, and electrical energy (=current) that cannot be discharged accumulates in the coil. Accumulation of excessive electrical energy in the coil leads to heat generation and destruction of the output transistor.

Also, in a step-up type switching power supply, there is a risk of excessive step-up at the time of starting (especially at the time of starting in a light load state or no load state).

The invention disclosed in the present specification provides a switching power supply capable of preventing heat generation and destruction of an output transistor when a current detection terminal is grounded in view of the above problem found by the inventor of the present application. The first purpose is to

A second object of the invention disclosed in the present specification is to provide a switching power supply capable of suppressing excessive boosting at startup in view of the above-described problem found by the inventors of the present application. and

In order to achieve the first object, the controller IC disclosed in this specification includes a current detection terminal for detecting coil current flowing in the switching power supply; In normal operation, the output transistor is turned on when the coil current decreases to a zero value or a value close to it, and in the case of a ground fault, the output transistor is turned on after a predetermined minimum off period has elapsed. and an on-timing setting unit that generates a timing setting signal (first configuration).

In the controller IC having the first configuration, the on-timing setting unit compares the terminal voltage of the current detection terminal or a voltage corresponding thereto with a predetermined threshold voltage to generate a zero current detection signal. a zero current detection unit; a timer that counts the minimum off period after the output transistor is turned off to generate a timer output signal; a selector that outputs one of the output signals as the on-timing setting signal (second configuration).

Further, in the controller IC having the second configuration, the selector includes a D flip-flop that latches the zero current detection signal when the output transistor is off, and the zero current detection signal is detected according to the latch output signal of the D flip-flop. A configuration (third configuration) in which either one of the current detection signal or its delayed signal and the timer output signal is selected may be employed.

Further, in the controller IC having the second or third configuration, the on-timing setting section includes a signal delay section that generates a delayed signal of the zero current detection signal and outputs it to the selector (fourth configuration). configuration).

In the controller IC having the fourth configuration, the signal delay unit includes a capacitor, a current source that generates a charging current for the capacitor, and a discharge switch that discharges the capacitor in response to the zero current detection signal. , and an inverter for generating the delay signal from the charged voltage of the capacitor (fifth configuration).

In the controller IC having any one of the second to fifth configurations, the timer includes a capacitor, a current source that generates a charging current for the capacitor, and a discharger that discharges the capacitor during an ON period of the output transistor. A configuration (sixth configuration) that includes a switch and a buffer that generates the timer output signal from the charged voltage of the capacitor is preferable.

Further, in the controller IC having any one of the second to sixth configurations, the zero current detection unit is connected between a reference voltage application terminal and the current detection terminal, and the terminal voltage of the current detection terminal is to the reference voltage side, and a first resistor voltage dividing unit connected between the reference voltage application terminal and the ground terminal to divide the reference voltage and divide the threshold voltage A configuration (seventh configuration) that includes a second resistor voltage dividing unit that generates a voltage and a comparator that compares the divided terminal voltage and the threshold voltage to generate the zero current detection signal is preferable.

The controller IC having any one of the first to seventh configurations includes an error amplifier for generating an error voltage corresponding to the difference between the output voltage of the switching power supply or its divided voltage and a predetermined reference voltage, and a lamp. an oscillator that generates a voltage; a main comparator that compares the error voltage and the ramp voltage to generate an off-timing setting signal; and a switching control signal based on the on-timing setting signal and the off-timing setting signal. A configuration (eighth configuration) having an RS flip-flop and a driver for driving the output transistor according to the switching control signal is preferable.

Further, the switching power supply disclosed in this specification includes a switch output stage that generates an output voltage from an input voltage using the output transistor, and any one of the first to eighth controller ICs. (9th configuration).

The switching power supply having the ninth configuration may be configured to function as a power factor correction circuit (tenth configuration).

Further, in order to achieve the second object, the controller IC disclosed in the present specification is a control entity of an output transistor included in a step-up switching power supply, and the output transistor is controlled during activation of the switching power supply. A configuration (an eleventh configuration) is provided that includes an over-boost suppression unit that forcibly lowers the on-duty of the transistor.

The controller IC having the eleventh configuration includes: an error amplifier for generating an error voltage corresponding to the difference between the output voltage of the switching power supply or the feedback voltage corresponding thereto and a predetermined reference voltage; a main comparator for comparing the output voltage with the ramp voltage and generating a pulse width modulation signal for setting the off timing of the output transistor, wherein the over-boost suppressing unit reduces the output voltage or A configuration (twelfth configuration) may be employed in which forced discharge of the error voltage is started when the feedback voltage exceeds the discharge start voltage.

Further, in the controller IC having the twelfth configuration, the over-voltage suppression unit is configured to stop the forced discharge of the error voltage when the error voltage falls below the discharge stop voltage (the thirteenth configuration). good.

Further, in the controller IC having the twelfth or thirteenth configuration, the over-boost suppressing section stops forcibly discharging the error voltage when the pulse width modulation signal is fixed at the off logic level. (14th configuration).

In the controller IC having any one of the twelfth to fourteenth configurations, the error amplifier is a differential input stage that generates a current control signal corresponding to the difference between the output voltage or the feedback voltage and the reference voltage. a current output stage that generates a source current that flows into the output terminal of the error voltage or a sink current that is drawn from the output terminal of the error voltage according to the current control signal; and an auxiliary source current generator that generates an auxiliary source current when the voltage is below a first threshold voltage lower than the voltage (a fifteenth configuration).

Further, in the controller IC having the fifteenth configuration, the discharge start voltage may be the same value as the first threshold voltage (sixteenth configuration).

In the controller IC having the fifteenth or sixteenth configuration, the error amplifier generates an auxiliary sink current when the output voltage or the feedback voltage exceeds a second threshold voltage higher than the reference voltage. A configuration (seventeenth configuration) that further includes an auxiliary sink current generator that

Further, the controller IC disclosed in this specification is a control entity of an output transistor included in a step-up type switching power supply, and controls an output voltage of the switching power supply or a feedback voltage corresponding thereto and a predetermined reference voltage. a main comparator that compares the error voltage and the ramp voltage to generate a pulse width modulated signal for setting the off timing of the output transistor; and the switching an over-boost suppressing unit that forcibly lowers the gain of the error amplifier from that in a steady state until the output voltage or the feedback voltage exceeds a predetermined threshold voltage lower than the reference voltage only when the power supply is started. configuration (18th configuration).

Further, the switching power supply disclosed in this specification includes: a switch output stage for generating an output voltage from an input voltage using the output transistor; a controller IC having any one of the eleventh to eighteenth configurations; (19th configuration).

The switching power supply having the nineteenth configuration may be configured to function as a power factor correction circuit (twentieth configuration).

According to the invention disclosed in this specification, it is possible to provide a switching power supply capable of preventing heat generation and destruction of an output transistor when a current detection terminal is grounded.

Further, according to the invention disclosed in this specification, it is possible to provide a switching power supply capable of suppressing excessive boosting at startup.

Diagram showing the overall configuration of a switching power supply FIG. 4 is a diagram showing a configuration example of a controller IC; FIG. 11 is a diagram showing a configuration example of an on-timing setting unit; Timing chart showing minimum OFF period setting operation when IS-GND is shorted State machine diagram showing operation state transition of switching power supply Diagram showing behavior when IS-GND is shorted (minimum OFF period setting function: not introduced) Diagram showing behavior when IS-GND is shorted (minimum OFF period setting function: already introduced) FIG. 2 shows the first embodiment of the error amplifier; Timing chart showing an example of error voltage discharge operation Diagram showing output behavior at startup (error voltage discharge function: not introduced) Diagram showing output behavior at startup (error voltage discharge function: already introduced) The figure which shows 2nd Embodiment of an error amplifier

<Switching power supply>
FIG. 1 is a diagram showing the overall configuration of a switching power supply. The switching power supply 1 of this configuration example is a power conversion device (so-called AC/DC converter) that converts an AC input voltage Vi (for example, AC 85 to 265 V) into a desired DC output voltage Vo (for example, DC 400 V). It has various discrete components external to it (output transistor N1, resistors R1-R10, capacitors C1-C10 diodes D1 and D2, coil L1, fuse F1, filter FLT, and diode bridge DB).

The fuse F1 is connected between the application terminal of the AC input voltage Vi and the input terminal of the filter FLT, and is fused to protect the switching power supply 1 when an excessive current flows. The capacitor C1 is connected between the input terminals of the AC input voltage Vi and removes harmonic noise of the AC input voltage Vi. Filter FLT removes noise and surge from AC input voltage Vi. A diode bridge DB generates a full-wave rectified voltage Vrec (eg, 120-375 V DC) from the filtered AC input voltage Vi. A capacitor C2 is connected across the output terminals of the diode bridge DB and smoothes the full-wave rectified voltage Vi.

The controller IC 100 is a semiconductor integrated circuit device that mainly controls the switching power supply 1, and has eight external terminals (pins 1 to 8) as means for establishing electrical connection with the outside of the device. there is Of course, the controller IC 100 may be provided with external terminals other than these.

An output feedback terminal VS (pin 1) is connected to a connection node between resistors R3 and R4 connected in series between the output terminal of the DC output voltage Vo and the ground terminal. The resistors R3 and R4 function as a resistor voltage dividing unit that outputs a divided voltage (=Vo×{R4/(R3+R4)} of the DC output voltage Vo from a connection node therebetween. A smoothing capacitor C4 is connected between and the ground terminal.

A phase compensation terminal EO (pin 2) is connected to first ends of the capacitor C5 and the resistor R6. A second end of resistor R6 is connected to a first end of capacitor C6. Second ends of the capacitors C5 and C6 are both connected to ground. Capacitors C5 and C6 and resistor R6 connected in this manner function as phase compensation means for the error amplifier integrated in the controller IC100.

An oscillation control terminal RT (pin 3) is connected to first ends of the resistor R7 and the capacitor C7. Second ends of the resistor R7 and the capacitor C7 are both connected to the ground end. The resistor R7 and capacitor C7 function as frequency adjustment means for the oscillator integrated in the controller IC100.

An overvoltage detection terminal OVP (pin 4) is connected to a connection node between resistors R1 and R2 connected in series between the output terminal of the DC output voltage Vo and the ground terminal. The resistors R1 and R2 function as a resistor voltage dividing unit that outputs a divided voltage (=Vo×R2/(R1+R2)) of the DC output voltage Vo from a connection node therebetween. A smoothing capacitor C8 is connected between the overvoltage detection terminal OVP and the ground terminal. In this way, if the overvoltage detection terminal OVP is provided separately from the output feedback terminal VS, the overvoltage detection function will not be impaired even if an open abnormality or a short abnormality occurs in one side, so that safety can be improved. can.

A current detection terminal IS (pin 5) is an external terminal for detecting the coil current IL flowing in the switching power supply 1, and the negative output terminal of the diode bridge DB (=the first terminal of the resistor R5) via the resistor R8. It is connected to the. A second end of the resistor R5 is connected to the ground terminal. That is, the sense voltage (=IL×R3) corresponding to the coil current IL (<0) flowing from the ground end to the negative output end of the diode bridge DB via the resistor R5 is applied to the current detection terminal IS. A smoothing capacitor C9 is connected between the current detection terminal IS and the ground terminal.

A ground terminal GND (pin 6) is connected to the ground terminal.

The output terminal OUT (pin 7) is connected to the gate of an output transistor N1 (NMOSFET [N-channel type metal oxide semiconductor field effect transistor] in this figure) via a resistor R9. A resistor R10 is connected between the gate and source of the output transistor N1. The source and backgate of the output transistor N1 are connected to the ground terminal. A first end of the coil L1 is connected to the positive output end of the diode bridge DB (=corresponding to the output end of the full-wave rectified voltage Vrec) and the anode of the diode D2. A second end of the coil L1 is connected to the drain of the output transistor N1 and the anode of the diode D1. The cathodes of the diodes D1 and D2 and the first terminal of the capacitor C3 are both connected to the output terminal of the DC output voltage Vo. A second end of the capacitor C3 is connected to the ground end.

The output transistor N1, the coil L1, the diodes D1 and D2, and the capacitor C3 connected in this way function as a step-up switch output stage that generates the DC output voltage Vo from the full-wave rectified voltage Vrec. The output transistor N1 is on/off controlled according to a gate signal G1 provided from the output terminal OUT of the controller IC100. More specifically, the output transistor N1 turns on when the gate signal G1 is at high level, and turns off when the gate signal G1 is at low level.

A brief description will be given of the step-up operation of the switch output stage. When the output transistor N1 is turned on, a coil current IL flows through the coil L1 toward the ground end via the output transistor N1, and its electrical energy is stored. At this time, the switch voltage Vsw appearing at the anode of the diode D1 drops to approximately the ground potential through the output transistor N1. Therefore, since the diode D1 is reverse biased, no current flows from the capacitor C3 to the output transistor N1.

On the other hand, when the output transistor N1 is turned off, the back electromotive force generated in the coil L1 causes the electrical energy stored therein to be released as current. At this time, since the diode D1 is forward-biased, the coil current IL flowing through the diode D1 flows as the DC output current Io from the output end of the DC output voltage Vo into the load (not shown) and also through the capacitor C3. , and also flows into the ground terminal to charge the capacitor C3.

By repeating the above operation, the switch output stage generates a DC output voltage Vo by boosting the full-wave rectified voltage Vrec.

Further, the switching power supply 1 of this configuration example makes the envelope waveform of the drain current Id that flows when the output transistor N1 is turned on resemble the voltage waveform of the full-wave rectified voltage Vrec (and the voltage waveform of the AC input voltage Vi). Thus, it functions as a power factor correction circuit (so-called PFC [power factor correction] circuit) that brings the power factor closer to 1.

A power supply terminal VCC (pin 8) is connected to an application terminal of a power supply voltage Vcc (eg, 10 to 26 V). A smoothing capacitor C10 is connected between the power supply terminal VCC and the ground terminal.

<Controller IC>
FIG. 2 is a diagram showing a configuration example of the controller IC 100. As shown in FIG. The controller IC 100 of this configuration example includes an error amplifier 101, a comparator 102 for GUP [gain-up], a comparator 103 for DOVP [dynamic over voltage protection], a comparator 104 for SP [short protection], and an SOVP Comparator 105 for [static OVP], NMOSFET 106, main comparator 107, oscillator 108, comparator 109 for RT_H detection, comparator 110 for RT_L detection, and comparator 111 for ISOCP [IS over current protection] , zero current detector 112, signal delay unit 113, timer 114, selector 115, OR gate 116, RS flip-flop 117, AND gate 118, pre-driver 119, clamper 120, PMOSFET [P -channel type MOSFET] 121, NMOSFET 122, resistor 123, comparator 124 for OVP, inverter 125, Zener diode 126, comparator 127 for UVLO [under voltage locked-out], and reference voltage source 128. , a reference voltage buffer 129, a regulator 130, and a temperature protection unit 131 are integrated.

The error amplifier 101 has a feedback voltage Vfb (=the terminal voltage of the output feedback terminal VS) input to the inverting input terminal (-) and a predetermined reference voltage Vref (for example, 2.0) input to the non-inverting input terminal (+). 5V) is generated. Specifically, the error amplifier 101 lowers the error voltage Veo when the feedback voltage Vfb is higher than the reference voltage Vref, and raises the error voltage Veo when the feedback voltage Vfb is lower than the reference voltage Vref. The output end of the error amplifier 101 (=the output end of the error voltage Veo) is connected to the phase compensation terminal EO. Also, the error amplifier 101 has a source current capability (=ability to flow current into the phase compensation terminal EO) and a sink current capability (=capability to flow current from the phase compensation terminal EO) according to both the gain-up signal GUP and the overvoltage protection signal DOVP. ability to pull out).

The comparator 102 compares the feedback voltage Vfb input to the non-inverting input terminal (+) and the GUP threshold voltage Vth102 (eg Vref×0.9) input to the inverting input terminal (-) to determine the gain. Generate an up signal GUP. The gain-up signal GUP becomes high level (=logical level when the source current is stationary) when Vfb>Vth102, and becomes low level (=logical level when the source current is increased) when Vfb<Vth102.

The comparator 103 compares the feedback voltage Vfb input to the non-inverting input terminal (+) and the DOVP threshold voltage Vth103 (for example, Vref×1.05) input to the inverting input terminal (-) to detect an overvoltage. Generate a protection signal DOVP. The overvoltage protection signal DOVP becomes high level (=logical level when the sink current is increased) when Vfb>Vth103, and becomes low level (=logical level when the sink current is stationary) when Vfb<Vth103.

The comparator 104 compares the feedback voltage Vfb input to the non-inverting input terminal (+) and the SP threshold voltage Vth104 (for example, 0.3 V) input to the inverting input terminal (-) to generate a short protection signal. Generate SP. The short protection signal SP becomes high level (=normal logic level) when Vfb>Vth104, and becomes low level (=abnormal logic level) when Vfb<Vth104.

The comparator 105 compares the feedback voltage Vfb input to the non-inverting input terminal (+) and the SOVP threshold voltage Vth105 (for example, Vref×1.08) input to the inverting input terminal (-) to detect an overvoltage. Generate a protection signal SOVP. The overvoltage protection signal SOVP becomes high level (=abnormal logic level) when Vfb>Vth105, and becomes low level (=normal logic level) when Vfb<Vth105.

The NMOSFET 106 is a switch element for pulling down the error voltage Veo during UVLO operation. Regarding the connection relationship, the drain of the NMOSFET 106 is connected to the phase compensation terminal EO (=the output terminal of the error amplifier 101). The source and backgate of NMOSFET 106 are connected to ground. The gate of the NMOSFET 106 is connected to the application end of the inverted low-voltage protection signal UVLOB (=logically inverted signal of the low-voltage protection signal UVLO). Therefore, the NMOSFET 106 is turned on when the inverted low voltage protection signal UVLOB is at high level (=logic level when UVLO is activated), and the inverted low voltage protection signal UVLOB is at low level (=logic level when UVLO is released). turn off at times.

The main comparator 107 compares the error voltage Veo input to the inverting input terminal (-) and the ramp voltage Vramp input to the non-inverting input terminal (+) to generate a pulse width modulated signal PWM. The pulse width modulation signal PWM becomes low level when the error voltage Veo is higher than the ramp voltage Vramp, and becomes high level when the error voltage Veo is lower than the ramp voltage Vramp.

The oscillator 108 generates a ramp voltage Vramp having a slope waveform (triangular wave, sawtooth wave, n-order RC wave, etc.) at a predetermined oscillation frequency fosc in synchronization with the switching control signal Sctrl. The oscillation frequency fosc can be arbitrarily adjusted according to the resistance and capacitance values of the resistor R7 and capacitor C7 (see FIG. 1) externally attached to the oscillation control terminal RT.

The comparator 109 has an RT terminal voltage Vrt (=the terminal voltage of the oscillation control terminal RT) input to the non-inverting input terminal (+) and an upper limit detection threshold voltage Vth109 (for example, 1.65V) to generate the upper limit detection signal RT_H. The upper limit detection signal RT_H becomes high level (=abnormal logic level) when Vrt>Vth109, and becomes low level (=normal logic level) when Vrt<Vth109.

The comparator 110 compares the RT terminal voltage Vrt input to the inverting input terminal (-) and the threshold voltage Vth110 (for example, 0.15 V) for detecting the lower limit input to the non-inverting input terminal (+) to determine the lower limit. A detection signal RT_L is generated. The lower limit detection signal RT_L becomes low level (=normal logic level) when Vrt>Vth110, and becomes high level (=abnormal logic level) when Vrt<Vth110. The lower limit detection signal RT_L is used as an enable signal EN for the oscillator 108 .

The comparator 111 compares the current detection voltage Vis (=the terminal voltage of the current detection terminal IS) input to the inverting input terminal (-) with the ISOCP threshold voltage Vth111 input to the non-inverting input terminal (+). to generate the overcurrent protection signal ISOCP. The current detection voltage Vis becomes a negative voltage value (<0 V) when the coil current IL is flowing, and becomes a zero value (=0 V) when the coil current IL stops flowing. Therefore, the threshold voltage Vth111 should be set to a negative voltage value (eg, −0.6 V) corresponding to the upper limit value IL_H of the coil current IL. The overcurrent protection signal ISOCP becomes low level (=normal logic level) when Vis>Vth111, and becomes high level (=abnormal logic level) when Vis<Vth111.

The zero current detection unit 112 compares the current detection voltage Vis input to the non-inverting input terminal (+) and the threshold voltage Vth112 for ZCD input to the inverting input terminal (-) to generate a zero current detection signal. Generate ZCD [zero current detection]. As described above, the current detection voltage Vis becomes a negative voltage value (<0 V) when the coil current IL is flowing, and becomes a zero value (=0 V) when the coil current IL stops flowing. Become. Therefore, the threshold voltage Vth112 should be set to a negative voltage value slightly lower than 0V (eg, -10 mV). Note that the zero current detection signal ZCD becomes low level (=logic level when zero current is not detected) when Vis<Vth112, and becomes high level (=logic level when zero current is detected) when Vis>Vth112. Become.

The signal delay unit 113 delays the zero current detection signal ZCD by a predetermined delay time Tdelay (for example, 0.6 to 2.0 μs) to generate the delayed zero current detection signal DLYO (=delayed signal of the zero current detection signal ZCD). Generate.

The timer 114 counts a predetermined minimum off period Tmin_off (eg, 30 μs) after the output transistor N1 is turned off (NO=H) to generate a timer output signal TMRO. As the timer 114, it is possible to use a restart timer for counting the waiting time from the release of UVLO to the start of switching.

Selector 115 performs ground fault detection of current detection terminal IS when output transistor N1 is off, and turns on either zero current detection signal ZCD (or its delayed signal) or timer output signal TMRO according to the detection result. Output as a setting signal SET.

The OR gate 116 generates the off-timing setting signal RST by ORing the pulse width modulation signal PWM and the overcurrent detection signal ISOCP. Therefore, when ISOCP=L (=normal logic level), RST=PWM, and when ISOCP=H (=abnormal logic level), RST=H is fixed.

The RS flip-flop 117 generates the switching control signal Sctrl according to the on-timing setting signal SET input to the set terminal (S) and the off-timing setting signal RST input to the reset terminal (R). Specifically, the RS flip-flop 117 sets the switching control signal Sctrl to a high level (=the logic level when turning on the output transistor N1) at the rising timing of the on-timing setting signal SET, and the off-timing setting signal RST. , the switching control signal Sctrl is reset to low level (=logical level when turning off the output transistor N1).

The AND gate 118 performs switching control by AND operation of the switching control signal Sctrl and various protection signals (UVLO, SP, SOVPB (=logically inverted signal of SOVP), TSD, OVPB, RT_HB (=logically inverted signal of RT_H)). Generate signal Sctrl2. Therefore, Sctrl2=Sctrl when all of the various protection signals are at high level (=logical level at normal time), and Sctrl2=L fixed when at least one of the various protection signals is at low level (=logical level at abnormal time). becomes.

The pre-driver 119 generates gate signals PO and NO according to the switching control signal Sctrl2 input from the AND gate 118 . More specifically, the pre-driver 119 basically sets both the gate signals PO and NO to low level when the switching control signal Sctrl2 is high level in order to complementarily turn on/off the PMOSFET 121 and NMOSFET 122. Both the gate signals PO and NO are set to high level when the switching control signal Sctrl2 is at low level.

However, in order to prevent an excessive through-current from flowing through the PMOSFET 121 and the NMOSFET 122, the simultaneous off time (so-called dead time) in which the gate signal PO is at a high level and the gate signal NO is at a low level is set at the timing of switching the respective on/off states. is provided.

The clamper 120 limits the power supply voltage applied to the source of the PMOSFET 121 (and the high level of the gate signal G1) to a predetermined value or less.

PMOSFET 121 and NMOSFET 122 function as a half-bridge output stage to generate gate signal G1 for output transistor N1. Both the source and the back gate of the PMOSFET 121 are connected to the power terminal via the clamper 120 . The drains of the PMOSFET 121 and NMOSFET 122 are connected to the output terminal OUT as the output terminal of the gate signal G1. The source and backgate of NMOSFET 122 are both connected to ground. A resistor 123 is connected between the drain and source of the NMOSFET 122 .

A gate signal PO is input from the predriver 119 to the gate of the PMOSFET 121 . Therefore, the PMOSFET 121 is turned off when the gate signal PO is at high level, and turned off when the gate signal PO is at low level.

On the other hand, the gate signal NO from the pre-driver 119 is input to the gate of the NMOSFET 122 . Therefore, the NMOSFET 122 turns on when the gate signal NO is at high level and turns off when the gate signal NO is at low level.

The comparator 124 has a divided voltage Vdet (=the terminal voltage of the overvoltage detection terminal OVP) input to the non-inverting input terminal (+) and a threshold voltage Vth124 for OVP input to the inverting input terminal (-) (for example, Vref ×1.08) to generate the overvoltage protection signal OVP. The overvoltage protection signal OVP becomes high level (=abnormal logic level) when Vfb>Vth124, and becomes low level (=normal logic level) when Vfb<Vth124. In this way, by monitoring both the feedback voltage Vfb and the divided voltage Vdet using the comparators 105 and 124, double overvoltage protection can be applied, so that the safety of the switching power supply 1 can be improved. It becomes possible.

Inverter 125 logically inverts overvoltage protection signal OVP to generate inverted overvoltage protection signal OVPB. Therefore, the inverted overvoltage protection signal OVPB is at low level (=abnormal logic level) when the overvoltage protection signal OVP is at high level, and at high level (=normal logic level) when the overvoltage protection signal OVP is at low level. logical level).

Zener diode 126 is an electrostatic breakdown protection element for power supply terminal VCC. Regarding the connection relationship, the Zener diode 126 has a cathode connected to the power supply terminal VCC and an anode connected to the ground terminal.

The comparator 127 has a power supply voltage Vcc (=the terminal voltage of the power supply terminal VCC) input to the non-inverting input terminal (+) and a UVLO threshold voltage Vth127 (eg, 12.0 V) input to the inverting input terminal (-). /9.0V) to generate a low voltage protection signal UVLO. The low voltage protection signal UVLO becomes high level (=normal logic level) when Vcc>Vth127, and becomes low level (=abnormal logic level) when Vcc<Vth127.

A reference voltage source 128 generates a predetermined reference voltage Vbg (eg, 18.0 V) from the power supply voltage Vcc. As the reference voltage source 128, for example, a bandgap power supply with low power supply dependency and temperature dependency can be preferably used.

The reference voltage buffer 129 receives supply of the power supply voltage Vcc to operate, buffers the reference voltage Vbg input from the reference voltage source 128 and outputs it to each part of the controller IC 100 .

Regulator 130 generates a predetermined internal power supply voltage Vreg (eg, 4.0 V) from power supply voltage Vcc.

The temperature protection unit 131 compares the junction temperature Tj of the controller IC 100 with the threshold temperature Tth (for example, 150° C./175° C.) for TSD to generate the temperature protection signal TSD. The temperature protection signal TSD becomes low level (=abnormal logic level) when Tj>Tth, and becomes high level (=normal logic level) when Tj<Tth.

<On timing setting part>
By the way, among the components shown in FIG. 2, the zero current detection unit 112, the signal delay unit 113, the timer 114, and the selector 115 detect a ground fault at the current detection terminal IS (pin 5) when the output transistor N1 is turned off. , and the output transistor N1 is turned on when the coil current IL is reduced to a zero value or a value close to it in normal conditions, and the output transistor N1 is turned on after a predetermined minimum off period Ton_min has passed in the case of a ground fault. It functions as an on-timing setting section 200 that generates the timing setting signal SET. The configuration and operation thereof will be described in detail below.

FIG. 3 is a diagram showing a configuration example of the on-timing setting section 200. As shown in FIG. The on-timing setting unit 200 of this configuration example includes the zero current detection unit 112, the signal delay unit 113, the timer 114, and the selector 115, as described above.

The zero current detector 112 includes resistors 112a-112d, a comparator 112e, and an NMOSFET 112f.

The resistors 112a and 112b are connected in series between the application end of the reference voltage Vbg and the current detection terminal IS (=the application end of the current detection voltage Vis), and shift the current detection voltage Vis to the reference voltage Vbg side. It functions as a first resistor voltage dividing unit that generates a voltage dividing terminal voltage Vis′ (=(Rb×Vbg+Ra×Vis)/(Ra+Rb)).

The resistors 112c and 112d are connected in series between the application terminal of the reference voltage Vbg and the ground terminal, and divide the reference voltage Vbg to obtain the threshold voltage Vth112′ (=Vbg×{Rd/(Rc+Rd)}). It functions as a second resistive voltage divider to generate. Note that the threshold voltage Vth112' corresponds to a voltage obtained by level-shifting the threshold voltage Vth112 (eg, -10 mV) to the positive side by the amount of the level shift from the current detection voltage Vis to the voltage dividing terminal voltage Vis'.

The comparator 112e compares the voltage dividing terminal voltage Vis' input to the non-inverting input terminal (+) and the threshold voltage Vth112' input to the inverting input terminal (-) to generate the zero current detection signal ZCD. do. The zero current detection signal ZCD becomes low level (=logic level when zero current is not detected) when Vis'<Vth112', and becomes high level (=logic when zero current is detected) when Vis'>Vth112'. level).

The NMOSFET 112f is a switch element for pulling down the divided voltage terminal voltage Vis' when the zero current detection section 112 is disabled. Regarding the connection relationship, the drain of the NMOSFET 112f is connected to the application terminal of the voltage dividing terminal voltage Vis' (=the non-inverting input terminal (+) of the comparator 112e). The source and backgate of NMOSFET 112f are connected to the ground terminal. The NMOSFET 112f is turned on when the zero current detector 112 is disabled and turned off when the zero current detector 112 is enabled.

Note that a filter for removing noise from the current detection voltage Vis may be provided in the preceding stage of the zero current detection section 112 .

The signal delay unit 113 includes a current source 113a, a capacitor 113b, an NMOSFET 113c, and an inverter 113d.

The current source 113a is connected between the power supply end and the first end of the capacitor 113b to generate a charging current for the capacitor 113b. A second end of the capacitor 113b is connected to the ground end.

The capacitor 113b is charged by the charging current supplied from the current source 113a, and outputs the voltage across the capacitor 113b as the charging voltage Vd to the inverter 113d.

The NMOSFET 113c is connected in parallel with the capacitor 113b and functions as a discharge switch that discharges the capacitor 113b in response to the zero current detection signal ZCD. The NMOSFET 113c is turned on when ZCD=H and turned off when ZVD=L.

Inverter 113d (logic inversion level: Vth113d) generates delay zero current detection signal DLYO from charged voltage Vd of capacitor 113b. DLYO=L when Vd>Vth113d, and DLYO=H when Vd<Vth113d.

That is, in the signal delay unit 113 of this configuration example, after the zero current detection signal ZCD rises to a high level, the charging voltage Vd is very short from the start of discharging of the capacitor 113b until the charging voltage Vd falls below the logic inversion level of the inverter 113d. The rise of the zero-delayed current detection signal DLYO can be delayed by a required time (=corresponding to the delay time Tdelay). The delay time Tdelay can be arbitrarily set by adjusting the charging current value and capacitance value of the capacitor 113b.

Timer 114 includes current source 114a, capacitor 114b, NMOSFET 114c, and inverters 114d-114f.

A current source 114a is connected between the power supply end and a first end of the capacitor 114b to generate a charging current for the capacitor 114b. A second end of the capacitor 114b is connected to ground.

The capacitor 114b is charged by the charging current supplied from the current source 114a, and outputs the voltage across the capacitor 114b as the charging voltage Vt to the inverter 114d.

The NMOSFET 114c is connected in parallel to the capacitor 114b, and functions as a discharge switch that discharges the capacitor 114b according to the inverted gate signal NOB (=logically inverted signal of the gate signal NO). The NMOSFET 114c is turned on when NOB=H and turned off when NOB=L. That is, the ON period of the output transistor N1 corresponds to the discharge period of the capacitor 114b (=the reset period of the timer 114), and the OFF period of the output transistor N1 corresponds to the discharge stop period of the capacitor 114 (=the count period of the timer 114). Equivalent to.

Inverters 114d and 114e are connected in series between the first end of capacitor 114b and the output end of timer output signal TMRO, and are buffers (logic inversion level: BUFth). TMRO=H when Vt>BUFth, and TMRO=L when Vt<BUFth.

The inverter 114f logically inverts the gate signal NO to generate an inverted gate signal NOB. Therefore, when NO=H, NOB=L, and when NO=L, NOB=H.

That is, in the timer 114 of this configuration example, after the discharge of the capacitor 114b is stopped due to the turning off of the output transistor N1 (NO=H), the charging voltage Vd reaches the logic inversion level BUFth of the buffer (=inverters 114d and 114e). The timer output signal TMRO is raised to a high level when it rises to exceed the level. The time required from when the output transistor N1 is turned off to when the timer output signal TMRO rises to the high level corresponds to the minimum off period Toff_min. Note that the minimum OFF period Toff_min can be arbitrarily set by adjusting the charging current value and the capacitance value of the capacitor 114b, like the delay time Tdelay described above.

Selector 115 includes AND gates 115a and 115b, OR gate 115c, D flip-flop 115d, and inverter 115e.

The AND gate 115a generates a logical AND signal Sa of the zero delay current detection signal DLYO and the ground fault detection signal Sd. Therefore, when the ground fault detection signal Sd is at a high level (=normal logic level), Sa=DLYO, and when the ground fault detection signal Sd is at a low level (=abnormal logic level), Sa=L is fixed. Become.

AND gate 115b generates AND signal Sb of delay zero current detection signal DLYO and an inverted input signal of ground fault detection signal Sd. Therefore, when the ground fault detection signal Sd is at a low level (=logical level at the time of abnormality), Sb=TMRO, and when the ground fault detection signal Sd is at a high level (=logical level at the time of normality), Sb is fixed at L. Become.

The OR gate 115c generates a logical sum signal of both logical product signals Sa and Sb and outputs it as an on-timing setting signal SET. Therefore, the on-timing setting signal SET becomes low level when both the logical product signals Sa and Sb are low level, and becomes high level when at least one of the logical product signals Sa and Sb is high level.

The D flip-flop 115d outputs an inverted zero current detection signal ZCDB (= A logic inversion signal 9 of the zero current detection signal ZCD is latched and output from the output terminal (Q) as the ground fault detection signal Sd.

Inverter 115e logically inverts zero current detection signal ZCD to generate inverted zero current detection signal ZCDB. Therefore, when ZCD=H, ZCDB=L, and when ZCD=L, ZCDB=H.

Thus, the selector 115 selects one of the delay zero current detection signal DLYO and the timer output signal TMRO according to the latch output signal (=ground fault detection signal Sd) of the D flip-flop 115d, and turns it on. Output as a timing setting signal SET.

More specifically, when the ground fault detection signal Sd is at high level (=normal logic level), the AND gate 115a is in the signal passing state and the AND gate 115b is in the signal blocking state. Therefore, the zero-delay current detection signal DLYO is output as the on-timing setting signal SET, so that the switching control of the output transistor N1 is performed in the critical mode as before.

On the other hand, when the ground fault detection signal Sd is at a low level (=abnormal logic level), the AND gate 115a is in the signal blocking state and the AND gate 115b is in the signal passing state. Therefore, the timer output signal TMRO is output as the on-timing setting signal SET, so the setting of the minimum off period Toff_min is valid.

As described above, among the components included in the on-timing setting unit 200, the timer 114 and the selector 115, in particular, are used when the current detection terminal IS is grounded (for example, when the current detection terminal IS and the ground terminal GND are grounded). This is newly introduced as a means for setting the minimum OFF period Toff_min of the output transistor N1 when adjacent pins are short-circuited. The setting operation of the minimum OFF period Toff_min and its technical significance will be described below.

<Minimum OFF period setting operation>
FIG. 4 is a timing chart showing the minimum OFF period setting operation when IS-GND is shorted. drain-source voltage Vds (N1), coil current IL, error voltage Veo (broken line) and ramp voltage Vramp (solid line), current detection voltage Vis, zero current detection signal ZCD, ground fault detection signal Sd, charging of capacitor 114b Voltage Vt (=corresponding to the count value of timer 114) and timer output signal TMRO are depicted.

Time t1 to t2 is a high level period of the output terminal OUT (=on period of the output transistor N1), and its length varies depending on the load. More specifically, the heavier the load, the higher the error voltage Veo and the later the timing at which it intersects the ramp voltage Vramp (=the turn-off timing of the output transistor N1). Therefore, the high level period of the output terminal OUT becomes longer. Conversely, the lighter the load, the lower the error voltage Veo and the earlier the timing at which it crosses the ramp voltage Vramp. Therefore, the high level period of the output terminal OUT is shortened.

During the high level period of the output terminal OUT, the current detection voltage Vis decreases from 0V to the negative voltage side as the coil current IL increases. Also, during the high level period of the output terminal OUT, the capacitor 114b is discharged, so that Vt=0V.

At time t2, when the error voltage Veo becomes higher than the ramp voltage Vramp, the output transistor N1 is turned off. As a result, the coil current IL changes from increasing to decreasing, so the current detection voltage Vis starts rising toward 0V. At the off timing (time t2) of the output transistor N1, as long as there is no IS-GND short, Vis<Vth112 (eg, -10 mV), so ZCD=L, and the ground fault detection signal Sd goes high ( = normal logical level). Therefore, the next turn-on timing of the output transistor N1 is determined based on the zero current detection signal ZCD.

Also, when the output transistor N1 is turned off, the ramp voltage Vramp is reset to a zero value. Further, since the discharge of the capacitor 114b is stopped as the output transistor N1 is turned off, the charging voltage Vt starts to rise with a predetermined slope.

Thereafter, the coil current IL continues to decrease, and when Vis>Vth112 is satisfied at time t3, ZCD=H. Therefore, the output transistor N1 is turned on again at time t4 when the delay time Tdelay has elapsed from that time. Since the capacitor 114b is discharged with the turn-on of the output transistor N1, the charging voltage Vt is reset to 0V before exceeding the logic inversion level BUFth of the buffer (=inverters 114d and 114e). Therefore, the timer output signal TMRO never rises to the high level.

Even after time t4, if IS-GND short-circuit does not occur, the above switching control in the critical mode should continue. However, in this figure, an IS-GND short occurs after time t3, and as a result, the current detection voltage Vis is stuck at 0V (>Vth112). In such a situation, when the error voltage Veo becomes higher than the ramp voltage Vramp and the output transistor N1 is turned off (time t5), Vis>Vth112 is already satisfied.

Therefore, if the function of setting the minimum off period Toff_min of the output transistor N1 is not introduced, the output transistor N1 that has just been turned off at time t5 is immediately turned on, and excessive electrical energy is applied to the coil L1. It accumulates and leads to heat generation and destruction of the output transistor N1.

In order to solve such a problem, the controller IC 100 of this configuration example has a function of detecting a ground fault of the current detection terminal IS when the output transistor N1 is turned off, and setting the minimum off period Ton_min of the output transistor N1 when a ground fault occurs. has been introduced.

More specifically, when the IS-GND short occurs, at the off timing (time t5) of the output transistor N1, since Vis>Vth112, VCD=H, and the ground fault detection signal Sd becomes It becomes low level (=logical level at the time of abnormality). Therefore, the ON timing of the output transistor N1 after time t5 is determined based on the timer output signal TMRO instead of the zero current detection signal ZCD.

Referring to this figure, as the output transistor N1 is turned off (NO=H) at time t5, the discharge of the capacitor 114b is stopped, so the charge voltage Vt begins to rise with a predetermined slope. At time t6, when the charging voltage Vt rises to exceed the logic inversion level BUFth of the buffer (=inverters 114d and 114e), the timer output signal TMRO is raised to a high level, turning on the output transistor N1. be done.

After time t6, the ON timing of the output transistor N1 is set according to the timer output signal TMRO as long as the IS-GND short circuit is not resolved. On the other hand, the turn-off timing of the output transistor N1 is set according to the comparison result between the error voltage Veo and the ramp voltage Vramp (see time t7).

As described above, when the IS-GND is shorted, the timer 114 is used to forcibly ensure the minimum OFF period Toff_min of the output transistor N1. Therefore, the electric energy (=current) of the coil L1 can be discharged during the minimum off period Toff_min, so that it is possible to prevent the output transistor N1 from being heated or destroyed.

<Operating state transition>
FIG. 5 is a state machine diagram showing operation state transitions of the switching power supply 1 described so far. In the figure, "OUT ON" indicates the high level period of the output terminal OUT (=on period of the output transistor), and "OUT OFF" indicates the low level period of the output terminal OUT (=off period of the output transistor N1). ). Also, "ZCD" in the figure indicates an on-timing setting operation according to the zero current detection signal ZCD, and "TMR" indicates an on-timing setting operation according to the timer output signal TMRO.

As described above, when Vis<Vth112 at the off timing of the output transistor N1, the on timing setting operation is performed based on the zero current detection signal ZCD under the judgment that the IS-GND short has occurred. , the output transistor N1 is shifted to the ON period.

On the other hand, when Vis>Vth112 at the off-timing of the output transistor N1, it is determined that IS-GND short-circuit has occurred. setting operation), the output transistor N1 is shifted to the ON period.

<Effect of introduction of minimum off period setting function>
FIG. 6 is a diagram showing the behavior at the time of IS-GND shorting when the setting function of the minimum OFF period Toff_min is not introduced. signal G1), the coil current IL, the drain current Id, and the terminal voltage of the current detection terminal IS (=corresponding to the current detection voltage Vis). In this figure, the left side of the dashed line is the normal state, and the right side of the dashed line is the abnormal state (=IS-GND short state).

As shown on the right side of the dashed line in this figure, if the minimum OFF period Toff_min setting function is not introduced, it is assumed that the coil current IL is always zero when an IS-GND short (IS=0V) occurs. This is erroneously detected and immediately turns on the output transistor N1 which has just been turned off. Therefore, the OFF period of the output transistor N1 is almost eliminated, and the coil current IL and the drain current Id continue to rise. If the electric energy (=current) that cannot be discharged continues to accumulate in the coil L1 in this way, the stress on the output transistor N1 increases, leading to heat generation and destruction of the output transistor N1.

FIG. 7 is a diagram showing the behavior at the time of IS-GND shorting when the minimum OFF period Toff_min setting function has already been introduced. The voltage (=corresponding to the gate signal G1 of the output transistor N1), the coil current IL, the drain current Id, and the terminal voltage of the current detection terminal IS (=corresponding to the current detection voltage Vis) are depicted. In this figure, the left side of the dashed line is the normal state, and the right side of the dashed line is the abnormal state (=IS-GND short state).

As shown on the right side of the dashed line in this figure, if the minimum OFF period Toff_min setting function has already been introduced, the OFF period Toff of the output transistor N1 is ensured even if an IS-GND short (IS=0V) occurs. be done. Therefore, unlike FIG. 6, the electric energy accumulated in the coil L1 can be properly discharged, so that the coil current IL and the drain current Id do not continue to rise, and the stress on the output transistor N1 is reduced. mitigated.

Note that the function of setting the minimum OFF period Toff_min when the current detection terminal IS is grounded is not limited to the PFC circuit exemplified in the above embodiment, but the critical mode switching power supply (and the controller IC used therefor). It can be widely introduced in general. Also, for the switch output stage of the switching power supply, it is possible to adopt various output types (positive boost type, negative boost type, buck type, buck-boost type, inverting type, etc.). / non-insulated).

<Error amplifier (first embodiment)>
Further, the error amplifier 101 of FIG. 2 includes an over-boost suppression unit for suppressing over-boost when the switching power supply 1 is started (especially when started under a light load state or no load state). The configuration and operation thereof will be described in detail below.

FIG. 8 is a diagram showing a first embodiment of the error amplifier 101. As shown in FIG. The error amplifier 101 of this embodiment includes a differential input stage 101a, a current output stage 101b, an auxiliary source current generation section 101c, an auxiliary sink current generation section 101d, and an over-voltage suppression section 101e.

The differential input stage 101a responds to the difference (=|Vfb-Vref|) between the feedback voltage Vfb input to the inverting input terminal (-) and the reference voltage Vref input to the non-inverting input terminal (+). A current control signal Sa is generated. The current control signal Sa is a voltage signal that can take both positive and negative values with the output bias point of the differential input stage 101a as a reference value (=zero value). More specifically, when Vfb<Vref, the current control signal Sa increases in the positive direction as the difference between the two increases. Conversely, when Vfb>Vref, the larger the difference between the two, the higher the current control signal Sa in the negative direction. When the DC output voltage Vo is within the input dynamic range of the differential input stage 101a, instead of the feedback voltage Vfb (=divided voltage of the DC output voltage Vo), the DC output voltage Vo is applied to the differential input. A direct input to stage 101a may also be used.

The current output stage 101b includes current sources b1 and b2, and generates a source current IU1 (eg, maximum 30 μA) and a sink current ID1 (eg, maximum 30 μA) according to the current control signal Sa input from the differential input stage 101a. do. The current source b1 is connected between the power supply terminal and the phase compensation terminal EO (=the output terminal of the error voltage Veo), and generates the source current IU1 according to the positive current control signal Sa. Therefore, when Vfb<Vref, the source current IU1 flows from the power supply end toward the phase compensation terminal EO, so the error voltage Veo rises. On the other hand, the current source b2 is connected between the phase compensation terminal EO and the ground terminal, and generates a sink current ID1 according to the negative current control signal Sa. Therefore, when Vfb>Vref, the sink current ID1 is drawn from the phase compensation terminal EO toward the ground terminal, so the error voltage Veo is lowered.

The auxiliary source current generator 101c includes PMOSFETs c1 to c3 and a current source c4, and generates an auxiliary source current IU2 (eg, 20 μA) according to the gain up signal GUP. As for the circuit configuration, the sources and back gates of PMOSFETs c1 and c2 are connected to the power supply terminal. The gates of PMOSFETs c1 and c2 are connected to the drain of PMOSFET c1. A current source c4 is connected between the drain of the PMOSFET c1 and the ground terminal. The drain of PMOSFET c2 is connected to the source of PMOSFET c3. The drain of the PMOSFETc3 is connected to the phase compensation terminal EO (=the output terminal of the current output stage 101b). The gate of the PMOSFETc3 is connected to the input end of the gain-up signal GUP. The back gate of PMOSFETc3 is connected to the power supply terminal.

In the auxiliary source current generator 101c of this configuration example, the PMOSFETs c1 and c2 function as a current mirror that mirrors the drain current of the PMOSFET c1 (=constant current generated by the current source c4) as the drain current of the PMOSFET c2. Also, the PMOSFET c3 functions as a switching element for conducting/disconnecting between the drain of the PMOSFET c2 and the phase compensation terminal EO according to the gain up signal GUP.

When GUP=L (that is, Vfb<Vth102), the PMOSFET c3 is turned on, thereby conducting between the drain of the PMOSFET c2 and the phase compensation terminal EO. As a result, the auxiliary source current IU2 is supplied to the phase compensation terminal EO in addition to the source current IU1 of the current output stage 101b, so that the error voltage Veo tends to increase.

On the other hand, when GUP=H (that is, Vfb>Vth102), the PMOSFET c3 is turned off, so that the connection between the drain of the PMOSFET c2 and the phase compensation terminal EO is cut off. As a result, the auxiliary source current IU2 does not flow into the phase compensation terminal EO.

As described above, the auxiliary source current generator 101c generates the auxiliary source current IU2 when the feedback voltage Vfb is lower than the threshold voltage Vth102 (=first threshold voltage) lower than the reference voltage Vref. The current sourcing capability of error amplifier 101 is enhanced. Therefore, for example, when the DC output voltage Vo drops due to an increase in the load, the error voltage Veo is quickly raised to increase the on-duty Don (=Ton/T) of the output transistor N1, where Ton is the ON period of the output transistor N1, and T is switching cycle) can be increased, it is possible to minimize transient fluctuations in the DC output voltage Vo.

The auxiliary sink current generator 101d includes NMOSFETs d1 to d3, a current source d4, and an inverter d5, and generates an auxiliary sink current ID2 (eg, 20 μA) according to the overvoltage protection signal DOVP. Regarding the circuit configuration, the sources and back gates of NMOSFETs d1 to d3 are all connected to the ground terminal. The gates of NMOSFETs d1 and d2 and the drain of NMOSFET d3 are both connected to the drain of NMOSFET d1. A current source d4 is connected between the drain of the NMOSFET d1 and the power supply terminal. The drain of the NMOSFET d2 is connected to the phase compensation terminal EO (=output terminal of the current output stage 101b). The gate of the NMOSFET d3 is connected to the output end of the inverter d5 (=the output end of the inverted overcurrent protection signal DOVPB). The input end of the inverter d5 is connected to the input end of the overcurrent protection signal DOVP.

In the auxiliary sink current generator 101d of this configuration example, NMOSFETs d1 and d2 function as a current mirror that mirrors the drain current of NMOSFET d1 (=constant current generated by current source d4) as the drain current of PMOSFET d2. Further, the NMOSFET d3 switches between valid/invalid of the current mirror by conducting/interrupting between the drain and source of the NMOSFET d1 according to the inverted overcurrent protection signal DOVPB (=logically inverted signal of the overcurrent protection signal DOVP). It functions as a switching element for

When DOVPB=L (that is, Vfb>Vth103), the NMOSFET d3 is turned off, so that the drain-source of the NMOSFET d1 is shut off and the current mirror becomes effective. As a result, the auxiliary sink current ID2 is drawn from the phase compensation terminal EO in addition to the sink current ID1 of the current output stage 101b, so the error voltage Veo tends to decrease.

On the other hand, when DOVPB=H (that is, Vfb<Vth103), the NMOSFET d3 is turned on, so that the drain and source of the NMOSFET d1 are conducted and the current mirror is disabled. As a result, the auxiliary sink current ID2 is no longer drawn from the phase compensation terminal EO.

In this manner, the auxiliary sink current generator 101d generates the auxiliary sink current ID2 when the feedback voltage Vfb exceeds the threshold voltage Vth103 (=second threshold voltage) higher than the reference voltage Vref. The current sinking capability of error amplifier 101 is enhanced. Therefore, when the DC output voltage Vo shows a sign of an overvoltage abnormality, the error voltage Veo can be quickly lowered to reduce the on-duty Don of the output transistor N1. ) is applied, it is possible to suppress an increase in the DC output voltage Vo.

The over-boosting suppressing unit 101e includes a filter e1, D flip-flops e2 and e3, an inverter e4, AND gates e5 and e6, an NMOSFET e7, and a resistor e8. to forcibly lower the on-duty Don of the output transistor N1.

The filter e1 applies a predetermined masking process to the pulse width modulated signal PWM to generate an internal signal Se1. More specifically, when a pulse with a switching period T appears in the pulse width modulated signal PWM, the internal signal Se1 is maintained at a low level. On the other hand, the error voltage Veo falls below the lower limit value of the ramp voltage Vramp (=corresponding to the discharge stop voltage, for example 0.3 V), and the pulse width modulation signal PWM is at a high level (= N1 off logic level), that is, the switching power supply 1 is in burst mode (= power saving mode for thinning out pulses of the pulse width modulation signal PWM to increase efficiency in light load or no load state). ), the internal signal Se1 rises to a high level.

The D flip-flop e2 takes in the logic level (=always H) of the data signal input to the data terminal at the rise timing of the gain-up signal GUP input to the clock terminal, and latches it from the output terminal as an internal signal Se2. Output. Also, the D flip-flop e2 resets the internal signal Se2 to low level when the low voltage protection signal UVLO input to the reset terminal is at low level (=logic level during UVLO operation).

The D flip-flop e3 changes the logic level (=always H) of the data signal input to the data end at the rising timing of the internal signal Se5 (=the AND signal of the internal signal Se1 and the internal signal Se2) input to the clock end. ) is taken in and latched out as an internal signal Se3 from the output terminal. Also, the D flip-flop e3 resets the internal signal Se3 to low level when the low voltage protection signal UVLO input to the reset terminal is at low level (=logic level during UVLO operation).

The inverter e4 logically inverts the internal signal Se3 to generate an internal signal Se4. Therefore, when Se3=L, Se4=H, and when Se3=H, Se4=L.

AND gate e5 generates a logical AND signal of internal signal Se1 and internal signal Se2, and outputs this as internal signal Se5. Therefore, when at least one of the internal signals Se1 and Se2 is low level, the internal signal Se5 is low level, and when both the internal signals Se1 and Se2 are high level, the internal signal Se5 is high level.

AND gate e6 generates a logical product signal of gain up signal GUP and internal signal Se4, and outputs this as discharge control signal DCHG. Therefore, when Se4=H, DCHG=GUP, and when Se4=L, DCHG=L fixed.

The drain of the NMOSFET e7 is connected to the phase compensation terminal EO (=the output terminal of the error voltage Veo) through the resistor e8. Both the source and the back gate of NMOSFET e7 are connected to the ground terminal. A discharge control signal DCHG is input to the gate of the NMOSFET e7. Therefore, NMOSFET e7 turns on when DCHG=H and turns off when DCHG=L. The NMOSFET e7 connected in this manner functions as a discharge switch that discharges the error voltage Veo according to the discharge control signal DCHG.

A resistor e8 is a current limiting element (eg, 4 kΩ) for limiting the discharge current flowing through the NMOSFET e7 so that it does not become excessive.

In this figure, for convenience of explanation, the over-voltage suppression unit 101e is depicted as a component of the error amplifier 101, but the error amplifier 101 and the over-voltage suppression unit 101e may be understood as separate and independent circuit blocks. Absent. The error voltage discharge operation by the over-voltage suppression unit 101e and its technical significance will be described below.

<Error voltage discharge operation>
FIG. 9 is a timing chart showing an example of the forced discharge operation of the error voltage Veo by the over-boost suppression unit 101e. Signal Se1, gain-up signal GUP, internal signal Se2, internal signal Se4, discharge control signal DCHG, error voltage Veo, and feedback voltage Vfb are depicted.

Since the feedback voltage Vfb is lower than the threshold voltage Vth102 before time t11 while the switching power supply 1 is starting up, the gain-up signal GUP is at low level (=logic level when increasing the source current). Therefore, since the current source capability of the error amplifier 101 is enhanced, the error voltage Veo rises relatively sharply.

Note that when GUP=L, DCHG=L, so that the error voltage Veo is not discharged. Further, while the error voltage Veo is higher than the lower limit value of the ramp voltage Vramp and the pulse width modulation signal PWM (and thus the output terminal OUT) is being pulse-driven, the internal signal Se1 is maintained at a low level. . Since neither of the D flip-flops e2 and e4 receives a clock pulse, Se2=L and Se4=H.

After that, at time t11, when the feedback voltage Vfb exceeds the threshold voltage Vth102, the gain-up signal GUP rises to high level (=logical level when the source current is stationary). As a result, the current sourcing capability of error amplifier 101 is returned to a steady state. At time t12, the internal signal Se2 is latched to a high level as the gain-up signal GUP rises. Note that once the internal signal Se2 is latched to a high level, it is maintained at a high level until the low voltage protection signal UVLO falls to a low level.

At time t12, the discharge control signal DCHG rises to high level as both the gain amplifier signal GUP and the internal control signal Se4 become high level. Therefore, the NMOSFET e7 is turned on to start discharging the error voltage Veo. That is, when the feedback voltage Vfb exceeds the threshold voltage Vth102 (=corresponding to the discharge start voltage) while the switching power supply 1 is starting up, the over-voltage suppression unit 101e starts forcibly discharging the error voltage Veo.

As described above, in the switching power supply 1 of the present embodiment, the discharge start voltage of the over-boost suppression unit 101e is set to the same value as the GUP threshold voltage Vth102. In other words, the single comparator 102 is shared by both the auxiliary source current generation section 101c and the overvoltage suppression section 101e, and the gain-up signal GUP is diverted as a discharge start trigger signal for the error voltage Veo. By adopting such a configuration, the chip size of the controller IC 100 can be prevented from being unnecessarily increased when the overvoltage suppression unit 101e is introduced.

After that, the discharge of the error voltage Veo progresses, and at time t13, when the error voltage Veo falls below the lower limit value of the ramp voltage Vramp (=corresponding to the discharge stop voltage), the pulse width modulation signal PWM (and eventually the output terminal OUT) Since the pulse drive is stopped, the internal signal Se1 rises to high level. As a result, the internal signal Se5 rises to high level, the internal signal Se3 is latched to high level, and the internal signal Se4 falls to low level.

At this time, since Se4=L, the discharge control signal DCHG falls to a low level, so that the NMOSFET e7 is turned off and the discharge operation of the error voltage Veo is stopped. That is, when the error voltage Veo falls below a predetermined discharge stop voltage, the over-voltage suppression unit 101e, for example, according to the present embodiment in which the discharge stop voltage is set to the lower limit value of the ramp voltage Vramp, is as follows: Forced discharge of the error voltage Veo is stopped when the pulse width modulation signal PWM is fixed at a high level (=logic level when N1 is off). Therefore, after time t13, the error voltage Veo begins to rise again.

After that, at time t14, when the error voltage Veo exceeds the lower limit value of the ramp voltage Vramp, pulse driving of the pulse width modulation signal PWM (and the output terminal OUT) is resumed. However, at this time, since the gain-up of the error amplifier 101 has already been completed, the error voltage Veo gently rises from a sufficiently low voltage value. Therefore, it is possible to keep the switching power supply 1 started while keeping the on-duty Don of the output transistor N1 small, so that it is possible to suppress excessive boosting of the DC output voltage Vo.

Note that once the internal signal Se3 is latched to a high level, it is maintained at a high level until the low voltage protection signal UVLO falls to a low level. Therefore, the internal signal Se4 is maintained at low level, and the discharge control signal DCHG is also maintained at low level (=logical level at the time of forced discharge stop). By adopting such a latch configuration, the forced discharge operation of the error voltage Veo by the overvoltage suppression unit 101e becomes effective only once when the switching power supply 1 is started.

<Effect of introduction of error voltage discharge function>
FIG. 10 is a diagram showing the output behavior at startup when the error voltage discharge function by the over-voltage suppression unit 101e is not introduced. , the terminal voltage of the output terminal OUT (=corresponding to the gate signal G1 of the output transistor N1).

As shown in the figure, at time t21, when the DC output voltage Vo exceeds its target value, the error voltage Veo changes from increasing to decreasing. However, if the error voltage discharging function by the over-boost suppression unit 101e is not introduced, the error voltage Veo cannot be lowered quickly, the pulse width of the gate signal G1 remains large, and the DC output voltage Vo becomes excessive. fall into a boosted state. In particular, the above-mentioned problem becomes conspicuous at the time of start-up in a light load state or no load state. 1 is interrupted.

FIG. 11 is a diagram showing the output behavior at startup when the error voltage discharge function by the over-voltage suppression unit 101e has already been introduced. The error voltage Veo and the terminal voltage of the output terminal OUT (=corresponding to the gate signal G1 of the output transistor N1) are depicted.

If the error voltage discharge function by the overvoltage suppression unit 101e is not introduced, at time t31, when the DC output voltage Vo exceeds a predetermined threshold value (for example, 90% of the target value), the error voltage Veo is forcibly discharged. is discharged effectively. As a result, after the on-duty Don of the output transistor N1 is lowered to the minimum value, the step-up operation thereafter is gradually resumed.

Note that the over-boost suppression unit 101e that forcibly discharges the error voltage Veo while the switching power supply 1 is starting up is much smaller than a general soft-start circuit (for example, one that gently changes the reference voltage Vref). be. Therefore, the chip size of the controller IC 100 does not need to be increased when the overvoltage suppression unit 101e is introduced.

<Error amplifier (second embodiment)>
FIG. 12 is a diagram showing a second embodiment of the error amplifier 101. As shown in FIG. The error amplifier 101 of the present embodiment is based on the first embodiment (FIG. 8), and is provided with an overvoltage suppression unit 101f instead of the overvoltage suppression unit 101e, and a current output stage 101b and an auxiliary source current generator. Changes have been made to section 101c. Therefore, the same reference numerals as those in FIG. 8 are used for the components that have already been described to omit redundant description, and the characteristic portions of the present embodiment will be mainly described below.

Current output stage 101b includes current sources b1X and b1Y and PMOSFET b3 instead of current source b1 in FIG.

The current source b1X is connected between the power supply end and the phase compensation terminal EO, and generates the source current IU1X in response to the positive current control signal Sa, like the current source b1 in FIG. On the other hand, the current source b1Y is connected between the power supply end and the source of the PMOSFET b3, and always generates the source current IU1Y without depending on the current control signal Sa.

The current values of the source currents IU1X and IU1Y are set so that the sum of both of them becomes the same value as the source current IU1 (for example, maximum 30 μA) (for example, IU1X=maximum 15 μA, IU1Y=15 μA).

The drain of PMOSFETb3 is connected to the phase compensation terminal EO. An internal signal Sf3 is input to the gate of the PMOSFETb3 from the over-boost suppression unit 101f. The back gate of PMOSFETb3 is connected to the power supply end. The PMOSFET b3 connected in this manner functions as a switching element for conducting/disconnecting between the current source b1Y and the phase compensation terminal EO according to the internal signal Sf3.

When Sf3=L, the PMOSFET b3 is turned on, thereby conducting between the current source b1Y and the phase compensation terminal EO. As a result, the source current IU1Y flows into the phase compensation terminal EO together with the source current IU1X. That is, when Sf3=L, the current source capability of the error amplifier 101 becomes equal to that of the first embodiment (FIG. 8).

On the other hand, when Sf3=H, the PMOSFET b3 is turned off, so that the connection between the current source b1Y and the phase compensation terminal EO is cut off. As a result, the source current IU1Y does not flow into the phase compensation terminal EO. That is, when Sf3=L, the current source capability of the error amplifier 101 is lower than that of the first embodiment (FIG. 8).

The auxiliary source current generator 101c includes a PMOSFETc5 instead of the PMOSFETc3. The source and backgate of PMOSFETc5 are connected to the power supply terminal. The drain of PMOSFET c5 is connected to the drain of PMOSFET c1. An internal signal Sf2 is input to the gate of the PMOSFET c5 from the over-boost suppression unit 101f. Due to the above change, the drain of the PMSOFETc2 is directly connected to the phase compensation terminal EO.

In the auxiliary source current generation unit 101c of this configuration example, the PMOSFET c5 is for switching between valid/invalid of the current mirror composed of the PMOSFETs c1 and c2 by conducting/interrupting the drain-source of the PMOSFET c1 according to the internal signal Sf2. Functions as a switch element.

When Sf2=H, the PMOSFET c5 is turned off, so that the drain-source of the PMOSFET c1 is shut off and the current mirror becomes effective. As a result, the auxiliary source current IU2 flows into the phase compensation terminal EO in addition to the source currents IU1X+IU1Y of the current output stage 101b, so that the error voltage Veo tends to rise.

On the other hand, when Sf2=L, the PMOSFET c5 is turned on, so that the drain and source of the PMOSFET c1 are electrically connected to disable the current mirror. As a result, the auxiliary source current IU2 will not flow into the phase compensation terminal EO.

The over-voltage suppression unit 101f includes a D flip-flop f1, a selector f2, and an inverter f3, and only when the switching power supply 1 is activated, until the feedback voltage Vfb exceeds the GUP threshold voltage Vth2 (<Vref), The gain of the error amplifier 101 is forcibly lowered from that in the steady state.

The D flip-flop f1 takes in the logic level (=always H) of the data signal input to the data terminal at the rise timing of the gain-up signal GUP input to the clock terminal, and latches it from the output terminal as an internal signal Sf1. Output. Also, the D flip-flop f1 resets the internal signal Sf1 to low level when the low voltage protection signal UVLO input to the reset terminal is at low level (=logic level during UVLO operation).

The selector f2 selects either the gain-up signal GUP or the fixed low-level signal (eg, GND) according to the internal signal Sf1 and outputs it as the internal signal Sf2. More specifically, when Sf1=H, Sf2=GUP, and when Sf1=L, Sf2=L fixed.

Inverter f3 logically inverts internal signal Sf1 to generate internal signal Sf3. Therefore, when Sf1=L, Sf3=H, and when Sf1=H, Sf3=L.

When the over-boost suppression unit 101f having the configuration described above is introduced, Sf1=L, Sf2=L, Sf1=L, Sf2=L, and while the feedback voltage Vfb is lower than the threshold voltage Vth102 (GUP=L) at the start-up of the switching power supply 1, Sf3=H. Therefore, the current output stage 101b turns off the PMOSFETb3 to output only the source current IU1X. Further, the auxiliary source current generator 101c disables the current mirror composed of the PMOSFETs c1 and c2 and stops generating the auxiliary source current IU2. Such a state corresponds to a state in which the gain of the error amplifier 101 is forcibly lowered from that in the steady state. As a result, when the switching power supply 1 is started, the on-duty Don of the output transistor N1 is gradually increased, so that excessive boosting of the DC output voltage Vo can be suppressed.

Thereafter, when the switching power supply 1 is started up and the feedback voltage Vfb exceeds the threshold voltage Vth102, GUP=H, so Sf1=H, Sf2=GUP, and Sf3=L. Therefore, the current output stage 101b turns on the PMOSFET b3 to add and output the source current IU1X and the source current IU1Y. In addition, the auxiliary source current generation unit 101c enables the current mirror composed of PMOSFETs c1 and c2, and becomes capable of outputting the auxiliary source current IU2 according to the gain-up signal GUP. Such a state corresponds to a state in which the forcible gain reduction of the error amplifier 101 is cancelled. Therefore, subsequent output feedback control can be performed without delay.

The above source current limiting operation will be specifically described. For example, in the switching power supply 1 of this embodiment, the current source capability of the error amplifier 101 is limited to 15 μA (=IU1X only) while Vfb<Vth102. After that, when Vfb>Vth102, the current source capability of the error amplifier 101 is restored to the steady-state value of 30 μA (=IU1X+IU1Y). After that, when Vfb<Vth102, the current source capability of the error amplifier 101 is increased to 50 μA (=IU1X+IU1Y+IU2).

Note that once the internal signal Sf1 is latched to a high level, it is maintained at a high level until the low voltage protection signal UVLO falls to a low level. It remains held at a low level. By adopting such a latch configuration, the source current limiting operation of the overvoltage suppression unit 101f becomes effective only once when the switching power supply 1 is started.

It should be noted that the over-boost suppression units 101e and 101f are not limited to the PFC circuit exemplified in the above embodiment, and can be widely introduced into boost-type switching power supplies (and controller ICs used therein). . In addition, the type of insulation (insulation/non-insulation) of the switch output stage is also irrelevant.

Also, when introducing the over-voltage suppression units 101e and 101f, the auxiliary source current generation unit 101c and the auxiliary sink current generation unit 101d are not essential components, and switching power supplies that do not have one or both of these may also be used. It can be widely introduced.

<Other Modifications>
In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. For example, the mutual replacement of bipolar transistors with MOS field effect transistors and the logic level inversion of various signals are optional. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments, and the claims should be understood to include all changes falling within the meaning and range of equivalence to the range of.

The invention disclosed herein can be used, for example, in a critical mode PFC controller IC.

1 Switching power supply (PFC circuit)
100 Controller IC
101 error amplifier 101a differential input stage 101b current output stage b1, b1X, b1Y, b2 current source b3 PMOSFET
101c Auxiliary source current generator c1 to c3, c5 PMOSFET
c4 current source 101d auxiliary sink current generator d1-d3 NMOSFET
d4 current source d5 inverter 101e over-boosting suppressor e1 filter e2, e3 D flip-flop e4 inverter e5, e6 AND gate e7 NMOSFET
e8 resistor 101f over-boost suppressor f1 D flip-flop f2 selector f3 inverter 102 comparator (GUP)
103 Comparator (DOVP)
104 Comparator (SP)
105 Comparator (SOVP)
106 NMOSFETs
107 Main comparator 108 Oscillator 109 Comparator (RT_H)
110 Comparator (RT_L)
111 Comparator (ISOCP)
112 Zero current detector (ZCD)
112a Comparator 112b-112e Resistor 112f NMOSFET
113 signal delay unit 113a current source 113b capacitor 113c NMOSFET
113d inverter 114 timer 114a current source 114b capacitor 114c NMOSFET
114d to 114f inverter 115 selector 115a, 115b AND gate 115c OR gate 115d D flip-flop 115e inverter 116 OR gate 117 RS flip-flop 118 AND gate 119 pre-driver 120 clamper 121 PMOSFET
122 NMOSFETs
123 resistor 124 comparator (OVP)
125 Inverter 126 Zener diode 127 Comparator (UVLO)
128 reference voltage source 129 reference voltage buffer 130 regulator 131 temperature protection unit 200 on-timing setting unit N1 output transistor (NMOSFET)
R1~R10 Resistor C1~C10 Capacitor D1, D2 Diode L1 Coil F1 Fuse FLT Filter DB Diode bridge

Claims (10)

a current detection terminal for detecting coil current flowing in the switching power supply;
A ground fault is detected at the current detection terminal when the output transistor is off, and the output transistor is turned on when the coil current decreases to a zero value or a value close to it in a normal state, and a predetermined minimum off period elapses when the ground fault occurs. an on-timing setting unit for generating an on-timing setting signal to turn on the output transistor after the above;
A controller IC characterized by comprising: The on-timing setting unit
a zero current detection unit that compares the terminal voltage of the current detection terminal or a voltage corresponding thereto with a predetermined threshold voltage to generate a zero current detection signal;
a timer that counts the minimum off period after the output transistor is turned off and generates a timer output signal;
a selector that outputs one of the zero-current detection signal or its delayed signal and the timer output signal as the on-timing setting signal according to a ground fault detection result;
2. The controller IC according to claim 1, comprising: The selector includes a D flip-flop that latches the zero current detection signal when the output transistor is turned off, and outputs the zero current detection signal or its delayed signal and the timer output signal according to the latch output signal of the D flip-flop. 3. The controller IC according to claim 2, wherein either one is selected. 4. The controller IC according to claim 2, wherein the on-timing setting section includes a signal delay section that generates a delayed signal of the zero current detection signal and outputs the delayed signal to the selector. The signal delay unit is
a capacitor;
a current source that generates a charging current for the capacitor;
a discharge switch for discharging the capacitor in response to the zero current detection signal;
an inverter that generates the delay signal from the charged voltage of the capacitor;
5. The controller IC according to claim 4, comprising: The timer
a capacitor;
a current source that generates a charging current for the capacitor;
a discharge switch that discharges the capacitor during an ON period of the output transistor;
a buffer that generates the timer output signal from the charged voltage of the capacitor;
6. The controller IC according to any one of claims 2 to 5, comprising: The zero current detection unit is
a first resistor voltage dividing unit connected between a reference voltage application terminal and the current detection terminal for generating a divided voltage terminal voltage obtained by shifting the terminal voltage of the current detection terminal to the reference voltage side;
a second resistor voltage dividing unit connected between the reference voltage application terminal and the ground terminal for dividing the reference voltage to generate the threshold voltage;
a comparator that compares the divided voltage terminal voltage and the threshold voltage to generate the zero current detection signal;
7. The controller IC according to any one of claims 2 to 6, comprising: an error amplifier that generates an error voltage corresponding to the difference between the output voltage of the switching power supply or its divided voltage and a predetermined reference voltage;
an oscillator for generating a ramp voltage;
a main comparator that compares the error voltage and the ramp voltage to generate an off-timing setting signal;
an RS flip-flop that generates a switching control signal based on the on-timing setting signal and the off-timing setting signal;
a driver that drives the output transistor according to the switching control signal;
8. The controller IC according to any one of claims 1 to 7, comprising: a switch output stage using the output transistor to generate an output voltage from an input voltage;
a controller IC according to any one of claims 1 to 8;
A switching power supply characterized by comprising: 10. The switching power supply according to claim 9, functioning as a power factor correction circuit.

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